Elements of an FPGA fabric
Topics
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FPGA fabric architecture concepts.
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!
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Logic.
Interconnect.
I/O pins.
IOB
IOB
LE
IOB
LE
…
LE
interconnect
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FPGA-Based System Design: Chapter 3
!
!
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Configuration: bits that determine logic function +
interconnect.
CLB: combinational logic block = logic element (LE).
LUT: Lookup table = SRAM used for truth table.
I/O block (IOB): I/O pin + associated logic and
electronics.
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FPGA-Based System Design: Chapter 3
!
!
!
b
memory
a
1001
FPGA-Based System Design: Chapter 3
out
LE
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b
0
0
0
1
1
0
1
1
Input connections.
Internal function.
Typically 4 inputs.
Generally includes register.
May provide specialized logic.
Adder carry chain.
FPGA-Based System Design: Chapter 3
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Logic synthesis
out
!
!
a
LE
Coarser-grained than logic gates.
!
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Example logic element
0010
LE
Programmable:
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Lookup table:
LE
Logic element
!
!
LE
…
FPGA-Based System Design: Chapter 3
Terminology
!
LE
0
1
0
0
1
0
0
1
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How do we break the function into logic elements?
How do we implement an operation within a logic
element?
FPGA-Based System Design: Chapter 3
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Placement
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Programmable wiring
Where do we put each piece of logic in the array of logic
elements?
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!
!
LE
LE
LE
LE
LE
…
LE
LE
LE
LE
Organized into channels.
!
!
!
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FPGA-Based System Design: Chapter 3
Channels from source to destination.
Wires within the channels.
FPGA-Based System Design: Chapter 3
Programmable interconnection point
D
Many wires per channel.
Connections between wires made at programmable
interconnection points.
Must choose:
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Programmable wiring paths
Q
FPGA-Based System Design: Chapter 3
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FPGA-Based System Design: Chapter 3
Choosing a path
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Routing problems
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Global routing:
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Local routing:
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Routing metrics:
LE
!
!
!
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Which combination of channels?
Which wire in each channel?
Net length.
Delay.
LE
FPGA-Based System Design: Chapter 3
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FPGA-Based System Design: Chapter 3
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Segmented wiring
Offset segments
Length 1
Length 2
FPGA-Based System Design: Chapter 3
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I/O
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Programming technologies
Fundamental selection: input, output, three-state?
Additional features:
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!
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Register.
Voltage levels.
Slew rate.
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SRAM.
!
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Antifuse.
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Flash.
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!
!
!
Similar to SRAM but using flash memory.
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Configuration vs. programming
Must set control bits for:
!
Programmed once.
FPGA-Based System Design: Chapter 3
Configuration
!
Can be programmed many times.
Must be programmed at power-up.
!
!
FPGA-Based System Design: Chapter 3
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FPGA-Based System Design: Chapter 3
!
LE.
Interconnect.
I/O blocks.
FPGA configuration:
!
!
Bits stay at the device they
program.
A configuration bit controls a
switch or a logic bit.
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CPU programming:
!
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Instructions are fetched from a
memory.
Instructions select complex
operations.
Usually configured off-line.
!
!
Separate burn-in step (antifuse).
At power-up (SRAM).
FPGA-Based System Design: Chapter 3
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FPGA-Based System Design: Chapter 3
add r1, r2
addIR
r1, r2
memory
CPU
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Reconfiguration
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Some FPGAs are designed for fast configuration.
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FPGA fabric architecture questions
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A few clock cycles, not thousands of clock cycles.
Given limited area budget:
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Allows hardware to be changed on-the-fly.
!
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FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
FPGA-Based System Design: Chapter 3
Logic element questions
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!
!
!
!
!
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All functions of n inputs or eliminate some combinations?
What inputs go to what pieces of the function?
Any specialized logic?
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How many pins?
!
!
!
!
Maximum number of pins determined by package type.
Are pins programmed individually or in groups?
Can all pins perform all functions?
How many logic families do we support?
FPGA-Based System Design: Chapter 3
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What register features?
I/O block questions
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!
!
Adder, etc.
FPGA-Based System Design: Chapter 3
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Interconnect questions
How many inputs?
How many functions?
!
How many logic elements?
How much interconnect?
How many I/O blocks?
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How many wires in each channel?
Uniform distribution of wiring?
How should wires be segmented?
How rich is interconnect between channels?
How long is the average wire?
How much buffering do we add to wires?
FPGA-Based System Design: Chapter 3
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