SRAM-based FPGAs
Topics
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SRAM-based FPGA fabrics:
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Xilinx.
Altera.
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Program logic functions, interconnect using SRAM.
Advantages:
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Disadvantages:
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FPGA-Based System Design: Chapter 3
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SRAM burns power.
Possible to steal, disrupt configuration bits.
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FPGA-Based System Design: Chapter 3
Logic elements
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Re-programmable;
dynamically reconfigurable;
uses standard processes.
LUT-based logic element
Logic element includes combinational function +
register(s).
Use SRAM as lookup table for combinational function.
n
inputs
Lookup
table
configuration
bits
1
out
Can multiplex at output or address at input
FPGA-Based System Design: Chapter 3
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FPGA-Based System Design: Chapter 3
Example
Evaluation of SRAM-based LUT
111
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1, 1, 1, 0,
0,
1, 1, 0,
1, 0,
1, 10
0 1
!
!
FPGA-Based System Design: Chapter 3
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N-input LUT can handle function of 2n inputs.
All logic functions take the same amount of space.
All functions have the same delay.
SRAM is larger than static gate equivalent of function.
Burns power at idle.
Want to selectively add register to LE:
FPGA-Based System Design: Chapter 3
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Registers in logic elements
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Other LE features
Register may be selected into the circuit:
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Multiple logic functions in an LE.
Addition logic:
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Partitioned lookup tables.
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Configuration bit
LUT
carry chain.
LE out
D
Q
FPGA-Based System Design: Chapter 3
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FPGA-Based System Design: Chapter 3
COUT
F5IN
Xilinx Spartan-II CLB
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G3
G2
Each CLB has two identical slices.
Slice has two logic cells:
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YB
Y
G4
lookup
table
carry/
control
logic
lookup
table
carry/
control
logic
D
Q
YQ
G1
BY
LUT.
Carry logic.
Registers.
SR
YB
Y
F4
F3
F2
D
Q
YQ
F1
BX
CE
CLK
FPGA-Based System Design: Chapter 3
CIN
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Spartan-II CLB details
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Spartan-II CLB operation
Each lookup table can be used as a 16-bit synchronous
RAM or 16-bit shift register.
Arithmetic logic includes an XOR gate.
Each slice includes a mux to ocmbine the results of the
two functino generators in the slice.
Register can be configured as DFF or latch.
Has three-state drivers (BUFTs) for on-chip busses.
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Arithmetic:
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Carry block includes XOR gate.
Use LUT for carry, XOR for sum.
Each slice uses F5 mux to combine results of multiplexers.
F6 mux combines outputs of F5 muxes.
Registers can be FF/latch; clock and clock enable.
Includes three-state output for on-chip bus.
FPGA-Based System Design: Chapter 3
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Altera APEX II logic element
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data1
data2
data3
data4
Each logic array block has 10 logic elements.
Logic elements share some logic.
lookup
table
labclr1
carry in
cascade in
carry
chain
cascade
chain
load
clear
synchronous
load/clear
logic
D
Q
asynchronous
clear/preset/
load logic
labclr2
chip
reset
labclk1
labclk2
labclkena1
labclkena2
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FPGA-Based System Design: Chapter 3
Apex II LE modes
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APEX-II LE normal mode
Modes of operation:
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Normal.
Arithmetic.
Counter.
carry in
data1
data2
cascade in
enable
4-input
lookup
table
data3
out
D
Q
data4
out
cascade out
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FPGA-Based System Design: Chapter 3
APEX-II LE arithmetic mode
cascade in
carry in
APEX-II LE counter mode
carry in
enable
synchronous load
data1
data2
3-input
lookup
table
Q
data2
enable
3-input
lookup
table
out
D
Q
out
data3
cascade out
3-input
lookup
table
carry out
FPGA-Based System Design: Chapter 3
synchronous clear
data1
out
3-input
lookup
table
cascade in
out
D
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FPGA-Based System Design: Chapter 3
cascade out
carry out
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FPGA-Based System Design: Chapter 3
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APEX-II LE control logic
Programmable interconnect
dedicated
clocks
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MOS switch controlled by configuration bit:
fast global
signals
local
interconnect
D
Q
local
interconnect
local
interconnect
local
interconnect
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FPGA-Based System Design: Chapter 3
Programmable vs. fixed interconnect
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Switch adds delay.
Transistor off-state is worse in advanced technologies.
FPGA interconnect has extra length = added capacitance.
Interconnect strategies
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Some wires will not be utilized.
Congestion will not be same throughout chip.
Types of wires:
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FPGA-Based System Design: Chapter 3
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LE
LE
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Interconnect architecture
Connection may be long, complex:
LE
Short wires: local LE connections.
Global wires: long-distance, buffered communication.
Special wires: clocks, etc.
FPGA-Based System Design: Chapter 3
Paths in interconnect
!
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FPGA-Based System Design: Chapter 3
LE
Connections from wiring channels to LEs.
Connections between wires in the wiring channels.
LE
Wiring channel
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
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LE
FPGA-Based System Design: Chapter 3
LE
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Interconnect richness
Within a channel:
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channel
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Switchbox
How many wires.
Length of segments.
Connections from LE to channel.
Between channels:
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channel
Number of connections between channels.
Channel structure.
channel
channel
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FPGA-Based System Design: Chapter 3
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Spartan-II interconnect
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Spartan-II general-purpose network
Types of interconnect:
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local;
general-purpose;
dedicated;
I/O pin.
Provides majority of routing resources:
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FPGA-Based System Design: Chapter 3
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General routing matrix (GRM) connects horizontal/vertical
channels and CLBs.
Interconnect between adjacent GRMs.
Hex lines connect GRM to GRMs six blocks away.
12 longlines span the chip.
Spartan-II three-state bus
Relationship
between GRM, hex
lines, and local
interconnect:
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Horizontal on-chip busses:
CLB
FPGA-Based System Design: Chapter 3
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FPGA-Based System Design: Chapter 3
Spartan-II routing
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FPGA-Based System Design: Chapter 3
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FPGA-Based System Design: Chapter 3
CLB
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Spartan-II clock distribution
APEX II interconnect
clock pin
row interconnect
clock rows
clock rows
MegaLAB interconnect
row
clock spine
FPGA-Based System Design: Chapter 3
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column interconnect
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
LE
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LVTTL, PCI, LVCMOS2, AGP2X, etc.
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FPGA-Based System Design: Chapter 3
Configuration ROM
Need to set all configuration SRAM bits:
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LE
LE
Spartan-II I/O block diagram
Configuration
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LE
Provides registers.
Programmable delay for pin-dependent hold time.
Programmable weak keeper circuit.
FPGA-Based System Design: Chapter 3
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LE
Supports multiple I/O standards:
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LE
FPGA-Based System Design: Chapter 3
Spartan-II I/O
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LE
LE
local interconnect
clock rows
LE
LE
local interconnect
column interconnect
column
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Configured on start-up from ROM:
minimum pin cost;
reasonable speed.
Configure SRAM as shift register to read configuration
bits.
Configuration can also be read back for testing.
FPGA-Based System Design: Chapter 3
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Configuration
memory
FPGA
FPGA-Based System Design: Chapter 3
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Spartan-II configuration
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Configuration length depends on size of chip:
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Scan chain
200,000 to 1.3 million bits.
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Configuration modes:
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Master serial for first chip in chain.
Slave serial for follow-on chips.
Slave parallel.
Boundary-scan.
FPGA-Based System Design: Chapter 3
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FPGA-Based System Design: Chapter 3
JTAG boundary scan
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board
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Boundary scan concepts
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TAP: test access port.
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Boundary scan decouples chips:
provide scan chain at pins;
allow control of chip interior;
decouple chip from rest of board for test.
FPGA-Based System Design: Chapter 3
Requires three pins not shared with other logic.
Test reset, test clock, test mode select, test data in, test data out.
TAP controller recognizes pins, controls boundary scan
registers.
Instruction register defines boundary scan mode.
FPGA-Based System Design: Chapter 3
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Chip-on-board testing
JTAG: Joint Test Action Group.
Boundary scan:
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Scan chain: shift register used to access internal state.
Logic-sensitive scan design (LSSD): scan structure that
uses some hardware for normal mode and scan.
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FPGA-Based System Design: Chapter 3
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