Supertex inc.
TD9944
Dual N-Channel Enhancement-Mode
Vertical DMOS FET
Features
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General Description
Dual N-channel devices
Low threshold – 2.0V max.
High input impedance
Low input capacitance – 125pF max.
Fast switching speeds
Low on-resistance
Free from secondary breakdown
Low input and output leakage
This low threshold, enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven, silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and the high input
impedance and positive temperature coefficient inherent
in MOS devices. Characteristic of all MOS structures, this
device is free from thermal runaway and thermally-induced
secondary breakdown.
Applications
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Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
Ordering Information
Product Summary
Part Number
Package Option
Packing
TD9944TG-G
8-Lead SOIC
2000/Reel
BVDSS/BVDGS
240V
-G denotes a lead (Pb)-free / RoHS compliant package.
Absolute Maximum Ratings
Value
Drain-to-source voltage
BVDSS
Drain-to-gate voltage
BVDGS
Gate-to-source voltage
±20V
Typical Thermal Resistance
TO-243AA (SOT-89)
θja
133OC/W
Note:
Mounted on FR5 Board, 25mm x 25mm x 1.57mm
Doc.# DSFP-TD9944
B080713
VGS(th)
(max)
(min)
(max)
6.0Ω
D1
D1
D2
-55OC to +150OC
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
Package
ID(ON)
1.0A
2.0V
Pin Configuration
Parameter
Operating and storage temperature
RDS(ON)
D2
S1
G1
S2
G2
8-Lead SOIC
Product Marking
TD99
44TG
YYWW
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
Package may or may not include the following marks: Si or
8-Lead SOIC
Supertex inc.
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TD9944
Electrical Characteristics (T
A
= 25OC unless otherwise specified)
Sym
Parameter
Min
Typ
Max
Units
BVDSS
Drain-to-source breakdown voltage
240
-
-
V
VGS = 0V, ID = 2.0mA
VGS(th)
Gate threshold voltage
0.6
-
2.0
V
VGS = VDS, ID= 1.0mA
Change in VGS(th) with temperature
-
-
-5.0
Gate body leakage
-
-
100
nA
VGS = ± 20V, VDS = 0V
-
-
10
µA
VGS = 0V, VDS = Max Rating
-
-
1.0
mA
VDS = 0.8Max Rating,
VGS = 0V, TA = 125°C
0.5
1.9
-
1.0
2.8
-
-
4.0
6.0
-
4.0
6.0
-
-
1.4
300
600
-
ΔVGS(th)
IGSS
IDSS
Zero gate voltage drain current
ID(ON)
ON-state drain current
RDS(ON)
ΔRDS(ON)
Static drain-to-source on-state resistance
Change in RDS(ON) with temperature
Conditions
mV/OC VGS = VDS, ID= 1.0mA
A
Ω
%/OC
VGS = 4.5V, VDS = 25V
VGS = 10V, VDS = 25V
VGS = 4.5V, ID = 250mA
VGS = 10V, ID = 0.5A
VGS = 10V, ID = 0.5A
GFS
Forward transductance
CISS
Input capacitance
-
65
125
COSS
Common source output capacitance
-
35
70
CRSS
Reverse transfer capacitance
-
10
25
td(ON)
Turn-on delay time
-
-
10
Rise time
-
-
10
Turn-off delay time
-
-
20
Fall time
-
-
20
Diode forward voltage drop
-
-
1.8
V
VGS = 0V, ISD = 1.0A
Reverse recovery time
-
300
-
ns
VGS = 0V, ISD = 1.0A
tr
td(OFF)
tf
VSD
trr
mmho VDS = 20V, ID = 0.5A
pF
ns
VGS = 0V,
VDS = 25V,
f = 1.0MHz
VDD = 25V,
ID = 1.0A,
RGEN = 25Ω
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
10V
INPUT
0V
Pulse
Generator
10%
t(ON)
td(ON)
VDD
OUTPUT
0V
VDD
90%
t(OFF)
tr
td(OFF)
OUTPUT
RGEN
tf
10%
10%
90%
RL
INPUT
D.U.T.
90%
Supertex inc.
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TD9944
Typical Performance Curves
Output Characteristics
4.0
VGS =10V
8V
2.4
6V
1.6
4V
0.8
10
20
30
40
6V
1.5
4V
1.0
2V
0
8V
3V
0.5
3V
0
VGS =10V
2.0
ID (amperes)
ID (amperes)
3.2
Saturation Characteristics
2.5
0
50
2V
0
2
4
VDS (volts)
6
8
10
VDS (volts)
BVDSS Variation with Temperature
On-Resistance vs. Drain Current
10
1.1
VGS =4.5V
RDS(ON) (ohms)
BVDSS (normalized)
8
1.0
VGS =10V
6
4
2
0.9
3.0
2.5
0
50
100
0
150
1
2
3
4
5
ID (amperes)
Transfer Characteristics
V(th) and RDS Variation with Temperature
2.4
25°C
VDS =25V
1.4
RDS(ON) @ 10V, 0.5A
150°C
VGS(th) (normalized)
TA =-55°C
2.0
ID (amperes)
0
Tj (°C)
1.5
1.0
1.2
V(th) @ 1.0mA
2.0
1.6
1.0
1.2
0.8
RDS(ON) (normalized)
-50
0.8
0.5
0.6
0
0
2.0
4.0
6.0
VGS (volts)
8.0
-50
10
0
50
100
0.4
150
Tj (°C)
Supertex inc.
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TD9944
Typical Performance Curves (cont.)
Capacitance vs. Drain-to-Source Voltage
200
10
f = 1MHz
Gate Drive Dynamic Characteristics
VDS = 10V
8
VGS (volts)
C (picofarads)
150
100
CISS
6
VDS = 40V
150 pF
4
50
COSS
2
CRSS
0
0
10
20
30
0
40
63pF
0
0.4
VDS (volts)
1.0
1.2
1.6
2.0
Transconductance vs. Drain Current
VDS = 25V
TA = -55°C
0.8
GFS (siemens)
0.8
QG (nanocoulombs)
TA = 25°C
0.6
TA = 150°C
0.4
0.2
0
0
0.8
1.6
2.4
3.2
4.0
ID (amperes)
Supertex inc.
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B080713
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TD9944
8-Lead SOIC (Narrow Body) Package Outline (TG)
4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
θ1
D
8
Note 1
(Index Area
D/2 x E1/2)
E1
E
L2
L
1
θ
L1
Top View
View B
Note 1
Gauge
Plane
Seating
Plane
View B
h
A
h
A A2
Seating
Plane
A1
e
b
Side View
View A-A
A
Note:
1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier;
an embedded metal marker; or a printed indicator.
Symbol
Dimension
(mm)
A
A1
A2
b
MIN
1.35*
0.10
1.25
0.31
NOM
-
-
-
-
MAX
1.75
0.25
1.65*
0.51
D
E
E1
4.80* 5.80* 3.80*
4.90
6.00
3.90
5.00* 6.20* 4.00*
e
1.27
BSC
h
L
0.25
0.40
-
-
0.50
1.27
L1
L2
θ
θ1
0
5O
-
-
8
15O
O
1.04
REF
0.25
BSC
O
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.
* This dimension is not specified in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-8SOLGTG, Version I041309.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
Supertex inc.
©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Doc.# DSFP-TD9944
B080713
5
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com