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Proceedings of the 14th International Middle East Power Systems Conference (MEPCON’10), Cairo University, Egypt, December 19-21, 2010, Paper ID 319. Implementing a Three Phase Nine-Level Cascaded Multilevel Inverter with low Harmonics Values Hussein A. Konber and Osama I. EL-Hamrawy Mahmoud EL-Bakry Department of Electrical Engineering University of Al-Azhar Cairo, Egypt, [email protected] Department of Power Electronics Electronics Research Institute Cairo, Egypt [email protected] The switching angles α1, α2, α3, and α4 are first calculated at different values of the main harmonics, so as to obtain zero values of the 5th, 7th, and 11th harmonics, using a selective harmonic elimination technique [6, 7]. All the undesired low order harmonics till the 11th harmonic are eliminated in the output line voltage of the three phase cascaded multilevel inverter. Noting that the odd tripled harmonic, i.e. (3th, 9th, 15th, …etc.) are self cancelled by the three phase balancing. The harmonic values and total harmonic distortion till the 31st harmonic are registered. Next the construction of the implemented three phase ninelevel cascaded multilevel inverter is described and experimental measures when applying the calculated switching angles are recorded under no load and inductive load. Abstract – A three phase nine-level cascaded multilevel inverter with very low values of the undesired low order harmonics is implemented. The switching angles of the inverter power switches are calculated to obtain zero values of the low order harmonics till the 11th harmonic for different values of the output voltage. These values of the switching angles are then applied to the constructed multilevel inverter and the harmonics are measured till the 31st harmonic. The paper presents experimental results, which show very low values of these harmonics as well as for the total harmonic distortion under no load and inductive load. Index Terms –Multilevel inverter implementation, Multilevel inverter harmonics, Selective harmonic elimination, Total harmonic distortion. I. INTRODUCTION Multilevel inverters are widely used in high power industrial applications such as ac power supplies, static VAR compensators, drive systems, etc., [1]. One of the significant advantages of multilevel inverters is the low values of the produced undesired low order harmonics, even when using low switching frequencies, [2]. Cascaded multilevel inverter is a well-known multilevel inverter topology. It is superior to other multilevel inverter topologies, such as diode–clamped and flying capacitor multilevel inverters [3], due to its simple modular structure, ease of control, least number of component and no need for clamping diode or voltage balancing capacitors, [4, 5]. The selection of the level of a multilevel inverter is a critical issue, since multilevel inverters of higher levels produce lower values of undesired harmonics and need power switches of lower ratings, but at the cost of increasing the number of components and control complexity. In this paper a three phase nine-level cascaded multilevel inverter is considered. Fig. 1 shows the structure of a single phase of this inverter. It consists of four simple H-bridge inverters, each can produce three output voltages +Vdc, 0 or – Vdc, thus the whole inverter can produce nine voltage levels. Fig.2 shows an odd-sine symmetric waveform that each phase will be designed to produce. Each H-bridge will be switched on and off only once each half cycle of the main harmonic. The harmonics produced by this way will be the main harmonic in addition to odd sine harmonics only. Fig. 1 single-phase structure of a nine-level multilevel cascaded inverter 983 v1 = 4E π [cos α1 + cos α 2 + cos α 3 + cos α 4 ] 4E [cos 5α1 + cos 5α 2 + cos 5α 3 + cos 5α 4 ] 5π 4E v7 = [cos 7α1 + cos 7α 2 + cos 7α 3 + cos 7α 4 ] 7π 4E v11 = [cos11α1 + cos11α 2 + cos11α 3 + cos11α 4 ] 11π v5 = These four relations will be turned to be four equations that are solved to obtain the values of the switching angles α1, α2, α3, and α4; by setting: v1 = The required amplitude of the main harmonic v5 = 0, v7 = 0, v11 = 0 . B. Solution results The above four nonlinear equations are solved using the "Newton-Raphson method" [4, 8and 9] for the values v1 = 4E, 3.8E, 3.6E, 3.4E, 3.2E, and 2.8E Table 1 gives the obtained values of α1, α2, α3, and α4, as well as the percentage total harmonic distortion (THD) in the output line voltage till the 31st harmonic for each value of v1 , as defined by Fig. 2 Output phase voltage waveform of a nine-level cascade inverter (taking equal values of the dc voltage sources) II. THD = CALCULATING THE SWITCHING ANGLES Vout (ωt ) = ∑ m=0 4 π ∫V out sin(2m + 1)ωtdωt 0 s 4 = Vk cos(2m + 1)α k ∑ π (2m + 1) k =1 Where Vk is the increase in voltage value from each switching angle to another. Assuming regular staircase waveform (V1=V2=.....=Vs=E), the amplitude of the harmonic voltage v2 m +1 is given by the values of a 2 m +1 i.e. v2 m +1 = ) 2 / v1 × 100 Table 1.1the switching angles at different value of π with a 2 m +1 = 2 m +1 Noting that the tripled odd harmonics (2m+1=3, 9, ….) are not considered. a2 m +1 sin(2m + 1)t 2 ∑ (v m =1 A. Formulation of the problem The Fourier series of the general quarter wave symmetric waveform, similar to that of Fig.2, with switching angles α1, α2, α3..., αs per quarter cycle is given by ∞ 15 v1 v1 4E 3.8E α1 10.015° 11.549° 14.409° 19.099° 24.699° 36.118° α2 22.140° 27.392° 33.539° 39.722° 45.530° 47.876° α3 40.752° 46.720° 51.290° 55.586° 57.039° 61.072° α4 61.768° 64.444° 66.546° 66.978° 68.888° 76.297° THD % 5.1635 7.1598 5.3259 3.6E 3.4E 7.3345 3.2E 6.2731 2.8E 7.471 Figure 3 shows the variations of THD with v1 . Figures 4 and 5 show the harmonic spectrum of the line voltage till the 31st harmonic for v1 =4E and 2.8E respectively. s 4E ∑ cos(2m + 1)α k π (2m + 1) k =1 It should be noted that under pure inductive load the total harmonic distortion in the current will be much lower, since it is given by: For the nine level inverter four switching angles α1, α2, α3, α4 are available, and the first four non zero harmonics in the output line voltages of the three phase inverter are THD = 15 m =1 984 v2 m +1 ∑ ( 2 m + 1) 2 / v1 × 100 Fig.3 the voltage THD versus v1 Fig.4 Harmonic spectrum of the line voltage at Fig.5 Harmonic spectrum of the line voltage at Fig.6 Construction of a three-phase nine-level cascaded inverter The hardware prototype shown in Fig. 6 consists of four main parts as follows: 1) The control circuit; An Atmel AT89C52 microcontroller is used as the main processor, which provides the gate logic signals. The microcontroller board is a part of the control unit. It receives the control command from the key button to enter the value of the switching angles, and generates the control signals for the gate drives. The microcontroller board consists of one microcontroller chip as the master processor and three microcontrollers as slave processors for generating the control signal for each gates of the module board. The generation of the control signals is realized inside the microcontroller chip. To control the gate signals, the command program, which is implemented in C++ language, is generated on a personal computer and then transferred to the microcontroller on the control circuit board. 2) The gate-driver circuit: NE555 is used as a gate-driver, which receives a TTL logic signal from the microcontroller and provides +10 V for the turn on the gate signal and 0 V the for the turn off the gate signal to obtain the proper gate voltages necessary for proper switching of the MOSFET. It is important to isolate the output signal from the drive circuit to avoid the propagation of fault voltages. Isolation is achieved by using optocouplers (type 4N35). 3) The power stage: Four MOSFET, IRFP260, are used as the main switches, which are connected in full-bridge configuration. Each power stage is supplied by a separate dc source E=72 V. Figure 7 shows the experimental configuration v1 =4E v1 =2.8E III. EXPERIMENTAL ANALYSIS A. Experiment setup The construction of the three phase wye-connected, nine-level cascaded multilevel inverter is illustrated in Fig.6. The power electronics switch used for this particular multilevel inverter is IRFP260 MOSFET with voltage ratings of 200V and current ratings of 46A. 985 H-bridge power stage Separate DC source Fig. 10 No load peak phase voltage at v1 =2.8E=200v Fig. 7 Experimental configuration B. Experimental results 1-under no load: Figure8 shows the peak phase voltage of the inverter with no load at v1 =4E=288v and f=50Hz. Figure9 shows the voltage harmonic spectrum at v1 =4E=288v The THD measured by a power harmonic analyzer is 4.48%. Figures 10, and 11 show the same at v1 =2.8E=200v. The THD measured by a power harmonic analyzer is 7.46%. Fig. 8 No load peak phase voltage at Fig. 11 Harmonic spectrum of line voltage at v1 =2.8E 2-under inductive load: The inverter is loaded by a three phase step down transformer 380v/133v connect to a three phase inductive load each inductance has L=125mH, r =0.9Ω. Figures 12 and 13 show the phase voltage and phase current waveform respectively of the inductive load at the secondary output of the transformer at v1= 4E. Figures 14 and 15 show the harmonic content of phase voltage and phase current at different voltage values respectively. The experimental phase voltage THD measured by the power harmonic analyzer 5.79 %. The experimental phase current THD measured by the power harmonic analyzer is 2.67 %. v1 =4E=284v The value of each of the dc voltage sources was taken 72 v. This value can be changed to obtain any desired value of the output voltage. It is clear that the inverter produces very low values, nearly negligible, of the undesired low order harmonics. Fig. 9 Harmonic spectrum of line voltage at v1 =4E 986 IV. CONCLUSIONS A three phase nine-level cascaded multilevel inverter is implemented that produces very low values of the low order harmonics. The switching angles of the inverter power switches are calculated such that the low order harmonics till the 11th harmonic are eliminated. Digital generation of switching signals using a microcontroller allows generating the required switching angles for different voltage values. The harmonics measured till the 31st harmonic are very low for different values of the output voltage, as well the value of the total harmonic distortion under no load and inductive load. REFERENCES Fig. 12 Output voltage with inductive load, Fig. 13 Inductive load current, v1 =4E [1] Lai J.S. and Peng F.Z., "Multilevel Inverters: A Survey of Topologies, Control and Applications," IEEE Trans.Ind.Elec., vol. 49, pp.724-738, Aug.2002. [2] A. Muthuramalingam, M. Balaji and S. Himavathi "Selective Harmonic Elimination Modulation Method for Multilevel Inverters" Proceedings of India International Conference on Power Electronics pp.40-45, 2006 [3] M. Ghasem Hosseini Aghdam S. Hamid Fathi and Gevorg B. Gharehpetian "Harmonic Optimization Techniques in Multi-Level Voltage-Source Inverter with Unequal DC Sources" Journal of power electronics.vol.8, No2, April 2008 pp.171-180 [4] Y.Sahali, and M. K. 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Wu, "Selective Harmonic Elimination Techniques for Multilevel Cascaded H-Bridge Inverters", The 6th International Conference on Power Electronics and Drive Systems (IEEE PEDS 2005), Kuala Lumpur, Malaysia, pp. 1441-1446, 28 November- 1 December 2005 [7] Jagdish Kumar, Biswarup Das, and Pramod Agarwal "Harmonic Reduction Technique for a Cascade Multilevel Inverter" International Journal of Recent Trends in Engineering, Vol 1, No. 3, May 2009 pp.181185 [8] Q. Jiang, and T. A. Lipo, "Switching Angles and DC Link Voltages Optimization for Multilevel Cascade Inverters", Electric Power Components and Systems, Vol. 33, No. 14, October 2005. [9] S. Sirisukprasert, J. Lai, and T. Liu, "Optimum Harmonic Reduction with a Wide Range of Modulation Indexes for Multilevel Converters", IEEE Transactions on Industrial Electronics, Vol. 49, No. 4, pp. 875- 881, August 2002 v1 =4E Fig.14 Voltage harmonic spectrum at v1 =4E Fig.15 Current harmonic spectrum at v1 =4E 987