InSthisSthesisSworkBS theS die4attachmentS andS interconnectionS technologiesS forS state4
of4the4artSSiCSandSGaNShigh4powerSdevicesSareSpresented8
TheSmainSfocusShasSbeenSgivenStoStheSdie4attachmentStechniques8STwoSnovelSdie4
attachmentS methodsS i8e8S Ag4sinteringS andS TransientS LiquidS PhaseS LTLPPS bondingS
wereS investigated8SForS TLPS bondingBS Sn4AgS andS In4AgS basedS multilayerS foilsS wereS
sucessfullyS producedS asS interlayerS materials8S BothS Ag4sinteredS andS TLPS bondedS
layersS wereS foundS toS beS stableS upS toS 97z˚C8S TheirS electricalBS thermalS andS
mechanicalS propertiesS wereS betterS thanS theS currentS state4of4the4artS soldersS i8e8S
AgSnBS AuSnS andS AuGeS etc8S UsingS Ag4sinteringS andS TLP4bondingBS thermalS andS
thermo4mechanicalS stressesS duringS packagingS andS operationS wereS foundS toS beS
considerablySlowSasScomparedStoScurrentStechniques8S
AS systematicS electricalS andS thermalS characterizationS ofS SiCS andS GaNS devicesS wasS
performedS fromS theS on4waferS devicesS toS theS finalS assembly8S AcceleratedS agingS
testsBS suchS asS passiveS temperatureS cyclingS andS activeS powerS cyclingBS wereS
performedS forS theS packagedS devices8S BothS Ag4sinteredS andS TLPS bondedS layersS
exhibitedS superiorS powerS cyclingS capabilities8S TheS crackS propagationS ratesS inS theS
die4attachS layersS wereS modelledS withS Paris’S Law8S Ag4sinteringS andS TLPS bondingS
wereS foundS toS beS highlyS reliableS mountingS methods8S ItS canS beS concludedS fromS theS
currentS investigationsBS thatS bothS Ag4sinteringS andS TLPS bondingS areS realisticS
AssemblySandSPackagingSTechnologiesSforSGaNSandSSiCSDevicesS
.
AdeelSAhmadSBajwa
NewSAssemblySandSPackagingSTechnologies
forSHigh-PowerSandSHigh-TemperatureSGaN
andSSiCSDevicesS
devices8
AdeelSAhmadSBajwa
candidatesS forS industrialS processesS forS die4attachmentS ofS SiBS SiCS andS GaNS powerS
6786
918x
x5581
TemperatureSL˚CP
IMTEKBSUniversitySofSFreiburg
x3789
New Assembly and Packaging Technologies for
High-Power and High-Temperature GaN and SiC
Devices
Dissertation
zur Erlangung des Doktorgrades
der Technischen Fakultät der
Albert-Ludwigs-Universität Freiburg im Breisgau
Adeel Ahmad Bajwa
Freiburg im Breisgau, 2015
i
Dekan
Prof. Dr. Georg Lausen
Referenten
Prof. Dr.-Ing. Jürgen Wilde
Prof. Dr. rer. nat. Oliver Ambacher
Tag der mündlichen Prüfung: 02-10-2015
Albert-Ludwigs-Universität Freiburg
Technische Fakultät
Institut für Mikrosystemtechnik - IMTEK
Professur für Aufbau- und Verbindungstechnik
ii
Acknowledgement
I would like to gratefully thank my principal supervisor Prof. Dr.-Ing. Jürgen Wilde for
providing me an opportunity to work on this interesting topic. During the research work,
he always gave me worthy advices and suggestions. Through regular meetings and
presentations, he kept a keen eye on my work progress. Thereby, I was able to finish my
work in an efficient manner. Especially, his scientific discussions were very fruitful and
eventually helped me gaining the in-depth knowledge.
I am also very thankful to Prof. Dr. rer. nat. Oliver Ambacher for his continuous support
and willingness to accept the role as my second supervisor. During my doctoral work, I
was simultaneously a member of his Laboratory for Compound Semiconductor
Microsystems. Being a part of his team, I was also provided with the best available
laboratory facilities at Fraunhofer Institute for Applied Solid State Physics (IAF),
Freiburg, Germany.
I would like to acknowledge Dr. Rüdiger Quay for all his support during the work. He
was always very helpful and encouraging. I learned a lot from discussions with him and
he helped me to understand the key scientific issues. Very special thanks to my
colleagues, M.Sc. Richard Reiner and Dipl.-Ing. Beatrix Weiss, at the Fraunhofer IAF.
They were always very cooperative and friendly. Mr. Reiner also helped me in proof
reading of the thesis. I would also like to thank all other staff members at Fraunhofer
IAF for their support.
I also acknowledge the Fritz Hüttinger Foundation for the financial support of the
project. Moreover, a bundle of thanks to all industrial partners, especially Trumpf
Hüttinger GmbH, Infineon Technologies Austria and Heraeus GmbH. They provided
valuable materials support during my project.
Special thanks go to all my colleagues Dr.-Ing. Roderich Zeiser, Dr.-Ing. Matthias
Steiert, M.Sc. Mujtaba Syed, Dipl.-Phys. Marcel Tondorf, M.Sc. Eike Moeller and our
lab’s senior scientist Dr.-Ing. Michael Berndt for their support during my doctoral work.
All my colleagues were very cooperative and friendly. I will also mention our secretary
Mrs. Tania Dintcheva for her dedication in solving administrative issues.
I also acknowledge Dipl. Chem. Kay Steffen for his key support during our novel
multilayer foil preparations. His dedication and supportiveness always helped to
overcome technical issues. A very special thanks to Dr.-Ing. Michael Wandt, Dipl.-Ing.
(FH) Michael Reichel, Nico Lehmann and other cleanroom staff members. They always
cooperated to meet the dead lines.
Here, I will also mention the support of the lab’s student assistants B.Sc. Lorenz
Litzenberger, B.Sc. Kevin Hanka and all others. A special thanks goes to M.Sc
iii
Yangyang Qin. She worked as a student assistant in our lab to support my project.
Additionally, she wrote her valuable master thesis about foil-based TLP bonding
process.
I would like to acknowledge my friends Mueed Azhar, Sarmad Ullah and all others for
their continuous moral support during my stay in Germany.
I whole heartedly acknowledge my wife Raazia Adeel, for her continuous support during
the most crucial phase of my doctoral work. She has always been extremely patient and
caring. At times when I was under enormous work pressures, she always encouraged me.
I would like to thank my father Masood Bajwa, my mother Farzana Bajwa and my
brother Shajeel Bajwa for their continuous support during my whole academic life.
Especially, my mother has been a great source of inspiration for me. I dedicate my thesis
work to her and this dream would not have been fulfilled without her encouragement.
iv
Abstract
This thesis work is aimed at investigating the assembly and packaging technologies for
GaN and SiC based high-power and high-temperature electronic devices. The dieattachment and interconnection methods have been in the focus of investigations. For
mounting SiC and GaN devices, Ag-sintering and foil-based Transient Liquid Phase
(TLP) bonding were selected as die-attachment techniques. For TLP bonding process,
the TLP-interlayer material was produced in the form of electroplated multilayer foils,
which were based on Ag-Sn and Ag-In binary systems. Two design variants of
multilayer foils, consisting of a 3-layer sandwich structure and a 9-layer structure, were
successfully produced. The 9-layer structure provided the benefit of avoiding the postbonding annealing step. The novel multi-layer foil can be utilized as a commercial
product for TLP-interlayer material. For both Ag-sintering and foil-based TLP bonding,
a complete process parameter optimization was performed. Various characterizations
methods such as Differential Scanning Calorimetry (DSC), Energy Dispersive X-ray
(EDX) Spectroscopy, Infrared (IR) Thermography, Digital Image Correlation (DIC) and
Die-Shear Tests were used to determine the properties of the die-attachments.
Subsequently, electrical, thermal and mechanical properties of both die-attachment types
were compared to the current state-of-the-art high-temperature die-attachments such as
Au80Sn20, Au88Ge12 etc. It was found that both Ag-sintering and TLP bonding
exhibited better thermal and electrical properties. The thermo-mechanical stresses in Agsintered and TLP bonded joints were considerably low in a wide range of temperatures
i.e. 30 – 400 ºC.
The GaN-on-Si High Electron Mobility Transistors (HEMTs) from Fraunhofer IAF
Freiburg, were used during the investigations. These devices feature high breakdownvoltages, lower specific on-state resistances and achieve higher performances on smaller
area as compared to their Si counterpart. A systematic electrical characterization of
GaN-on-Si HEMTs was performed from on-wafer devices to the final assembly. The
objective was to investigate the assembly-related thermal and thermo-mechanical
influences on the electrical characteristics of the devices. A major emphasis was given to
the thermal characterization of the GaN assemblies. The surface temperatures of the
devices were measured using IR-thermography and surface-mounted Pt-1000
temperature sensors. The actual channel temperatures were determined through MicroRaman Spectroscopy. A correlation was made between the surface temperature of the
device and its actual channel temperature. This was aimed at determining the reliable
upper operational temperature limits of the GaN-on-Si HEMTs, which is usually from
220 – 250 Cº. Both Ag-sintering and TLP bonding were used for mounting GaN-on-Si
HEMTs. Whereas, for electrical interconnection, thin wire bonds (ϕ = 50 µm) based on
v
gold and palladium were investigated. Though, palladium is a high-temperature stable
material, its temperature-dependent electrical resistivity was found to be a great
hindrance during high-current operation. Thereby, gold was preferred as the optimum
electrical interconnection material. Commercially available SiC Schottky diodes were
also used during the thesis work. These devices were rated for a forward current of 8 A,
blocking voltage of 600 V and an upper junction temperature limit of 175 ºC. A novel
aluminum alloy AlX, from Heraeus GmbH, was used for wire (ϕ = 300 µm) bonding of
SiC diodes. This material exhibited similar electrical properties to Al, while, it was
stable up to 300 ºC. The diodes were mounted using both Ag-sintering and TLP
bonding. In a similar fashion to GaN assemblies, the complete electrical and thermal
characterization of SiC assemblies was performed.
No damage to the SiC and GaN-on-Si devices occurred during Ag-sintering and foilbased TLP bonding process. The electrical characteristics of both GaN-on-Si HEMTs
and SiC Schottky diodes were fully retained after die-attachment. Excellent thermal
dissipation behavior was observed for both assemblies. The reliability tests such as
passive temperature cycling and active power cycling were performed for both
assemblies. Both die-attachments exhibited shear strengths above 30 MPa after passive
temperature shock cycling from -40 ºC to +150 ºC. During power cycling of GaN
HEMTs, device failures occurred before any considerable damage to the die-attachment
or wire bonds. The failure was indicated by an increase of gate leakage current beyond
50 mA. Therefore, power cycling tests performed on SiC assemblies helped to determine
the fatigue in the die-attach layer. It was found that both Ag-sintering and Sn-Ag TLP
bonding lead to superior power cycling reliability in comparison with soldering and
adhesive bonding. The crack rates were experimentally determined by dividing the total
crack length by the number of power cycles to failure. Based on plastic material models
of both Ag-sintered and TLP bonded layers, coupled thermo-mechanical finite element
simulations were performed to determine the damage parameter i.e. plastic strain range
amplitude (∆εp). Consequently, the crack propagation rates in both die-attach layers
could be modelled in the form of Paris’ Law. It can be stated that both Ag-sintering and
TLP bonding are realistic candidates for the industrial die-attachment processes for both
SiC and GaN devices. Additionally, both die-attachment techniques can be applied to the
current Si-based power devices as well.
Based on novel Ag-sintering and foil-based TLP bonding, a complete package consisting
of a die, substrate and base plate has been proposed. The chip-substrate and substratebase plate connections can be made using either die-attach technology. Thereby, the
resultant package exhibits the high-temperature stability of materials up to 480 ºC. The
overall thermal dissipation behavior of the assembly was improved, as novel attachments
exhibit excellent thermal properties. A better CTE match was achieved between the chip
(GaN-on-Si or SiC) and substrate (AlN) in comparison with copper, which is the
substrate material in currently used TO-220 packages. With a combination of better CTE
matching and improved thermal properties, the package life time is expected to improve.
vi
Zusammenfassung
Ziel dieser Arbeit war es, Technologien für den Aufbau und das Packaging von GaNund SiC-basierten Hochleistungs- und Hochtemperaturbauelementen zu untersuchen.
Hauptbestandteile
der
Untersuchung
waren
die
Befestigungsund
Verbindungsmethoden. Für den Einbau von SiC- und GaN-Bauelementen wurde SilberSintern und folienbasiertes Transient Liquid Phase (TLP) Bonden als ChipBefestigungstechniken ausgewählt. Für den TLP-Bondprozess wurde das
Zwischenschichtmaterial in Form von mehrlagigen galvanisierten Folien hergestellt,
welche auf den Binärsystemen Ag-Sn und Ag-In basieren. Zwei Entwurfsvarianten von
mehrschichtigen Folien, welche aus einer 3-schichtigen sandwichartigen Struktur und
einer 9-schichtigen Struktur bestehen, wurden erfolgreich hergestellt. Die 9Schichtstruktur bietet den Vorteil, dass auf die Wärmebbehandlung nach dem Bonden
verzichtet werden kann. Die neue mehrschichtige Folie kann die Basis für kommerzielle
TLP-Zwischenschichtmaterialien bilden. Für beide Bondverfahren, Silber-Sintern und
folienbasiertes TLP, wurde eine komplette Optimierung der Prozessparameter
durchgeführt. Verschiedene Methoden zur Charakterisierung der Die-Befestigung wie
Differential Scanning Calorimetry (DSC), Energy Dispersive X-Ray (EDX)
Spectroscopy, Infrared (IR) Thermography, Digital Image Correlation (DIC) und
Scherversuche wurden verwendet, um die Eigenschaften zu bestimmen. Anschließend
wurden die elektrischen, thermischen und mechanischen Eigenschaften von beiden DieBefestigungstypen mit dem Stand der Technik bei Hochtemperatur-Die-Befestigung wie
den Löten mit Au80Sn20 und Au88Ge12 verglichen. Es wurde festgestellt, dass beide
Bondverfahren, Silber-Sintern und TLP, bessere thermische und elektrische
Eigenschaften aufweisen. Der thermomechanische Stress in silbergesinterten oder mit
TLP verbundenen Anschlüssen war über einen breiten Temperaturbereich von 30 –
400 ºC erheblich kleiner.
Die GaN-on-Si High-Electron-Mobility-Transistoren (HEMT) von Fraunhofer IAF in
Freiburg wurden in den Untersuchungen verwendet. Diese Bauteile weisen hohe
Durchbruchspannungen und einen geringen spezifischen Durchlasswiderstand auf. Sie
erreichen höhere Leistungen auf kleineren Flächen im Vergleich zu Gegenstücken auf
Si-Basis. Eine systematische elektrische Charakterisierung von GaN-on-Si HEMTs
wurde von On-Wafer-Bauelementen bis zur Endmontage durchgeführt. Das Ziel war es,
die fertigungsbezogenen thermischen und thermomechanischen Einflüsse auf die
elektrischen Eigenschaften des Bauelementes zu untersuchen. Der thermischen
Charakterisierung von GaN-Baugruppen wurde eine besondere Beachtung geschenkt.
Die Oberflächentemperaturen wurden mittels IR-Thermometer und auf der Oberfläche
montierten Pt-1000 Temperatursensoren gemessen. Die tatsächliche Kanaltemperatur
vii
wurde mittels Micro-Raman-Spektroskopie bestimmt. Die Oberflächentemperatur des
Bauteils und die tatsächliche Kanaltemperatur wurden korreliert. Dies wurde genutzt,
um zuverlässig die obere Grenze der Betriebstemperatur von GaN-on-Si HEMTs zu
bestimmen, welche in Bereich von 220 °C bis 250 °C liegt. Silber-Sintern und TLPBonden wurden für die Befestigung der GaN-on-Si-HEMTs verwendet, wobei für die
elektrischen Anschlüsse dünne Drahtbonds (ϕ=50 μm) aus Gold und Palladium
untersucht wurden. Obwohl Palladium ein hitzebeständiges Material ist, wurde
festgestellt, dass dessen temperaturabhängiger Widerstand ein signifikanter Nachteil ist.
Gold wird hingegen als das beste Verbindungsmaterial für elektrische Kontakte
angesehen. Für diese Arbeit wurden kommerziell verfügbare Schottky-Dioden aus SiC
verwendet. Diese sind für einen Strom in Durchlassrichtung von bis zu 8 A, eine
Sperrspannung bis 600 V und eine obere Temperaturgrenze von 175 ºC spezifiziert. Für
das Bonden der SiC Dioden wurden Drähte (ϕ = 300 μm) aus einer neuen
Aluminiumlegierung verwendet. Dieses Material zeigt ähnliche elektrische
Eigenschaften wie reines Al und ist bis zu einer Temperatur von 300 °C stabil. Beide
Verfahren, Silber-Sintern und TLP-Bonding wurden zum Befestigen der Dioden
verwendet. Die komplette elektrische und thermische Charakterisierung der SiCBaugruppen wurde wie die der GaN-Baugruppen durchgeführt.
Nach dem Silber-Sintern oder TLP-Bonden wurden keine Schäden an den SiC- und
GaN-on-Si-Bauelementen festgestellt. Die elektrischen Eigenschaften der GaN-on-SiHEMTs und SiC-Schottky-Dioden blieben nach der Die-Befestigung vollständig
erhalten. Bei beiden Bauteilen wurde eine hervorragende Wärmeabführung beobachtet.
Weiterhin wurden passive Temperaturwechseltests und aktive Leistungszyklen zur
Bestimmung der Zuverlässigkeit durchgeführt. Nach Schockzyklen von -40 °C bis
150 °C zeigten die Die-Befestigungen Scherspannungen von über 30 MPa. Während der
Leistungszyklen der GaN-HEMTs traten Ausfälle der Bauelemente auf, bevor ein
nennenswerter Schaden der Die-Befestigung oder der Verbindungen vorlag. Der Anstieg
des Gate-Leckstromes von über 50 mA deutete dabei auf den Defekt des Transistors hin.
Somit ermöglichen Leistungszyklen die Materialermüdung von SiC-Baugruppen in DieBefestigungen zu bestimmen. Bei beiden Verfahren, Silber-Sintern und TLP-Bonden mit
Sn-Ag, wurde festgestellt, dass diese im Vergleich zu herkömmlichen Lötverfahren und
Klebeverbindungen eine hervorragende Beständigkeit bei Leistungszyklen haben. Die
Rissfortschrittsrate wurde dabei experimentell als Quotient aus Bruchlänge und Anzahl
der Leistungszyklen bis zum Ausfall bestimmt. Eine gekoppelte thermomechanische
Finite-Elemente-Simulation wurde zur Bestimmung der spezifischen, lokalen
Materialbeanspruchung , z.B. der plastischen Dehnungsamplitude durchgeführt. Die
Ausbreitungsrate des Bruchs in beiden gebondeten Schichten kann durch ein ParisGesetz modelliert werden. Abschließend kann festgestellt werden, dass beide
Verbindungstechnologien
ein
hohes
Potential
besitzen,
als
alternative
Verbindungstechnologien für den Aufbau von Si-, SiC- und GaNLeistungsbauelementen zu dienen.
viii
Komplette Aufbauten, bestehend aus Chip, Substrat und einer Basisplatte, wurden mit
neuartigen Bondingverfahren dargestellt. Die Technologie zur Die-Befestigung kann zur
Herstellung der Verbindung zwischen Chip und Substrat sowie zwischen Substrat und
Basisplatte verwendet werden. Das Endprodukt übersteht 480 °C und verfügt somit über
herausragende thermische Eigenschaften. Zwischen dem Chip (GaN-on-Si oder SiC)
und dem Substrat (AlN) wurde eine verbesserte CTE-Anpassung im Vergleich zu
Kupfer erreicht, welches das derzeitige Material für die TO-220 Gehäuse ist. Vorschläge
für weitere forschungsbetreffende Untersuchungen wäre eine Kombination aus besser
angepasstem CTE und verbesserten thermischen Eigenschaften, welche noch höhere
Lebensdauern der Verpackung erwarten lassen.
ix
Table of Contents
1 Introduction ................................................................................................................... 1
1.1
Wide Bandgap Semiconductors ........................................................................... 1
1.2
Assembly Requirements for High-Power & High-Temperature Operation ........ 2
1.2.1 Requirements for Die-Attachment ........................................................... 2
1.2.2 Requirements for Interconnection ............................................................ 3
1.3
Aims of the Thesis Work ..................................................................................... 3
1.4
Thesis Outline ...................................................................................................... 5
2 Theoretical Background ................................................................................................ 7
2.1
Sintering ............................................................................................................... 7
2.1.1 Classifications of Sintering ...................................................................... 7
2.1.2 Sintering Process Mechanism .................................................................. 8
2.1.3 Low-Temperature Sintering Strategies .................................................... 9
2.1.4 Drawbacks of Nanoscale Particle Size ..................................................... 9
2.1.5 Low Temperature Joining Technique .................................................... 10
2.1.6 Advantages and Disadvantages of Ag-Sintering .................................... 11
2.2
Transient Liquid Phase (TLP) Bonding ............................................................. 11
2.2.1 TLP Bonding Process ............................................................................. 12
2.2.2 Process Variables ................................................................................... 13
2.2.3 Advantages and Disadvantages of TLP Bonding ................................... 14
2.3
Power Electronics Package Concept .................................................................. 15
2.4
Failure Mechanism of Power Modules .............................................................. 16
2.5
Material Modelling ............................................................................................ 17
2.6
Crack Formation and Propagation Modelling .................................................... 17
2.7
Crack Propagation in Ag-Sintered Joints ........................................................... 18
2.8
Lifetime Prediction Models ............................................................................... 19
2.9
Summary ............................................................................................................ 20
x
3 State-of-the-Art ........................................................................................................... 22
3.1
High-Temperature High-Power Devices ........................................................... 22
3.1.1 GaN-on-Si HEMT.................................................................................. 23
3.1.2 SiC Merged PN/Schottky Diodes .......................................................... 25
3.2
High-Temperature Die-Attach Solutions........................................................... 26
3.2.1 Lead-Free Solder Systems ..................................................................... 26
3.2.2 TLP Bonding Systems ........................................................................... 27
3.2.3 Silver Sintering ...................................................................................... 28
3.2.4 Process Parameters of Die-Attach Methods .......................................... 28
3.2.5 Material Properties of Die-Attachments ................................................ 30
3.3
Characterization Methods of Die-Attach ........................................................... 31
3.3.1 Energy Dispersive X-Ray Spectroscopy................................................ 31
3.3.2 Differential Scanning Calorimetry......................................................... 32
3.3.3 Digital Image Correlation Technique .................................................... 32
3.3.4 Shear Tests ............................................................................................. 34
3.4
High-Temperature Interconnection Methods .................................................... 35
3.5
Substrate Materials ............................................................................................ 35
3.6
Applications ....................................................................................................... 36
3.7
Summary............................................................................................................ 37
4 Experimental Procedures ............................................................................................ 38
4.1
Substrates ........................................................................................................... 38
4.2
Test Chips .......................................................................................................... 39
4.3
Die-attachment Methods.................................................................................... 40
4.3.1 Silver Sintering ...................................................................................... 40
4.3.2 Sinter Process ......................................................................................... 41
4.3.3 Materials ................................................................................................ 41
4.3.4 Application of Ag-Sinter Paste .............................................................. 42
4.3.5 Sintering Setups ..................................................................................... 43
4.3.6 Sintering Temperature Profile ............................................................... 45
4.3.7 Effects of Process Parameters ................................................................ 45
4.3.8 Transient Liquid Phase Bonding............................................................ 47
xi
4.3.9 TLP Bonding Process ............................................................................. 48
4.3.10 High-Temperature Stable Binary Compounds ....................................... 50
4.3.11 Design Criteria of Multilayer TLP Foil.................................................. 51
4.3.12 Multilayer Foil Preparation .................................................................... 51
4.3.13 Electrochemical Deposition ................................................................... 52
4.3.14 Micrographs of Multilayer Foils ............................................................ 54
4.3.15 TLP Bonding Experimental Setup ......................................................... 56
4.3.16 Process Parameter Optimization ............................................................ 56
4.4
Interconnection Methods.................................................................................... 58
4.4.1 Gold and Palladium Wire Bonding. ....................................................... 58
4.4.2 Process Parameter Optimization ............................................................ 59
4.4.3 AlX Wire Bonding ................................................................................. 60
4.5
Summary ............................................................................................................ 60
5 Characterization Methods and Results ........................................................................ 61
5.1
Shear Strength .................................................................................................... 61
5.2
Differential Scanning Calorimetry ..................................................................... 64
5.2.1 Sn-Ag TLP Bonded Joints...................................................................... 65
5.2.2 In-Ag TLP Bonded Joints ...................................................................... 66
5.3
Energy Dispersive X-ray Spectroscopy ............................................................. 67
5.3.1 Sn-Ag TLP Bonded Joints...................................................................... 67
5.3.2 9-layer Sn-Ag TLP Bonded Joints ......................................................... 68
5.3.3 In-Ag TLP Bonded Joints ...................................................................... 69
5.4
Thermal Resistance ............................................................................................ 70
5.5
Electrical Conductivity ...................................................................................... 72
5.6
Thermal Stresses in Die-Attachment ................................................................. 73
5.6.1 Properties of Die-Attach Materials ........................................................ 74
5.6.2 Analytical Considerations ...................................................................... 75
5.6.3 Die-Attach Shear Stress ......................................................................... 76
5.6.4 Die Stresses ............................................................................................ 77
5.6.5 Warpage of Assembly ............................................................................ 78
5.6.6 Comparison of Analytical Solution ........................................................ 78
xii
5.6.7 Experimental Determination of Bending Stresses ................................. 80
5.7
Mechanical Characterization ............................................................................. 84
5.8
Micrographs of TLP and Ag-Sintered Joints..................................................... 86
5.9
AlX Material Characterization .......................................................................... 87
5.9.1 Mechanical Characterization ................................................................. 87
5.9.2 Electrical Characterization ..................................................................... 88
5.10 Pull-Strengths of Wire bonds ............................................................................ 88
5.11 Summary............................................................................................................ 89
6 Assembly and Packaging of SiC Schottky Diodes ..................................................... 92
6.1
Motivation ......................................................................................................... 92
6.2
SiC Schottky Diodes .......................................................................................... 92
6.3
Assembly Process for SiC Schottky Diodes ...................................................... 94
6.4
Electrical Characterization ................................................................................ 94
6.4.1 Forward Characteristics ......................................................................... 94
6.4.2 Maximum Continuous Forward Current ............................................... 96
6.4.3 Breakdown Characteristics .................................................................... 97
6.5
Thermal Resistance of SiC Assemblies ............................................................. 97
6.5.1 Junction Temperature Characterization ................................................. 99
6.6
Active Power Cycling ...................................................................................... 100
6.6.1 Crack Propagation Rates ...................................................................... 102
6.7
Summary.......................................................................................................... 103
7 Assembly and Packaging of GaN HEMTs ............................................................... 104
7.1
GaN-on-Si HEMTs .......................................................................................... 104
7.2
Assembly Process for GaN-on-Si HEMTs ...................................................... 105
7.3
Electrical Characterization .............................................................................. 106
7.3.1 Wafer Statistics .................................................................................... 107
7.3.2 Forward Characteristics ....................................................................... 107
7.3.3 Effect of Interconnect Resistivity ........................................................ 109
7.3.4 Effects of Assembly on Electrical Characteristics ............................... 111
7.4
Thermal Resistance of Assembled GaN HEMTs ............................................ 112
7.4.1 Surface Temperature Characterization ................................................ 114
xiii
7.4.2 Micro-Raman Spectroscopy ................................................................. 115
7.5
Passive Temperature Cycling........................................................................... 117
7.6
Active Power Cycling ...................................................................................... 118
7.7
Short-Term High-Temperature Tests ............................................................... 121
7.8
Complete Package ............................................................................................ 122
7.8.1 Thermal Modelling ............................................................................... 123
7.9
Chapter Summary ............................................................................................ 125
8 Discussion and Conclusions ...................................................................................... 127
8.1
Die-Attachment Methods ................................................................................. 127
8.1.1 Foil-based Interlayer TLP Material ...................................................... 127
8.1.2 Comparison of Process Parameters ...................................................... 127
8.1.3 Comparison of Die-Attach Properties .................................................. 129
8.1.4 Reliability of Die-Attachments ............................................................ 132
8.1.5 Modelling of Crack Propagation Rates ................................................ 134
8.2
Interconnection Methods.................................................................................. 136
8.3
SiC Schottky Diode Packaging ........................................................................ 137
8.4
GaN-on-Si HEMT Packaging .......................................................................... 138
8.5
Conclusions ...................................................................................................... 140
9 Literature ................................................................................................................... 141
xiv
1
Introduction
Presently, various electronic applications such as down-hole oil and gas industry for well
logging, military, aircraft, automotive and space exploration etc. require electronic
devices to operate at high-power levels and under high-temperature conditions [1].
Besides extreme ambient conditions, the power electronic devices during operation face
several high-stress switching conditions such as clamped inductive loads and shortcircuited loads. Under transient conditions, the temperature inside a device can reach to
very high values, resulting in device failure [2]. Very often in high-frequency and highpower applications like plasma sources, large power reflections can occur during
impedance mismatch conditions. This results in sudden high-temperature peaks, which
can possibly destroy the device and/or assembly [3]. Currently, the Si-based electronic
devices such as IGBTs, MOSFETS, diodes etc. dominate the current power electronics
systems. But these devices face their limitations in terms of switching speeds, junction
temperatures and power densities etc. [4]. At temperatures above 200 ºC and under highpower densities (several hundred of Watts/cm2) [1], the failure can possibly occur due to
semiconductor device itself or due to the assembly failures. The die-attachment and
interconnections are the most critical components of the assembly. The assembly
processes and set of materials, which are currently used for Si-device packaging, can
operate reliably up to 150 ºC. The operational limitation of both the Si-devices and
assembly technologies prompts the research for new high-temperature stable
semiconductor materials and also the reliable packaging technologies [4].
1.1
Wide Bandgap Semiconductors
In order to overcome the limitations of Si, the state-of-the-art wide band gap
semiconductors such as GaN and SiC with their excellent electrical and physical
properties [4], [5], [6], have been proposed for high-power and high-temperature
applications. Compared to Si, both GaN and SiC based power devices can operate at
much higher junction temperatures reaching up to 300 ºC [6]. Due to wider band gap,
these devices exhibit high breakdown voltages. Moreover, they possess high current
capabilities and very low switching losses, which allow them to operate at higher
frequencies [3], [4]. An increase of maximum power-per-unit-area is achieved by
fabricating SiC and GaN devices, which have much smaller areas as compared to their
Si counterparts. The literature reports on a variety of SiC and GaN devices which can
operate at high-temperature and high-power [4].
1
Chapter 1
1.2
Introduction
Assembly Requirements for High-Power &
High-Temperature Operation
In order to take advantage of excellent electrical properties of SiC and GaN devices, an
assembly process is required, which allows the high-temperature operation without any
deterioration of their electrical characteristics. Currently for high-power (≤ 1KW) and
high-temperature operation from 250 ºC – 500 ºC, the set of assembly processes and
materials are limited and assembly technology is yet not fully matured. The major
challenges are physical, thermal and electrical stability of packaging materials [7]. For
instance, the current state-of-the-art high-temperature die-attachments such as AuSn and
AuGe solders melt at 280 ºC and 356 ºC respectively, which limits their operational
capability well below their melting points. The high-temperature stability, matching of
thermal expansion coefficients (CTE) between different materials, and other material
properties such as thermal conductivity, electrical conductivity and elastic modulus etc.
become very critical for these materials. The commonly available interconnection
materials such as Cu, Al etc. oxidize while operating above 250 ºC [7]. The extreme
thermal cycling conditions during operation can cause high thermal and thermomechanical stresses on the package, which significantly reduces the package lifetime.
All these factors open a wide gate for research on high-temperature stable assembly
materials and processes. In the next sections, the requirements for high-temperature
stable die-attachments and interconnection methods and materials will be discussed.
1.2.1 Requirements for Die-Attachment
The die-attachment process includes three components, which are chip, die-attach layer
and substrate. The high-temperature stable die-attachment needs to fulfill the following
requirements, which are the focus of investigation in this thesis work.
‒ The die-attach material should be stable up to 500 ºC [7] or more in order to
prevent the melting during the high-temperature peaks which possibly result
from large power reflections [3].
‒ The thermal conductivity of the die-attach material must be high to dissipate the
heat generated in the active area of the device during high-power operation [8].
This holds true for both lateral and vertical designs of the semiconductor devices.
‒ For power devices with vertical design, the electrical conductivity of the dieattachment material should be high to achieve high-power levels [9].
‒ The coefficient of thermal expansion (CTE) of chip, die-attach and substrate
must be matched in order to minimize the thermo-mechanical stresses, which are
produced during the die-attachment process and also during the high-temperature
operation of the semiconductor devices [10].
2
1.3
Aims of the Thesis Work
‒ The contact metallization of substrate and die backside have to be selected
carefully. High-temperature exposure increases the probability of brittle
intermetallics formation and also increases the interface diffusion [1], [4], which
can possibly occur at the chip/die-attach interface or at the substrate/die-attach
interface.
‒ The long-term stability and reliability of the die-attach material should be high
for safe operation of the device. Lifetime and reliability models such as Coffin
Manson Law and Paris’ Law can be applied to the new die-attachments [11].
‒ The die-attachment process parameters such as bonding-temperature, bondingtime, bonding-pressure etc. must be selected in a way to minimize the thermal
and thermomechanical stresses [10], [12]. Moreover, they must not affect the
electrical properties of the devices after the mounting process.
1.2.2 Requirements for Interconnection
Wire and ribbon bonding are the most common techniques for electrical interconnection
of the power devices [13]. The following requirements have to be fulfilled for the hightemperature operation of interconnection material.
‒ The material must withstand temperatures as high as 500 ºC or above. Common
interconnect materials such as Cu and Al often get oxidized at high-temperatures
[7], which reduces the cross sectional area of the wires.
‒ The interconnection material must exhibit good electrical properties. While
operating at high-temperatures, they should be able to carry high current
densities [14] .
‒ At high-temperatures, the material must be mechanically stable [15].
‒ The thermal and thermo-mechanical stresses must be minimized, which are
produced due to the local mismatch at the bonding sites and also due to the
global mismatch coming from the complete assembly [16], [17].
‒ The interconnection material must exhibit long-term stability and reliability [18].
1.3
Aims of the Thesis Work
This thesis work is aimed at investigating the die-attachment and interconnection
technologies for high-power and high-temperature electronic devices such as SiC
Schottky diodes and GaN-on-Si High Electron Mobility Transistors (HEMTs). For
mounting the aforementioned devices, Silver Sintering and foil-based Transient Liquid
Phase (TLP) bonding are selected as the die-attachment techniques, which are aimed at
high-temperature stability. The complete process development, optimization and
characterization of these die-attachments will be performed, while keeping in mind the
3
Chapter 1
Introduction
aforementioned high-temperature requirements. For performance comparison with the
current state-of-the-art die-attachments such as AuSn and AuGe solders etc., a set of
influencing parameters, for both processes and materials, is selected as described in table
1.1.
Table 1.1: Set of influencing parameters for die-attachment
1. Bonding temperature
Process-related
2. Bonding pressure
3. Process environment
1. Melting point
2. Electrical conductivity
Material-related
3. Thermal conductivity
4. High temperature stability
1. Bending stresses
2. Die-shear strength
Assembly-related
3. Active power cycling capability
4. Passive temperature cycling capability
5. Crack rates of die-attach layer
For electrical interconnection of GaN-on-Si HEMTs, gold and palladium are
investigated as bonding materials. The thin (ϕ = 50 µm) wire bonds are used during the
interconnection process. Whereas, a thick (ϕ = 300 µm) wire AlX (a novel Aluminum
alloy) is selected for interconnecting SiC Schottky diodes. Complete bonding process
optimization and characterization needs to be performed. For performance comparison,
the set of influencing parameters are described in table 1.2.
Table 1.2: Set of influencing parameters for interconnections
1. Current capability
Material and assembly-related
2. Bond pull strength
3. Active power cycling capability
The complete electrical characterization of the SiC and GaN-on-Si HEMTs from onwafer characterization to the final assembly process will be performed. The objective is
to analyze the thermal effects on electrical characteristics of the devices before and after
the assembly process. During various stages of assembly process, the on-state resistance
of the GaN and SiC devices will be selected as the performance parameter for
comparison. The on-state resistance of the device, both at low and high power levels, is
4
1.4
Thesis Outline
affected by the thermal resistance of the complete assembly, which will be measured for
both die-attachments. For GaN-on-Si HEMTs, a correlation has to be made between the
surface temperature Tsurface of the chip and actual channel temperature Tchannel. The
objective is to estimate the actual channel temperatures in the transistors during thermal
characterization and also during active power cycling. Based on accelerated tests i.e.
passive temperature cycling and active power cycling of SiC and GaN devices, the
reliability assessment of the die-attachments will be performed. The aim is to identify
the failure modes and to model fatigue in the new die-attachments i.e. Ag-sintering and
TLP bonding etc. using lifetime models such as the Coffin-Manson Law and the Paris’
Law.
In past, various investigations have been made on Ag-sintering as a die-attachment
process [4], [19], [20], [21], [22]. In thesis work, Ag-sintering is selected as a reference
die-attachment process, which exhibits excellent electrical and thermal properties. The
Transient Liquid Phase (TLP) boding or also known as Solid Liquid Inter-diffusion
(SLID) process is yet not a wide spread method for die-attachment in industry. Infineon
Technologies reports on a CuSn based TLP system for die-attachment of IGBTs [23],
[24], which faces its limitations in terms of brittle intermetallics of Cu3Sn and Cu6Sn5.
Furthermore, the high-temperature stability has yet not been thoroughly investigated for
active power devices. Numerous other sources also report on Ag-In, Au-Sn and Au-In
etc. binary systems, but they are not yet matured to be an industrial process [25], [26],
[27]. The interlayer TLP binary metals are mostly deposited by thin film deposition
processes. In addition, other process equipment requirements make it more complex. In
this work, a TLP interlayer system based on electroplated multilayer-foil will be
investigated, which is aimed at avoiding the aforementioned drawbacks of the current
TLP interlayer systems. The literature reports on the investigation of SiC diodes
mounted with Ag-sintering and AuSn TLP bonding [28], [29], [30]. However, both Agsintering and TLP bonding are the novel die-attachments techniques for the GaN
HEMTs. Based on die-attachment and interconnection characterizations, a new package
scheme will be proposed for GaN HEMTs and SiC diodes.
1.4
Thesis Outline
The thesis is organized in the following way. Chapter 2 describes the theoretical basics
of Ag-sintering and TLP bonding processes along with the reliability aspects of power
electronics packaging. Chapter 3 is dedicated for the current state-of-the-art hightemperature packaging techniques, including die-attachment and interconnection
methods. In chapter 4, the process optimization of the die-attachment and
interconnection processes is described along with the packaging materials. The chapter 5
explains the characterization methods for die-attachments and interconnections such as
Differential Scanning Calorimetry (DSC), Energy Dispersive X-ray (EDX)
Spectroscopy, Infrared (IR) Thermography, Digital Image Correlation (DIC), Die-Shear
Tests, and Bond-Pull Tests etc. The chapter 6 & 7 will give the packaging schemes for
5
Chapter 1
Introduction
SiC and GaN devices respectively. The electrical and thermal characterization of the onwafer devices to the final package is performed. The reliability investigations for dieattachments are performed after accelerated tests such as active power cycling. In
chapter 8, the comparisons with the current state-of-the-art die-attachment and
interconnection methods are discussed along with the conclusions.
6
2 Theoretical Background
This chapter describes the theoretical background of die-attachment techniques, which
have been investigated in this thesis work. Ag-Sintering and Transient Liquid Phase
(TLP) bonding are in the focus of discussion. These die-attachment methods are aimed
for their use in high-power and high-temperature applications of GaN and SiC devices.
In the following sections, the theory behind the Ag-sintering process and TLP bonding
process is discussed. The details of process parameters for both Ag-sintering and TLP
bonding are given, which greatly influence the materials properties of the Ag-sintered
and TLP bonded layers. The advantages and disadvantages of both techniques are also
described. Later on, a generalized power electronics package concept is explained.
Furthermore, the failure modes, physical degradation processes along with the lifetime
prediction models are discussed.
2.1
Sintering
Historically, sintering has been used for centuries for making ceramic tools. Today, it
also finds its applications in ultrasonic transducers, rocket nozzles, automobile engines
etc. In recent years, Ag-sintering has been widely used as die-attachment in power
electronic applications. A considerable research has been done to establish a connection
between the controllable variables in the sintering process such as pressure, temperature
and particle size etc. [19], [31] and properties of the final Ag-sintered layer.
2.1.1 Classifications of Sintering
In general, sintering can be classified into several types based on underlying mechanism,
which is responsible for the densification or shrinkage. Polycrystalline materials are
usually sintered using “Solid State Sintering”, which is proceeded by solid state
diffusion. On the other hand, amorphous materials are sintered using “Viscous
Sintering”, which uses the viscous flow for densification. “Liquid Phase Sintering” is a
type of sintering which makes use of a transient liquid phase at the sintering
temperature. The mechanism for Ag-sintering lies under the category of “Pressure
Assisted Sintering”, which makes use of an externally applied pressure to enhance
densification during a solid state diffusion process [19].
7
Chapter 2
Theoretical Background
Figure 2.1: Classification of sintering [32]
2.1.2 Sintering Process Mechanism
The entire sintering process is considered to be occurring in three stages. As the
processes occurring in each stage tend to overlap each other, there is no clear distinction
between the stages. However, some generalizations can be made to distinguish one stage
from the next one. During the first stage, in response to sintering forces a rearrangement
of particles occurs during sliding and rotation. This results in shrinkage and an overall
increase of the density of the material. The particles contact and formation of necks
occurs between them due to diffusion process. The second stage begins when the neck
radius starts further increasing and equilibrium shapes of the pores are attained as driven
by the surface and interfacial energies. Densification at this stage is assumed to take
place by reduction in cross sections of the pores. At last, these pores become unstable
and are pinched off from each other. During the last stage, the isolated pores are
completely eliminated and a density value closed to the theoretical value is achieved. In
addition, a possible grain growth can occur resulting in larger grain sizes at the expanse
of smaller grains [19].
The variables that determine the sinterability and the microstructure of the sintered joint
can be divided into two categories, which are material variables and process variables.
The sintering variables are described in table 2.1. The material variables usually
influence the powder compressibility and sinterability such as densification and grain
growth. Often mechanical milling and chemical processing is applied to improve
homogeneity of the powder. The process variables are mostly the thermodynamic
variables such as temperature, time, pressure etc. which greatly influence the quality of
final sintered layer [32].
8
2.1
Sintering
Table 2.1: Material and process variables [32]
Powder:
Material variables
Shape, size, distribution, agglomeration, mixedness,
etc.
Chemistry: Impurity, homogeneity, etc.
Process variables
Temperature, time, pressure, atmosphere, heating
and cooling rate, etc.
2.1.3 Low-Temperature Sintering Strategies
Because of their excellent electrical and thermal properties [31], sintered silver layers
are widely used as die-attachment in power electronics packaging. The major challenge
in silver sintering technique is the high-sintering temperature. In past, the research has
been done to reduce the sintering temperatures [19], [20]. During Ag-sintering process,
the densification rate of the sintering particles is related to driving force and the mass
transport mechanism, which is thermally activated. As the thermally activated mass
transport is low, the sintering driving force has to be significantly increased [19]. There
can be two ways to increase the driving force. Firstly with the application of external
pressure, the driving force can be increased and at the same time the sintering
temperature is lowered. Secondly, reducing the particle size can significantly increase
the surface energy. The excess surface energy becomes the driving force for the sintering
and results in the reduction of total interfacial energy. Thus reducing the particle size
from micron size to nanoscale can theoretically lower the sintering temperature. Both
strategies have their pros and cons, which will be discussed in the next sections.
2.1.4 Drawbacks of Nanoscale Particle Size
Although, nanoscale particle size of silver can significantly reduce the process
temperature. There are various drawbacks associated with nanoscale Ag-sintering pastes.
The drawbacks are agglomeration and aggregation, which can significantly reduce the
sinterability of nanoparticles. The figure 2.2 shows the difference between
agglomeration and aggregation. An agglomerate is a mass of interconnected particles,
which are held together by week forces such as Van der Waals forces and electrostatic
forces. The agglomerated particles can be dispersed by external energy such as
ultrasonic vibration and milling. On the other hand, aggregate is a mass of
interconnected particles bonded by strong chemical bonds. The aggregates can be barely
separated by external energy. Both agglomeration and aggregation result in
inhomogeneous distribution of particles and thus large voids can be easily formed. [19],
[20].
9
Chapter 2
Theoretical Background
Figure 2.2: Agglomeration and aggregation in nanoscale-particle sintering [20]
2.1.5 Low Temperature Joining Technique
The pressure-assisted low-temperature joining technique for the electronic devices was
first demonstrated by sintering large area silicon chips on top of the molybdenum
substrates [21]. This technique was based on sintering of Ag-powders and Ag-flakes.
These powders and flakes are covered with organic additives to protect them from
agglomeration and aggregation at room temperature. Other organic binders and sinter
additives are often included in the silvers paste containing these micron-sized flakes and
particles. The organic additives burn out at temperatures around 200 ºC [33]. Hence,
oxygen is often required to remove theses organic additives around the silver particles
and flakes.
The pressure assisted low temperature sintering technique is based on the atomic
diffusion of silver into the bonding surface. Therefore, the bonding surface must have
compatible metallization such as Ag or Ag on the surface. Moreover, often the bonding
surfaces also include a diffusion barrier layer of nickel below the surface finish layer
[21]. The external pressure helps to reduce the sintering temperatures in the range of
225 ºC to 300 ºC. The pressure assisted Ag-sintering process is carried out in the
following steps [20], [23], [34], [35].
10
Step 1.
Application of Ag-sinter paste using dispensing or screen printing on the
substrates.
Step 2.
Drying of the paste at about 150 ºC to burn out the organics inside the
paste.
Step 3.
Placement of the electronic component on the dispensed paste.
Step 4.
Sintering of the component is performed at temperature range of 225 ºC
to 275 ºC using pressure-assisted sintering process i.e. 10 MPa to
40 MPa. The sintering is carried in atmospheric air or in nitrogen
environment.
2.2
Transient Liquid Phase (TLP) Bonding
2.1.6 Advantages and Disadvantages of Ag-Sintering
The literature describes a number of key advantages of the Ag-sintered layers, which are
based on sintering pastes, formed using both nanoscale and microscale particles [19],
[20], [31], [36], [37].
− The melting point of Ag-sintered layer is 961 ºC, which is much higher than the
processing temperatures i.e. 230 ºC.
− Ag-sintered joints possess high thermal conductivity i.e. 100 – 200 W/mK.
− The thinner die-attach thicknesses i.e. 20 µm or less can be achieved with very
low thermal resistance.
− The electrical resistivity is very low i.e. 3.6 × 10-6 Ωm.
− It can be used as a possible attachment method of Ag-ribbons for electrical
interconnections on top of chips to replace wire bonds.
− Good reliability during passive thermal and active power cycling.
− The Si and SiC power devices have been demonstrated with Ag-sintered joints.
The main disadvantages of Ag-sintering are as follows.
− The processing times compared to soldering are relatively long.
− The pressure-less sintered layers may contain large porosities.
− The application of high bonding pressure may break the chip during the pressureassisted sintering process.
− The material properties of the Ag-sintered layers vary with the process conditions
i.e. sintering pressure, sintering temperature etc.
2.2
Transient Liquid Phase (TLP) Bonding
Transient Liquid Phase (TLP) bonding or commonly known as Solid Liquid Interdiffusion (SLID) process is a joining technique, which has ancient origin and has been
applied to many metallic systems [38]. In past, Wilde et al. has employed this technique
for successful contacting of solar cells using Au-In, Cu-Sn and Ag-Sn binary systems
[39]. In recent years, this technique has been widely used for power electronic
applications [23], [27]. The TLP bonding process offers several advantages such as
formation of high melting points binary alloys, flux free joining and void free interfaces
etc. [27], [38], [40]–[43].
11
Chapter 2
Theoretical Background
2.2.1 TLP Bonding Process
A schematic illustration of the process is shown in figure 2.3. The whole process is
mainly divided into following stages by Tuah-Poku et al. [44]
Stag1: Interlayer preparation
Stage2: Melting, dissolution and widening
Stage 3: Isothermal solidification and narrowing
Stage 4: Homogenization through post-bonding annealing
Figure 2.3: Four stages of TLP bonding [38]
Stage 1.
12
Firstly, a thin interlayer metal with a low melting point is placed between
two parent metals with high melting points. The TLP interlayer material
2.2
Transient Liquid Phase (TLP) Bonding
between the bonding surfaces can be produced by thin film deposition
processes such as sputtering and e-beam evaporation, by electroplating or
in the form of preforms of interlayer foils [38]
Stage 2.
Upon heating the entire system above the melting point of the interlayer
metal, a liquid layer is formed at the interface. The liquid layer then fills
the voids formed by unevenness of the mating surfaces. It may also
dissolve any residual surface contaminations at the interface [38]. The
liquid layer may also form because the reaction of interlayer metal with
parent metal can result in a low melting liquid alloy. The dissolution
process causes the interface to widen [40].
Stage 3.
With passage of time, the liquid layer at the interface diffuses completely
into the parent metal which results in isothermal solidification and
narrowing [38]. At this point, if desired the TLP process can be stopped.
The bond already has an elevated remelting temperature as compared to
the melting temperature of the interlayer metal [40].
Stage 4.
An optional bond homogenization step is often deployed at a suitable heat
treatment temperature. It can be an extended time in the same heating
chamber or a post-bond heat treatment applied at some other time [40].
2.2.2 Process Variables
Various process variables, which can affect the quality of the TLP bonded joint are
described in table 2.2 .
Table 2.2: Process variables of TLP bonding [38], [40], [45]
Process variables
Bonding temperature
Bonding pressure
Heating rate
Bonding time
Process environment
Annealing temperature and time
External pressure is usually applied to the bonding assembly to promote the bonding
process and also for the alignment of the assembly components. The literature describes
the pressure values between 1 and 10 MPa [40], [46], [47]. The heating of the bonding
assembly and the homogenization can be carried out with various equipments and with
various methods of heating such as radiation, conduction, radio-frequency, induction,
resistance, laser and infrared [40], [48]. Usually the process is carried out under vacuum
13
Chapter 2
Theoretical Background
[49]. However, the atmospheres such as nitrogen [40], [50], hydrogen [27], forming gas
(nitrogen and hydrogen) [38], [51] have also been reported. The time frame of the TLP
bonding is highly dependent on the material system and the experimental parameters
such as bonding pressure, temperature, interlayer thickness etc. The duration of the
bonding for individual stages of the TLP bonding in described in table 2.3.
Table 2.3: Times for discrete stages [38], [40], [47], [48]
TLP bonding stage
Time range
Heating to bonding temperature
Less than a minute to about
an hour
Melting of interlayer
Less than a second to several
seconds
Melting back of parent metal
Seconds to minutes
Isothermal solidification
Seconds to minutes to hours
Homogenization
Hours to days
The design of the interlayer thickness is also very critical to the TLP bonding process.
During the initial phase of heating, the interlayer material starts diffusing into the parent
metal. The magnitude of the diffusion depends upon the specific material combination.
As all solid-state diffusion rates increase upon heating, consequently, the heating rate
and interlayer thickness can significantly decrease the interlayer width. In some cases,
the complete interlayer can be dissolved before the melting temperature of the interlayer
is achieved. Although it is a very rare occurrence but still care has to be taken while
designing the interlayer thickness to avoid this scenario. The interlayer thickness also
depends on other variables such as bonding pressure, solid/liquid surface tension,
surface roughness of the parent metal and intermetallic formation [9], [40], [24]. The
bonding temperature is completely limited by the microstructural stability of the parent
metal [47], [52]. The literature describes the bonding temperatures vary from the optimal
bonding temperature to just above the melting points [44] or the bonding temperatures as
high as allowed by the parent metal [53], [54]. The intermetallic regions in a phase
diagram, which tend to slow down the diffusion rate, can be avoided by raising the
temperature [55].
2.2.3 Advantages and Disadvantages of TLP Bonding
− The TLP bond can operate at much higher temperatures than the bonding
temperature [40].
14
2.3
Power Electronics Package Concept
− Often TLP bonds have microstructural and therefore the material properties
similar to properties of the base metal. In some cases, the TLP bonded area
becomes indistinguishable from the other grain boundaries due to significant
diffusion. Such bonds are often as strong as the bulk substrate
materials [40], [56]. But this does not occur in thin-film based interlayer systems.
− The surface requires less joint preparation before bonding process. No fluxing
agent is required [40], [57].
− The liquid formed at the interface during TLP process fills the unevenness of the
mating surfaces and makes the costly surface finishing processes unnecessary
[38].
The main disadvantages of TLP bonding are as follows.
− The process is expensive compared to the other die-attachment processes [40].
− The formation of thicker layers of intermetallic compounds in the TLP joint may
cause to lower its strength and ductility [40].
− The time required for the isothermal solidification and sufficient bond
homogenization can be unfeasibly long [58].
− Formation of interlayer metal oxides may hinder the process [59].
The disadvantages of TLP bonding can often be avoided by optimized bonding
parameters at the cost of more experimentation.
2.3
Power Electronics Package Concept
The conventional Si-based power electronic modules such as insulated gate bipolar
transistors (IGBTs) and diodes etc. are usually mounted on a direct copper bonded
(DCB) substrate using a die-attach material. The electrical interconnections from the
chip to the substrate is usually made using wire bonds and interconnection to outside the
package can be realized with bus-bars, which are mounted on the substrate using a
solder material. The DCB substrate along with the chip and interconnections is then
mounted on a base plate. The generalized power package concept is depicted in figure
2.4. This package design is widely used in power electronics modules [60]. The hightemperature stable die-attachments i.e. Ag-sintering and TLP bonding can be used to
make chip-to-substrate connection, substrate-to-base plate connection and also for the
electrical interconnections. Consequently, the modules for high-temperature and highpower applications can be realized.
15
Chapter 2
Theoretical Background
Figure 2.4: Typical Si-power package design
2.4
Failure Mechanism of Power Modules
A typical power module as shown in figure 2.4 consists of different materials, which
have different coefficients of thermal expansions (CTEs). During the packaging process
and also during the device operation, the module undergoes cyclic temperature changes.
As a result, the interfaces between different materials are subjected to thermal and
thermo-mechanical stresses, which results in the failure of the module [60], [61].
Therefore, it is extremely important to identify and model the failure mechanism. The
well know weak points inside a standard wire-bonded power module are the bond wire –
chip interconnection, the chip – DCB solder joint and the DCB – base plate solder joint
[62].
The most common failure is the wire bond lift-off. The main reason behind the failure is
the local CTE mismatch between the wire bond (Al) and chip (Si), which occurs during
the cyclic temperature loads [60]. In addition, the wire bonds are also stressed due to the
global CTE mismatch, coming from the assembly [16]. Bond wire heel cracking is also
commonly observed in power modules. This failure occurs usually after long power
cycling tests and in the cases where the ultrasonic bonding process is not optimized [62].
The solder joint fatigue is a dominant failure mechanism in the power modules. The
DCB substrate-base plate solder joint is more critical than the chip-DCB substrate solder
joint because of larger CTE mismatch in the former. As the solder joint starts to crack,
the thermal resistance and temperature of the joint increases, which leads to a further
accelerated aging process [62]. The literature also reports on the cracks in the DCB
substrates and power modules such as IGBTs under cyclic temperature loads, which
create thermal and thermomechanical stresses [63].
16
2.5
2.5
Material Modelling
Material Modelling
The mechanical properties of the common solder materials vary with the temperature
and the rate of deformation. The solders often exhibit non-linear stress-strain behavior
(plasticity) and due to high homologous temperatures they tend to creep. The creep
behavior continues as long as the mechanical stresses are sustained. The creep rate dε/dt
is sensitive to variations in temperature and stress level and it can be also affected by the
creep history. Consequently, it is essential to take into account both the mechanisms of
creep and plasticity in a realistic thermomechanical life time assessment. A viscoplastic
deformation law, proposed by Anand, combines plasticity and creep in a unified physical
model as described in equation 2.1 [64], [65].
ε v = Ae
Where
-
Q
RT
σ
sinh ξ
s
1
m
2.1
ε v is the strain rate, R is the gas constant, T is the temperature in K, σ is the von
Mises equivalent stress, s is an internal variable that takes into account the
thermomechanical history like strain hardening and strain softening. A, Q, m are the
material constants. The procedures for determining the material parameters for solder
materials are described by Wang et al.[66]. For a whole deformation response of the
solder material, the elastic behavior such as temperature-dependent elastic moduli must
also be taken into account.
The materials models are included in the finite element simulations, which provide the
data about the distribution of stresses and strains in the solder joints. The damage
indicators are accumulated plastic/creep strain per cycle (∆εp) or plastic work density per
cycle (∆Wp), which are obtain from the hysteresis loops during cyclic deformation [60]
[64]. The total strain range is made up to elastic ∆εe, plastic ∆εp and a visco-plastic ∆εv
portions.
Δε t = Δεe + Δε p
2.6
Δε v
2.2
Crack Formation and Propagation Modelling
Based on plastic/creep strain per cycle (∆εp) obtained from the FEM simulations, the
crack initiation and propagation can be modelled. The crack initiation can be modelled
by equation 2.3 , which is in the form of Coffin-Manson law and predicts the number of
cycles to crack initiation Ni [64]
Ni = K
Δε v
2
1
C
2.3
17
Chapter 2
Theoretical Background
Where K and C are the material and temperature-dependent constants. The cracks
initiation is expected to be near the corners of the chip, where the shear stresses are
highest. A good CTE match between the bonding surfaces and an increased height of the
solder gap slightly increase the number to cycles to cracking [64]. After the crack
initiation, the crack propagates under the effect of low-cycle-fatigue, which can be
modelled by Paris’ Law which is in the form of equation 2.4. The process kinetics of the
crack rate can be described by the strain amplitude and material parameters c1 and c2
[64], [67].
da
= c1 (Δε v )c2
dN
2.4
The number of cycles Na to an actual crack length can be determined by numerical
integration when the dependency of strain range on the position across the solder joints
is available as a result of FEM simulations [64].
a
Na =
0
da
dx =
dN
a
0
1
dx
c1 (Δε v )c2
2.5
Based on the aforementioned equations 2.3 to 2.5, the number of cycles to crack
initiation and crack propagation can be modelled.
2.7
Crack Propagation in Ag-Sintered Joints
Various investigations have been made to determine the crack propagation rates in the
silver sintered joints, which are subjected to various thermal shock cycles [68], [69],
[70]. The table 2.4 summarizes the details of Ag-sintered assemblies, sintering process
conditions, thermal shock cycles and crack rates.
Table 2.4: Crack rates for Ag-sintered layers [68], [69], [70]
Assembly details
Thickness of
sintered layer
Sinter process
conditions
Temperature
shock cycles
Crack rates,
da/dN
Si chip 9 × 9 × 0.13
mm on 1.5 mm Cu.
38 µm
Ag-microflakes,
230 ºC, 40 MPa
-40 / +80 ºC
25 nm/Cycle
Si chip 9 × 9 × 0.13
mm on 1.5 mm Cu.
38 µm
Ag-microflakes,
230 ºC, 40 MPa
-55 / +125 ºC
85 nm/Cycle
30 µm
Ag-nanoparticles
275 ºC, 10 MPa,
1 min
-5 / +175 ºC
640 nm/Cycle
30 µm
Ag-nanoparticles
-5 / +175 ºC
3.6 µm/Cycle
Si chip
7.8 × 7.8 × 0.3 mm
on 1 mm Cu
18
2.8
Assembly details
Thickness of
sintered layer
Sinter process
conditions
Lifetime Prediction Models
Temperature
shock cycles
Crack rates,
da/dN
275 ºC, 2 MPa,
1 min
Si chip
10 × 10 × 0.375 mm
on Al2O3 DCB
400 mm2 DCB on
2.5 mm Cu
2.8
40 µm
/
-40 / +125 ºC
38 nm/Cycle
50 -100 µm
Ag-microflakes,
250 ºC, 30 MPa,
1 min
-40 / +125 ºC
< 100 nm/Cycle
Lifetime Prediction Models
In this section, the analytical lifetime prediction models for die-attachment and
interconnection failure in power modules will be discussed. The physics of failure
approach combines the mathematical modelling combined with the accelerated life
testing to predict the reliability of a module. The accelerated tests include passive and
active power cycling [60]. The analytical lifetime prediction models estimate the number
of cycles to failure based on junction temperature swing (∆Tj), medium temperature Tm,
frequency f, and bond wire current etc. A simple lifetime model, which takes into
account the temperature swing (∆T) is based on the Coffin-Mansion model. The
mathematical formulation is given in equation 2.6 [62]. The parameters a and n can be
obtained by numerical simulation and experimental measurements during power cycling.
Ciappa et al. have used this model to predict the module failure due to wire bond lift-off
[71].
Nf
a( T)-n
2.6
An improved analytical model has been proposed to include both the medium
temperature Tm and junction temperature swing (∆Tj) [62]. The medium temperature is
taken into consideration by means of an Arrhenius term, where activation energy E a is
determined experimentally. This model has been used to predict the module failures
because of solder fatigue during power cycling of IGBT modules.
Nf
-n
a( Tj ) e
Ea
(kTm )
2.7
Where ∆Tj is the junction temperature swing, Ea is the activation energy, k is the
Boltzmann constant and Tm is the medium temperature. The medium temperature Tm is
determined from the high (Thigh,j) and low (Tlow,j) junction temperatures during the power
on- and off-times respectively [13].
19
Chapter 2
Theoretical Background
Tm
Tlow, j
Thigh, j - Tlow, j
2
2.8
Bayerer et al. [72] presented a lifetime estimation model containing a large number of
parameters which take into account the influence of various parameters of power cycling
tests and power module characteristics. Besides the junction temperature swing (∆Tj),
the heating time ton (sec) during power cycling, current I (A) per bond stich on the chip,
bond wire diameter ϕ (µm) and block voltage V (volts) is included in the equation 2.9
[13].
Nf = K(ΔT) e
-β1
β2
Tlow
t βon3 Iβ4 Vβ5 Dβ6
2.9
Where the constants K and β1 to β6 are determined experimentally.
The number of cycles to failure for large solder joints due to thermo-mechanical fatigue
can be modelled by a Coffin-Manson power law given by equation 2.10 [71].
N f = 0.5
LΔαΔT
γx
1
2
2.10
Where L represents the lateral size of the solder, ∆α is the CTE mismatch between the
chip and substrate, ∆T is the temperature swing, c is the fatigue exponent, γ is the
ductility factor and x is the thickness of the solder layer. This model is often used to
model the fatigue cracks in the solder joints due to brittle intermetallics [71].
2.9
Summary
This chapter describes the theory behind the Ag-sintering and TLP bonding. The
sintering process normally requires substantially high temperatures, which can possibly
accede the maximum temperature that a semiconductor device can withstand. Moreover,
high process temperature can result in large thermo-mechanical stresses during the
assembly process. Two strategies have been used to reduce the sintering temperatures.
The nanoscale particle size approach helps to significantly lower the sintering
temperatures. However, the problem of agglomeration and aggregation in nanoparticlesbased sintering pastes pose considerable challenge to the sintering process. The pressureassisted microscale particle size approach allows the sintered joints to be made at lower
temperatures. The sintered joints exhibit properties similar to the bulk silver. TLP
bonding offers an alternative way to produce the high-temperature stable die-attachment.
The TLP bonding process is a more complex bonding technique, which requires more
resources to implement as compared to Ag-sintering process. Both Ag-sintering and TLP
bonding can be used to make the chip-substrate and substrate-base plate solder contacts.
20
2.9
Summary
The high-temperature stability of the electronic package can be improved with these dieattachments. The most common failures in power packages are caused by the solder joint
fatigue and wire bond lift-off etc. An important aspect of the reliability assessment is the
modeling of material properties. The viscoplastic and creep behavior of the common
solder material can be modelled by Anand Law. Including more accurate material
models in FE simulations result in determining damage parameters such as strain range
∆εv, which in turn can be used to determine the life time of the solders. A number of
analytical models exist which combine results from accelerated testing with the
mathematic models to determine the lifetimes of various failures such as solder fatigue
and wire bond lift-off etc.
21
3
State-of-the-Art
In this chapter, the assembly and packaging techniques for high-power and hightemperature electronic devices are described. The chapter starts with an introduction to
the wide bandgap semiconductor devices as they would replace silicon-based devices in
future high-temperature and high-power applications. The details on GaN-on-Si High
Electron Mobility Transistor (HEMT) and SiC merged PN/Schottky diode are explained.
Later on the state-of-the-art die-attachment and interconnection methods are described.
All die-attachment process parameters and key material properties are given. As
packaging is aimed at high-temperature applications, the details of characterization
techniques are also discussed.
3.1
High-Temperature High-Power Devices
The silicon has been used as the most common semiconductor material for power
electronic devices such as IGBTs, MOSFETs and diodes etc. Based on Si-devices,
power electronic modules like inverts, converters and rectifiers etc. are employed in
various high-power applications [73]. With the ever increasing demand of high-power
density, faster switching and device operation in harsh high-temperature environments,
Si-technology faces its inherent limitation. Due to its narrow band gap (1.1 eV), Si-based
devices cannot operate above 200 ˚C. The state-of-the-art wide band gap semiconductor
materials, which include gallium nitride (GaN) and silicon carbide (SiC), have been
proposed to overcome the inherent shortcomings of silicon devices. The table 3.1
summarizes the key material properties of wide bandgap semiconductors and Si.
Compared to Si, both SiC and GaN have much wider bandgaps, which offer advantages
such as higher achievable junction temperatures and thinner drift regions that give low
on-state resistances [74], [75]. The major advantages of these wide band
semiconductors, which make them useful for the manufacturing of power devices, have
been reported by Ozpineci and Tolbert [4], [76].
‒ Wide bandgap (WBG) power devices can operate at higher temperatures [4]. The
SiC power devices with maximum operating temperatures up to 300 ºC [6] have
been reported, which are much higher than the operating temperature of Si
(150 ºC).
− Because of the higher critical field strength, these devices have high breakdown
voltages as compared to Si [7], [76], [77].
22
3.1
High-Temperature High-Power Devices
− The switching losses are reduced due to very low reverse recovery currents.
Consequently, these devices can operate at higher frequencies [4], [76].
− The WBG devices based on SiC (370 W/mK) and diamond (2200 W/mK) have
higher thermal conductivity. Therefore, they possess lower junction to case
thermal resistances and as a results heat is more easily transferred out of the
device. GaN (130 W/mK) is an exception in this case [76].
Table 3.1: Characteristics of wide band gap semiconductors [4], [5]
Bandgap (eV)
Thermal
conductivity
(Wm-1K-1)
Breakdown
field strength
(MVcm-1)
Theoretical
maximum
operating
temperature
(˚C)
Si
1.1
150
0.3
150
6H-SiC
3.0
490
2.5
700
4H-SiC
3.2
370
2.2
750
GaN
3.4
130
3.0
>700
Semiconductor
material
Besides the advantages of WBG semiconductor devices, there are also some drawbacks
that limit their widespread use.
− The process yield is low because of defects in SiC and processing problems for
GaN [76].
− The process costs are relatively high [76].
− The high-temperate packaging techniques have yet not been matured [4], [76].
In the following sections, the state-of-the-art GaN and SiC devices will be discussed that
are later used in the experimental work.
3.1.1 GaN-on-Si HEMT
The GaN heterojunction field-effect transistor (HFET) or high electron mobility
transistor (HEMT) on Si has been reported as an important configuration to realize a
low-loss high-power device as well as the cost-effective solution. These GaN-on-Si
devices have a lateral design. These devices are able to operate at high-frequency and
under high-temperature conditions. In these devices, a two-dimensional electron gas
(2DEG) is generated at the interface of AlGaN/GaN heterostructure, which results in a
layer with high electron mobility and high carrier density due to its piezoelectric and
spontaneous polarization effects [78]. Consequently, the AlGaN/GaN heterostructure
23
Chapter 3
State-of-the-Art
can obtain high speed and large currents [79]. The cross section of an HFET device
structure on Si is shown in figure 3.1.
Figure 3.1: Cross section of GaN-on-Si
HEMT by Ikeda et al. [79]
Figure 3.2: Pulsed (150 µs) IV characteristics
of GaN-on-Si device developed with a gate
width of 259 mm at Fraunhofer IAF Freiburg
[80]
The literature describes the growth of AlGaN/GaN HEMTs on various substrates such as
SiC, sapphire, AlN, Si and diamond [81], [82]. The Si substrate is one of the most
promising candidates for growing GaN epitaxial layers due to the low cost and obtaining
a large diameter. The drawbacks are the large lattice mismatch between the Si and
epitaxialy grown layers, and a large CTE mismatch between the GaN and Si materials.
Consequently, buffer layer structures are included to reduce the lattice parameter of the
substrate towards the overlaying layers. In addition, the thermal conductivity (150 Wm1 -1
K ) of Si in comparison with SiC (370 Wm-1K-1) can contribute to self-heating effects
of the GaN-on-Si devices during device operation. An extensive research has been done
in order to improve the growth of GaN-on-Si substrate to advance the commercial
competitiveness of GaN HEMTs [79], [83]. Waltereit et al. have demonstrated GaN-onSi HEMTs, which are capable of delivering 1000 V breakdown voltage, 95 A of output
current and a lower product of on-state resistance and gate charge in comparison with
conventional Si-based devices. The forward IV-characteristics of a GaN-on-Si device
(Gate width: 259 mm) during pulsed (150 µs) operation are depicted in figure 3.2 [80].
The table 3.2 gives a comparison of key electrical properties for GaN-on-Si HEMT and
Si Power MOSFETs [84].
Table 3.2: Comparison of electrical characteristics [84]
24
Devices
GaN-on-Si HEMT
Si Power MOSFET
Si Power MOSFET
Source
Fraunhofer IAF
Freiburg.
Infineon
Technologies
(IPP60R099C6)
STMicroelectronics
(STP11NM50N)
3.1
High-Temperature High-Power Devices
Devices
GaN-on-Si HEMT
Si Power MOSFET
Si Power MOSFET
Area, A (mm2)
12
28.8
7.8
On-state resistance,
RON (mΩ)
72
91
450
Area-specific onstate resistance,
RON×A (mΩcm2)
8.6
26.2
35.1
Breakdown voltage,
VBR (V)
650
650
550
Pulsed (0.1 ms)
forward current,
ID, PLS (A)
58
78
14
The GaN-on-Si HEMTs have demonstrated comparable performance of commercial
state-of-the-art Si power devices. However, there is still a lot of potential for
improvement of electrical characteristics of GaN-on-Si HEMTs [84].
3.1.2
SiC Merged PN/Schottky Diodes
Silicon carbide (SiC) schottky diodes are the state-of-the-art devices used in high
efficiency and high power switch-mode power supplies because of their outstanding
performance as compared to Si diodes. SiC has a higher critical field strength.
Consequently, the Schottky diodes working up to VReverse = 3000 V have been reported.
The major advantage of these devices is the achievement of lower reverse recovery
charges. On the other hand, these SiC Schottky diodes have relatively low surge current
tolerance because of their unipolar nature and a significant positive coefficient of
resistivity. This may lead to thermal runaway during high overload currents, which also
occurs in Si-based Schottky diodes [85], [86].
A solution to this problem can be achieved by creating bipolar current conduction during
high current pulses through the diode. This is done by implementing a “merged PN
Schottky structure”, which uses a Schottky interface for nominal current operation and a
PN interface for high current operation. The schematic structure of 2nd generation SiC
Schottky diode from Infineon Technologies is shown in figure 3.3. The embedded Pdoped islands offer two advantages. The first one is the capability of building a bipolar
current path during surge current conditions. This condition is reached as soon as the
threshold voltage of SiC PN-junction is reached. The second advantage is that during the
reverse operation, the edges of the p-areas are the positions of the avalanche breakdown.
25
Chapter 3
State-of-the-Art
This leads to a homogeneous breakdown throughout the active area of the chip. Bjoerk
et al. have measured pulsed (400 µs) IV-characteristics of 1st generation original
Schottky diodes and 2nd generation merged PN/Schottky diodes as shown in figure 3.4.
Clearly the merged structure has twice the current capability at a forward voltage of 7 V
[85].
Figure 3.3: Schematic of SiC merged
PN/Schottky diode by Bjoerk et al.[85]
3.2
Figure 3.4: Pulsed (400 µs) IVcharacteristics (Vf vs If) for original and
merged pn/Schottky structure by Bjoerk et
al.[85]
High-Temperature Die-Attach Solutions
For die-attachment of Si, SiC and GaN based high-power high-temperature devices
several die-attach solutions have been proposed. In the following sections, the issues
related to each die-attachment method will be discussed.
3.2.1 Lead-Free Solder Systems
In power electronics applications, the lead-free solders such as Sn96.5Ag3Cu0.5,
Sn96.5Ag3.5 and etc. are used as alternatives to lead-based solders, which are banned by
the European Union [87]. With their melting temperature around 220 - 250 ˚C, these
solders have been found suitable for Si-based power electronic devices, which can
operate up to a maximum of 150 ˚C [4], [88].
The gold-based eutectic die-attach systems such as Au80Sn20 and Au88Ge12 have been
widely used as high-temperature stable die-attach solutions. The eutectic AuSn and
AuGe solders melt at 280 ˚C and 356 ˚C respectively. Au80Sn20 soldering is often used
for microwave devices and laser diodes [89]. In comparison with AuGe solder, AuSn
has better thermal and electrical properties and hence it is more commonly used. For
both solders, the die-attachment processes do not involve use of flux. On the other hand,
the process temperatures are high for both solders. In addition, their high elastic modulus
26
3.2
High-Temperature Die-Attach Solutions
results in the generation of high thermo-mechanical stresses, which are originated during
the die-attachment process and also develop during high-temperature operation of the
devices. Consequently, large die sizes should be limited when such solder systems are
used [6].
3.2.2 TLP Bonding Systems
The gold-based TLP systems such as Au-Sn and Au-In have been widely investigated as
high-temperature die-attach solutions. This process has been used for the packaging of
SiC devices [6], [29], [89]. The TLP bonding has the advantage of low process
temperatures because of the low melting points of Sn (232 ˚C) and In (156 ˚C). The
resulting alloy formed as a result of diffusion of Sn or In into the Au, has a high melting
point. For instance, the TLP bonding process in case of AuSn can possibly result in the
formation of ζ (Au5Sn) and δ (AuSn) phases, which are stated as high-temperature stable
phases with melting temperatures of 519 ˚C and 419.3 ˚C respectively [6], [90]. In both
the Au-Sn and Au-In binary systems, increasing the percentage of Au in the final alloy
will rise the melting temperature of the alloy further. The metal depositions on chip or
substrates are performed in few microns using thin-film deposition techniques such as
evaporation and sputtering. Some key drawbacks with gold-based TLP bonding systems
are high material and equipment costs, which make these systems unsuitable for some
industrial die-attachment processes [88], [91].
In the past, Guth et al. have used a Cu-Sn TLP bonding process for the die-attachment of
insulated gated bipolar transistors (IGBT) modules [23]. The intermetallic phases such
as η (Cu6Sn5) and ε (Cu3Sn), were produced as a result of inter-diffusion of Sn into Cu.
These phases have melting points of 408 ˚C and 676 ˚C respectively. Because of their
high elastic moduli of 119 GPa for η-phase and 143 GPa for ε-phase, these intermetallic
phases are found to be quiet brittle. Hence, cracks can easily propagate along the bonded
joint [88], [92].
The Ag-In and Ag-Sn based TLP bonding processes have been developed for hightemperature die-attach solution [59], [93], [94]. In case of Ag-Sn TLP bonding process,
material phases such as ζ (wt. % of Sn from 12.8 – 24.5 %) and Ag3Sn (wt. % of
Sn: 25 %) are formed by inter-diffusion process [93], [94]. These phases have melting
temperatures of 650 ˚C and 480 ˚C, respectively. The mechanical properties of Ag3Sn
phase suggests, that it is less brittle as compared to Au5Sn, Cu3Sn or Cu6Sn5
intermetallics, which makes it less vulnerable to crack propagation in the joint [92].
During the Ag-In TLP bonding process, material phases such as α (wt. % of In from 0 –
22.1 %) and Ag3In (wt. % of In: 25 %) are found [93]. Both material phases have
melting points beyond 600 ˚C [59], [94]. Further annealing of Ag-Sn or Ag-In
intermetallic joints causes a more uniform distribution of Sn or In in the Ag, which
increases the melting point of these joints. These processes avoid any use of flux. In
most of the published work, Ag, Sn and In layers are mostly deposited on the chip and
substrate by thin film evaporation process. The deposited layer thicknesses are in the
27
Chapter 3
State-of-the-Art
range of few microns. Various drawbacks such as interface diffusion and oxidation of
indium and tin are also reported with this technique [50], [59], [88].
3.2.3 Silver Sintering
Now a days, the silver sintering is the most widely adopted die-attach technique for Si
and SiC based devices [4], [6], [35], [37], [95]. The Ag-sintered layers have excellent
electrical, thermal and mechanical properties and they are very close to the bulk silver
properties. Ag-sintering materials are classified into nano- and microparticle based Agsystems.
The nanoparticle-based Ag-sintering materials have been reported for their use in the
sinter process. Nanoscale silver particles can be sintered at lower temperatures i.e. 250 350 ºC due to their large surface area. In these material, the solid state diffusion occurs
without any assistance of external pressure, which is usually required in miroparticlebased Ag-sintering materials. Bai et al. [31], [36] have reported successful use of
nanoparticle based Ag-sintering pastes. The silver paste consists of Ag particles in the
range of 25 nm to 30 nm. The particles are embedded in organic binder, dispersant and
thinner, which are burnt out quickly at low temperatures. The electrical and thermal
conductivities of the sintered silver layer were around 2.6 µΩ.cm and 2.4 W/cmK,
respectively. Nano-scale silver pastes are much more expensive than micro-scale silver
pastes. The extreme shrinking of nano-silver particles causes cracks in thick sintered
layers. Moreover, they suffer from the problem of particle aggregation and
agglomeration inside the paste [96].
The microparticle-based Ag-sintering materials are most commonly used during the
sinter process [23], [35], [34], [97]. Schmitt et al. have proposed several Ag-sintering
pastes with particle size ranging from 10 µm to 30 µm. The micron scaled silver powder
and sinter additives are stable and easy to handle [96]. The sintering process consists of
three steps. Firstly, the paste is screen printed or dispensed and dies are placed on the
substrates. Subsequently, the assembly is placed in the oven for drying out the organics.
In the final step, at temperatures ranging from 220 ˚C to 250 ˚C and with the help of
external pressure (10 MPa to 40 MPa) the dies are sintered. Depending upon sintering
conditions such as temperature and applied external pressure, sintered layers are
produced which can have material properties near to bulk silver.
3.2.4 Process Parameters of Die-Attach Methods
The details of process parameters for various die-attachment methods are summarized in
table 3.3. The process variables can contribute to the thermal and thermo-mechanical
stresses produced in the package, during the assembly process. Moreover, they should
not deteriorate the electrical properties of the electronic devices after the die-attachment
process.
28
3.2
High-Temperature Die-Attach Solutions
Table 3.3: Die-attachment process conditions
Material
System
Ag3.5Sn96.5
[98]
Au80Sn20
[99]
Au88Ge12
[100]
Au-Sn TLP
[101]
Au-In TLP
[39], [101]
Cu-Sn TLP
[101]
Cu-In TLP
[101]
Ag-Sn TLP
[39], [50]
Ag-In TLP
[27], [59], [101]
Ag-sintering
(Nanoscale)
[19]
Ag-sintering
(Micronscale)
[96]
Process
temperature
(ºC)
Bonding
duration
(min)
Bonding
pressure/force
Bonding
environment
250
1 – 1.2
/
Air
320
0.5 – 4
/
Nitrogen, Argon
410
0.5 – 4
/
Nitrogen
260
15
/
/
200
0.5
/
Vacuum
160 – 240
1 – 10
10 – 30 N
/
280
4
6 MPa
/
180
4
/
/
250
60
/
/
260
10
1.2 N
Nitrogen
250 – 350
1 – 10
10 – 100 N
/
210
10
0.3 MPa
Nitrogen
175
120
/
Vacuum
206
7
0.6 MPa
Hydrogen
280 – 350
15 – 60
No pressure
Air, Nitrogen
225 – 275
3 – 15
5 – 40 MPa
Air, Nitrogen
29
Chapter 3
State-of-the-Art
3.2.5 Material Properties of Die-Attachments
The key material properties of the high-temperature stable die-attach materials are
summarized in table 3.4. These properties include, melting points, thermal conductivity,
electrical conductivity, coefficient of thermal expansion (CTE) and elastic modulus.
Table 3.4: Die-attach material properties
Materials
Melting
temperature
(ºC)
Thermal
conductivity
(W/mK)
CTE
(ppm/K)
Elastic
modulus
(GPa)
Electrical
conductivity
105(Ωcm)-1
Sn96.5Ag3.5
[4], [22], [102]
221
78
22
50 – 56
0.8 – 1
Au80Sn20
[4], [103]
280
57
16
68
0.63
Au88Ge12
[4]
356
44
12
74
/
> 278
/
/
76 – 88
/
> 495
/
/
78 – 87
/
> 415
34 – 70.4
/
112 – 134
/
> 307
/
/
109 – 139
/
> 600
/
/
78
/
> 880
/
/
89 – 124
/
961
100 – 240
18 – 23
9 – 60
2.6 – 3.9
Au-Sn TLP
(intermetallics)
[104]
Au-In TLP
(intermetallics)
[105]
Cu-Sn TLP,
(intermetallics)
[106]
Cu-In TLP
(intermetallics)
[105]
Ag-Sn TLP
(intermetallics)
[106], [107]
Ag-In TLP
(intermetallics)
[105]
Ag-sintering
[37], [4], [96],
[103], [108].
30
3.3
3.3
Characterization Methods of Die-Attach
Characterization Methods of Die-Attach
As the Ag-sintering and TLP bonding are aimed at high-temperature applications,
various die-attachment techniques have been reported to determine the properties of dieattach layers. In the following sections some of these characterization techniques will be
elaborated which are later used during the experimental work.
3.3.1 Energy Dispersive X-Ray Spectroscopy
Energy Dispersive X-ray (EDX) spectroscopy is used to determine the chemical
composition of a solid state sample. The chemical information is obtained from the
excited characteristic X-rays of the specimen. A beam of high-energy electrons
penetrates and interacts with the sample emitting Bremstrahlung X-rays and
characteristic X-rays. The characteristic X-rays result from the electron transitions
between the inner orbits, with lower atomic energy levels. The characteristic X-ray are
collected in the EDX detector and used for the quantitative chemical analysis [109],
[110]. The Spatial resolution is determined by the penetration and spreading of the
electron beam in a particular sample. The lateral resolution is often about 1 to 2 µm
under typical conditions. The samples must be well polished so that the surface
roughness does not affect the results. If the sample surface is non-conducting, a
conducting coat such as vacuum-evaporated carbon, must be applied to provide a path
for incident electrons to flow to ground. The carbon has minimal influence on the X-ray
intensities and does not add unwanted peaks to the spectrum [111].
Table 3.5: Intermetallic phase development during TLP bonding
Material system for TLP bonding
Intermetallic phases
Ag-Sn [39], [43], [50]
Ag, ε (Ag3Sn), ζ (Ag85Sn15)
Cu-Sn [39], [43]
Cu6Sn5, Cu3Sn
Ag-In [59]
Ag, Ag2In, Ag3In
Au-In [39] [59]
AuIn, AuIn2
Au-Sn [41], [104]
Au5Sn, AuSn2
The EDX analysis is very often used to determine the composition of the material
phases, which are produced during the TLP bonding process. Literature describes the
composition analysis of various TLP joints based on Au-In, Ag-In, Ag-Sn and Cu-Sn
etc. The details of intermetallic compounds found during EDX analysis is summarized in
table 3.5.
31
Chapter 3
State-of-the-Art
3.3.2 Differential Scanning Calorimetry
The Differential Scanning Calorimetry (DSC) refers to the measurement of the change
of the difference in the heat flow rate to the sample and to a reference sample, while they
are subjected to a controlled temperature program [112]. When a sample material
undergoes a phase transition, more or less heat flows into the sample. For instance, once
the temperature has reached the melting point of the material phase, more heat will flow
into the samples in order to maintain the temperature of the sample at the same level
with the reference.
The DSC measurements are often used to measure the phase transitions and melting
points of the binary phase alloys, which are formed during the TLP process [26], [43],
[50]. Li et al. used the DSC measurements during the characterization of TLP bonding
of Ag-Sn-Ag interlayer system as shown in figure 3.5. The initial melting occurs at
221.3 ºC, which is melting point of 96.2Sn3.8Ag alloy. During the cooling phase the
solidification started at 201 ºC [50]. Often, the DSC measurements are used to analyze
the exothermal peaks in Ag-sintering process, which result as a result of organic burn
out as shown in figure 3.6 [113].
Figure 3.5: DSC measurement of Ag-Sn-Ag
TLP interlayer system during heating and
cooling phase [50]
Figure 3.6: DSC measurement of Ag-sintering
with heat treatment in air and nitrogen
environment [113]
3.3.3 Digital Image Correlation Technique
In electronics packaging, the thermally induced stresses are produced during fabrication
process such as die-attachment, encapsulation and also during the operation of electronic
devices. The stresses are produced due to the mismatch of the coefficient of thermal
expansions (CTE) of the materials comprising the package. The mechanical loadings can
be transmitted within the package through interconnects. Very often, the cyclic stresses
are produced during the power cycling of the modules. All of these issues can result in
die-attach failure, die fracture, interconnect breaking and encapsulation breaking etc.
[114].
32
3.3
Characterization Methods of Die-Attach
Digital Image Correlation (DIC) is a non-contact optical method for full-field
deformation measurement. This method traces the correspondence of the subimage
speckle patterns by finding the extremum of cross correlation coefficient in the reference
image and the deformed image captured before and after the deformation respectively.
The use of interpolation schemes and Newton-Raphson iteration method to search for
the extremum improves the measurement accuracy [114]. In electronics industry, DIC
method has been used to study the stresses in solder interconnects of BGA packages
under thermal loading [115], material characterization under thermal loading [116], out
of plane deformation of the substrate mounted dies [117]. and fracture toughness of the
underfill/chip interface due to temperature etc. [118], [119]. Kim et al. have used DIC
method to measure the out-of-plane deformation in the sensor chip and also for the
material characterization of molding compound as shown in figure 3.8 and figure 3.9
[117].
Figure 3.7: Schematic of DIC setup used by Kim et al. [117]
Figure 3.8: Out of plane deformation
measured by DIC method [117]
Figure 3.9: In-plane thermal strain of molding
compound. The slope gives CTE value [117]
33
Chapter 3
State-of-the-Art
The out-of-plane warpage in the sintered Si chips on Cu substrates have been measured
by Herboth et al. [120]. A good correlation was found between the DIC measurements
and FEM simulations using ANSYS. In these studies, the stresses were referred to as the
bending stresses in the chip.
3.3.4 Shear Tests
The bonding stability of the die-attachment is characterized by the die-shear tests, which
are conducted according to the test method “IPC-TM-650” [121]. During the active and
passive temperature cycling of the power electronic assemblies, very often the die-attach
layer is fatigued. Consequently, the shear strength goes down. The shear strengths of the
state-of-the-art die-attachments are summarized in table 3.6.
Table 3.6: Average shear strength of high-temperature stable die-attachments
Die-attachment
Au80Sn20
[122]
Au88Ge12
[123]
Average
shear strength
42 MPa
41 MPa
Ag-sintering
(Microscale)
36 MPa
[96], [97]
Ag-sintering
(Nanoscale)
40 MPa
[19], [97]
Ag-In TLP
[124]
Au-In TLP
[9]
34
20 MPa
>40 MPa
Average shear strength
(After temperature cycling)
38 MPa
2000 TS (-65 to +150 ºC)
>17 MPa
2000 TS (+40 to +360 ºC)
>20 MPa
1000 TS (-40 to +160 ºC)
>20 MPa
4000 TS (+50 to +250 ºC)
/
>30 MPa
120 TS (+35 to +400 ºC)
Comments
Si chips on AlN
DCBs
Si chips on Au
metallized Si3N4
substrates.
Si chips on DCB
substrates
SiC chips sintered
on AlN and Al2O3
DCB substrates
Cu chips TLP
bonded on Cu Agcoated substrates
SiC on Al2O3 DCB
substrate
3.4
3.4
High-Temperature Interconnection Methods
High-Temperature Interconnection Methods
With the advent of SiC and GaN based high-power devices, the demand for hightemperature stable interconnect material has continuously increased. The interconnection
material must also exhibit good electrical properties while operating at high
temperatures [14]. The literature describes various materials such as Al, Au, Ag, and Pt
for interconnection of SiC and GaN devices [103], [25], [125]. The table III gives the
details of various interconnection materials.
In past, Cai Wang et al. [25] have used especially drawn thick Au and Pt wires (Φ = 250
µm) for packaging of SiC devices. The used of gold and platinum wire bonding for highpower applications is hindered by their commercial unavailability in thick diameters.
Moreover, both gold and platinum-based wires are very expensive as compared to the
conventional aluminum and copper-based wires, which are used for power packaging. In
comparison with gold, the platinum is a hard material and it is extremely difficult to
bond. Thin silver wire (Φ = 50 µm) has also been used for the packaging of SiC devices
[125]. Due to its excellent electrical and thermal properties, it is an ideal material for
high power applications. A decrease of mechanical stability for Ag-wires has been
reported for operation above 350 ˚C [125]. The gold and aluminum thin wire bonds have
been reported as the interconnection materials for GaN packaging. The diameter of the
bonding wire depends mainly on the design of the underlying device. The literature
reports the use of the both Au-based wire (25 µm) and ribbon (12.5 µm × 100 µm)
bonding for GaN devices [126], [127]
Table 3.7: Material properties of interconnect materials [103]
Wire
diameter
Melting
point
Electrical
conductivity
Young’s
Modulus
(µm)
(ºC)
105(Ωcm)-1
(Gpa)
Al
25 – 300
660
2.3 – 2.8
68
24
Au
25 – 250
1064
4.5
73
14.2
Ag
25
961
6.3
76
19
Pt
250
1769
0.94
157
8.8
Material
3.5
CTE
(ppm/K)
Substrate Materials
In this section, the state-of-the-art substrate materials will be described. During the
packaging of high-power semiconductor devices, direct copper bonded (DCB) substrates
are usually used for mounting the devices.
35
Chapter 3
State-of-the-Art
Table 3.8: Material properties of ceramic materials [103]
Material
Density
(Kg/m3)
Elastic
modulus
Thermal
conductivity
(GPa)
(W/mK)
CTE
(ppm/K)
Dielectric
strength
(kV/mm)
Al2O3 96%
3970
310
24
6
12
AlN
3260
310
150 – 180
4.6
15
BeO
3000
345
270
7
12
Si3N4
2400
314
70
3
10
The DCB is a 3-layer sandwich structure consisting of an insulating ceramic substrate
along with a bonded copper layer on both sides of the ceramic. The substrate materials
are selected in a way to minimize the CTE mismatch between the chip and substrate.
Moreover, the thermal conductivity of the materials must be high in order to dissipate
the heat produced in the active area of the chip. The copper layer on DCB acts as a heat
spreader and it is often electroplated with a diffusion barrier layer of nickel and a surface
finish layer of silver or gold. The table 3.8 summarizes the key material properties of the
insulating ceramic substrates in DCB.
3.6
Applications
The wide bandgap SiC and GaN-based electronic devices are aimed at replacing current
Si-based devices in various high-power and high-temperature applications. The table 3.9
summarizes the details of some of potential applications with a description of chip
power, peak ambient temperatures along with current and future semiconductor
technologies.
Table 3.9: High-temperature applications [7]
High-temperature applications
TPeak, Ambient
(ºC)
PChip
(kW)
Current
technology
Future
technology
Automotive
On-cylinder and exhaust pipe
600
<1
/
WBG
Electric suspension and brakes
250
> 10
BS
WBG
Turbine engine
36
3.7
High-temperature applications
TPeak, Ambient
(ºC)
PChip
(kW)
Current
technology
300
<1
BS, SOI
600
<1
/
150
> 10
BS, SOI
600
> 10
Sensors, Telemetry, Control
Summary
Future
technology
WBG
Electric actuation
WBG
Spacecraft
Power management
300
1 – 10
BS, SOI
Venus & Mercury exploration
550
1
/
1
SOI
WBG
WBG
Industrial
High temperature processing
300 – 600
Deep-Well Drilling Telemetry
Oil and Gas
300
<1
SOI
SOI, WBG
Geothermal
600
<1
/
WBG
BS: Bulk Silicon, SOI: Silicon-On-Insulator, WBG: Wide Bandgap
3.7
Summary
This chapter gives a complete overview of state-of-the-art assembly processes i.e. dieattachment and interconnection and also the associated materials. The objective was to
give the advantages and limitations of these methods and materials. A set of process
parameters and material properties has been summarized. Later on, this set will be
compared to the properties of assembly methods and materials used during this thesis
work. At the end, potential high-temperature applications are presented. The dieattachment and interconnection processes and materials used in this thesis work are
aimed for their used in these applications.
37
4
Experimental Procedures
This chapter focuses on the process development and optimization of the die-attachment
and interconnection processes for high-power and high-temperature SiC and GaN
devices. In this thesis work, the Ag-sintering and Transient Liquid Phase (TLP) bonding
methods have been proposed as potential candidates for die-attachment. In the following
sections, the complete process parameter optimization is presented for both Ag-sintering
and TLP bonding methods. For TLP bonding process, an electroplating method was used
for producing multilayer foils as TLP bonding material. The multilayer foils were based
on tin-silver (Sn-Ag) and the indium-silver (In-Ag) based binary systems, which are
aimed at forming high-temperature stable material phases after the bonding process. A
detailed description of the design strategies for the foils is presented. The complete
development of the TLP interlayer material was carried out in-house.
For interconnection, gold, palladium and AlX (Al-alloy) based wire bonding processes
have been optimized. A detailed description of the bonding parameter optimization is
given at the end. Moreover, a detailed description of all the test substrates and test chips
is described. The metallurgical aspects on substrates and chip backside are also studied
here and their influence on die-attachment process is evaluated.
4.1
Substrates
The main substrates used during process optimization of Ag-sintering and TLP bonding
process were DCBs from Curamik GmbH and AlN substrates from Ceramtec GmbH.
The details of substrates along with their metallization are given in table 4.1. The surface
metallization was always performed in-house. The DCB substrates were electroplated
with nickel which acts like a diffusion barrier and a thin surface finish layer of gold or
silver. AlN substrates were sputtered with Ti-Ni-Ag or Au in the clean room (RSC) of
IMTEK, University of Freiburg. The gold and the silver metals are the most suitable
surfaces for the Ag-sintering process [34]. They also act as interface bonding materials
for TLP bonding processes. The surface roughness of the copper on DCB can possibly
reach up to a maximum of 20 µm as specified by the manufacturer. Therefore, DCBs
were optionally polished to achieve a smooth surface. This helped to reduce the
thickness of the die-attach layer. Consequently, a die-attach layer thickness below 10 µm
could also be achieved.
38
4.2
Test Chips
Table 4.1: Details of test substrates with contact metallization
Substrates
AlN DCB
Al2O3 DCB
Substrate
thickness
Metallization
5 µm - 0.5 µm
Ni: Diffusion
barrier layer
Ni - Ag
1.27 mm
Ti - Ni - Ag
4.2
Comments
Ni - Au
0.3 × 0.632 × 0.3
all in mm
Ti - Ni - Au
AlN
Thickness
50 - 100 - 200
all in nm
Au or Ag:
Surface finish
Test Chips
The silicon wafers were diced to various test chip sizes of 4 mm2, 9 mm2, 16 mm2,
25 mm2 and 49 mm2. The test chips were used during the process parameter
optimization of Ag-sintering process as well as the TLP bonding process. The test chips
had a backside metallization of Ti-Ni-Ag or Au as proposed in [34]. The metallization
were sputtered in the clean room (RSC) of IMTEK, University of Freiburg. The details
of chips along with the metallurgy are presented in table 4.2.
Table 4.2: Details of test chips with contact metallization
Chip
Si
Thickness
525 µm
Metallization
Ti - Ni - Au
Ti - Ni - Ag
Metallization
thickness
50 - 100 - 200
all in nm
Comments
Ti: Adhesion promoter
Ni: Diffusion barrier
Au or Ag: Surface finish
The impact of the seed layer of Ti on the adhesion of the metal stack to the die backside
surface was also studied. Before sputtering of Ti, the silicon wafers were cleaned with
Piranha solution (mixture of H2O2 and H2SO4) and dipped in HF acid to remove the
oxide layer. Later on the wafers were loaded into the sputtering machine and first
flushed with argon plasma to physically ablate the surface. Subsequently, the metals
(Ti - Ni - Au or Ag) were sputtered. This resulted in good adhesion of the metals on the
Si surface. Lack of any cleaning step resulted in poor adhesion of the metal stack on the
backside of the test chips. The Ni layer on die backside was deposited as a diffusion
barrier layer to prevent Ag and Au to diffuse into the substrate or die. The inclusion of
nickel layer was crucial for high temperature i.e. above 300 °C exposure of the chips
[35]. During the experiments, both the test chips and the test substrates were subjected to
a cleaning procedure. Both were first given an ultrasonic bath treatment in Isopropanol
39
Chapter 4
Experimental Procedures
and Acetone respectively for 3 minutes and later on rinsed with DI water. Afterwards,
the nitrogen gas was flushed over the surface for drying.
4.3
Die-attachment Methods
The optional set of the materials and processes is reduced significantly for the hightemperature applications. Various process parameters such as temperature, heating rate,
pressure, time and environment etc. have to be carefully selected in a way that they must
not deteriorate the operational functionality of an active device. In addition the material
aspects such as thermal conductivity and coefficient of thermal expansion (CTE)
matching of die-attachment, die and substrate have to be taken into account. In the
following sections the die-attachment processes and their parameter optimization will be
discussed.
4.3.1 Silver Sintering
For this thesis work, a “Pressure-Assisted Low-Temperature Sintering” technique has
been selected for investigations due to the following reasons. Primarily, the application
of external pressure significantly reduces the sintering temperature i.e. 220 ˚C to 250 ˚C.
The Ag-sintered layers have several advantages such as excellent electrical and thermal
properties and a melting temperature close to the bulk silver value i.e.961 ºC [20].
Figure 4.1: Sintering process steps [88]
40
4.3
Die-attachment Methods
4.3.2 Sinter Process
The paste-based sinter process can be divided into three stages. In the first stage, the
sinter paste is applied by dispensing or screen printing onto a substrate. Subsequently,
the chips are placed on the printed paste. In the second drying step, the assemblies are
placed in an oven and the organics inside the paste are dried out. Finally, in the last
sintering step the temperature is rapidly increased to the sintering temperature and an
appropriate sintering pressure is applied for few minutes. Later on, the whole assembly
is cooled down to room temperature. The process steps are described in the figure 4.1.
An Ag-sintered IXYS RF transistor on AlN DCB is shown in figure 4.2.
Figure 4.2: RF transistor (IXYS) attached on an AlN DCB using Ag-sintering
4.3.3 Materials
A novel microparticle based Ag-sintering paste LTS 275-3P2, was provided by Heraeus
GmbH. The paste consisted of micro-scaled silver particles, which are embedded in
organic binders and sinter additives etc. [96]. The material variables such as particle
shape, size, homogeneity, composition etc. were carefully selected and optimized by the
company. As instructed by the manufacturer, paste was stored at a temperature of 2 °C
to 6 °C. The paste was taken out of the fridge and brought to the room temperature
before application. The environmental conditions such as humidity and temperature
were noted before doing individual experiments. The details of the sinter paste as given
by the company are described in table 4.3.
Table 4.3: Details of Ag-sinter paste
Ag-Sinter paste
LTS 275-3P2
Particle size distribution
0.3 – 8 µm
Density of paste
3.7 – 4.3 g/cm3
41
Chapter 4
Experimental Procedures
Ag-Sinter paste
LTS 275-3P2
Viscosity
27 – 31 Pa.s
4.3.4 Application of Ag-Sinter Paste
The paste was applied using both dispensing and screen printing processes. For
dispensing process, the diameter of the dispensing needle, applied air pressure, and time
during the applied pressure were optimized to get a specific thickness of dispensed paste,
ranging from 25 to 100 µm. The optimized process parameters for dispensing process
are given in table 4.4. The dispensing setup is depicted in figure 4.3.
Table 4.4: Details of dispensing process parameters
Process parameters
Values
Air pressure
2.5 – 3 bars
Dispensing time
25 – 50 msec
Needle diameter
0.020 – 0.033 inch
Thickness
50 – 100 µm
Environmental
conditions
Temperature
23 – 26 ºC
Humidity
40 – 60 %
Figure 4.3: Setup for dispensing
42
4.3
Die-attachment Methods
For screen printing, the screen was obtained from KOENEN GmbH, such that the mesh
produced a layer thickness of 25 µm during the printing process. After drying out the
paste, the layer thicknesses remained up to 20 µm. As a result, several layers could be
printed over each other to produce a higher thickness of the die-attachment. With the
screen printing process, it was possible to get uniform layer thickness for all the samples
during experiments. The screen printer along with the screen, substrate holder and the
printed paste are shown in figure 4.4 to figure 4.7.
Figure 4.4: Screen printer
Figure 4.5: Substrate held by vacuum inside
holder
Figure 4.6:Screen along with the desired
pattern
Figure 4.7:Printed Ag-sinter paste on gold
surface
4.3.5 Sintering Setups
The schematics of the sintering setup are shown in the figure 4.8. A manual hot press
PW-20 from Paul-Otto Weber GmbH was used during the sintering process as shown in
figure 4.9. Both heating plates could achieve 10 °C/min ramping rate and were
controlled with a temperature controller attached with the setup. In addition, external
43
Chapter 4
Experimental Procedures
thermocouples were used to ensure the correct temperature reading from the inbuilt
temperature sensors. Both heating plates were hydraulically pressed and forces up to
200 kN could be applied with this setup. If the die is fragile or several dies are to be
bonded simultaneously, a soft material such as a high temperature stable silicon rubber
or polyimide foil can be placed above and between the dies.
Figure 4.8: Schematics of sintering setup [35]
Figure 4.10: Schematics of substrate bonder
Figure 4.9: WB-20 Hot press
Figure 4.11: SB6 substrate bonder
The Karl Suess SB6 substrate bonder shown in figure 4.11 was also used for the
sintering process. The schematics of the setup is given in figure 4.10. This bonder
consists of a chamber which is equipped with two heating plates (top and bottom) and
44
4.3
Die-attachment Methods
can be loaded up to a defined pressure. The chamber can be flushed with air or nitrogen
and can also be pumped down to create low pressure with a turbomolecular pump.
Compared to manual hot press, this bonder provides opportunity to carry out the sinter
process under different environmental conditions. Moreover, the external pressure
during the sintering process is more precisely controlled. Therefore, more thin and
delicate chips such as GaN HEMTs (150 µm) can be handled easily. The process
produces comparable results compared to the manual hot press.
4.3.6 Sintering Temperature Profile
The temperature profile in the figure 4.12 shows, that the dispensed or screen-printed
paste was firstly dried slowly at the rate of 2.5 °C/min up to 160 °C. It was kept for half
an hour to ensure that all organics are dried out. Then, the dies were heated quickly with
a rate of 10 °C/min to reach the temperature of 240 °C. In case of the substrate bonder, a
heating rate of 30 ˚C/min was used. At this point the pressure was applied for 3 minutes
and then removed instantly. The dies are then allowed to cool down slowly to the room
temperature.
Figure 4.12: Temperature profile for sintering [35]
4.3.7 Effects of Process Parameters
For Ag-sintering various process parameters were optimized, which included
temperature, time, atmosphere, heating rate and pressure. These parameters strongly
influence the properties of the final sintered joints. The objective was to find the most
suitable conditions, which not only result in stronger but also in reproducible bonds.
Shear strength of the sintered joint was selected as the comparison criterion for
45
Chapter 4
Experimental Procedures
parameter optimization. For statistical reasons, all sets of experiments were performed
with 20 samples with each combination.
Figure 4.13: Effect of sintering pressure on the
shear strength of Ag-sintered joints
Figure 4.14: Effect of sintering time on the
shear strength of Ag-sintered joints
Figure 4.15: Effect of heating rates during
drying and sintering process
Figure 4.16: Effect of process environment
and sintering pressure
It was found out that using high bonding pressure results in stronger die bonds as shown
in figure 4.13. Higher external pressure corresponds to higher driving force for the sinter
process. The figure 4.14 shows that increasing the sintering time beyond 5 min does not
increase the bonding strength. With passage of time as the sintered material becomes
more dense, effect of external driving pressure decreases rapidly. It was found that
during the drying step, the heating rate should be as low as possible to dry out all the
organics between the chip and substrate. Drying at high rate i.e. > 2.5 oC/min possibly
causes the formation of bubbles underneath the chip and results in voids in the die-attach
layer. This decreases the overall strength of the bond. After drying step, higher heating
46
4.3
Die-attachment Methods
rates should be preferred to reach the sintering temperature i.e. 240 ˚C. Rapid heating
increases the densification rate resulting in a stronger bond in shorter time. The effect of
heating rate is shown in figure 4.15. Furthermore, the bonding strength of the Agsintered joints formed in air is slightly higher than those formed in nitrogen atmosphere
as shown in figure 4.16.
Figure 4.17: Well bonded die on AlN
substrate after shear test [35]
Figure 4.18: Poorly bonded die on AlN
substrate after shear test [35]
4.3.8 Transient Liquid Phase Bonding
Transient Liquid Phase (TLP) bonding process has been used as high-temperature stable
die-attachment technique for power electronic devices and contacting of solar cells using
isothermal solidification. The advantages associated with this joining technique are
formation of high melting point binary alloys at relatively low bonding temperatures i.e.
200 °C, flux-free joining and void free interfaces etc. [39]. In this thesis work, Sn-Ag
and In-Ag binary systems are investigated as metallurgical basis for bonding of power
devices. Indium and tin metals have low melting points of 157 °C and 232 °C
respectively. Under appropriate environmental conditions, with the assistance of external
pressure and temperature, indium or tin melts and diffuses into the silver resulting in a
binary alloy, which is silver rich. Depending on the weight percentage of the two metals,
the reaction between Ag and In or Sn will result in a binary compound, which eventually
has a high melting point beyond 600 °C, [27], [39], [40]. TLP bonding can be an
effective die-attachment technique for wide bandgap semiconductors such as Silicon
Carbide (SiC) and Gallium Nitride (GaN). These high temperature devices are potential
candidates for various applications such as jet engines, nuclear reactors and space
electronics etc. [59]. An IXYS RF transistor mounted with foil-based SnAg TLP
bonding on an AlN DCB along with AlX wire bonds is depicted in figure 4.19.
47
Chapter 4
Experimental Procedures
Figure 4.19: RF transistor (IXYS) attached on an AlN DCB using Sn-Ag TLP boding [93]
Figure 4.20: Principle of Transient Liquid Phase Bonding starting from step 1 to 5 [12]
4.3.9 TLP Bonding Process
Transient liquid phase bonding (TLP) bonding process shown in figure 4.20 can be
summarized with the following four steps [38], [40], [93]:
48
4.3
Die-attachment Methods
1. The interlayer combination of metals is prepared in the form of foils or thin films
made by physical vapor deposition or electroplating. The interlayer consists of a
base-metal with a high melting point i.e. Au or Ag and an alloying-metal with a
low melting point i.e. Sn or In.
2. Upon heating above the melting point of alloying-metal i.e. In or Sn, a liquid
layer is produced at the interface. The liquid layer fills the voids formed by
unevenness of contact surfaces. In addition, an external force is applied on the
interlayer combination to guarantee an intimate contact between the mating
surfaces.
3. The interlayer combination is then kept at bonding temperature with a defined
external pressure until the liquid layer is isothermally solidified because of
diffusion. Depending upon the weight percentage of alloying-metal diffused into
the base-metal, various material phases can be formed in the resultant joint
4. An optional homogenization of the bond at suitable heat-treatment temperature
can be performed in the final step.
Figure 4.21: Binary phase diagram of Ag-Sn [128]
49
Chapter 4
Experimental Procedures
Figure 4.22: Binary phase diagram of Ag-In [128]
4.3.10 High-Temperature Stable Binary Compounds
The alloy phase diagrams of Ag-Sn and Ag-In in figure 4.21 and figure 4.22 respectively
will help to determine the high temperature phases produced during the TLP bonding
process. Both phase diagrams show that the composition of Ag-Sn and Ag-In binary
alloys, with contents of Sn and In up to 25 wt. %, would possibly result in high
temperature stable phases. Some of these high temperature material phases are
summarized in table 4.5 [128].
Table 4.5: High-temperature stable binary phases [128]
Binary system
Ag-Sn
Ag-In
50
Composition
(wt.% of Sn or In)
Melting
temperature (˚C)
Ag
0 - 12.5
725 - 961
ε (Ag3Sn)
25.5 - 27
480
ζ (Ag85Sn15)
12.8 - 24.6
600 - 724
α (Ag)
0 - 22.1
695 - 961
ζ
26.2 - 30
600 - 670
Ag2In
32.5 - 35
300
Phase
4.3
Die-attachment Methods
In the case of Ag-Sn and Ag-In binary systems, the following reactions can possibly take
place during the TLP bonding process [93].
3Ag  Sn  Ag3Sn
4.1
85Ag  15Sn  Ag85Sn15
4.2
3Ag  In  Ag3In
4.3
2Ag  In  Ag 2 In
4.4
4.3.11 Design Criteria of Multilayer TLP Foil
In this thesis work, foils were produced as multilayer materials for the TLP bonding
process, using the electroplating method. Various multilayer combinations of Sn-Ag and
In-Ag were proposed. Based on phase diagrams in figure 4.21 and figure 4.22, the
thicknesses of multilayer foils of Sn-Ag were designed to keep the overall starting
composition of 78.1 wt. % of Ag and 21.9 wt. % of Sn. Whereas, a composition of
74. wt. % of Ag and 25.98 wt. % of In was designed for the In-Ag multilayer foils. The
compositions had been selected so that after TLP bonding process, high temperature
stable binary compounds are present in the final bonded joints [93].
4.3.12 Multilayer Foil Preparation
During the foil preparation, a thin film of Au with a thickness of 250 nm, was deposited
as starting layer on a thin (300 µm) stainless steel carrier. Thereafter, thin layers were
deposited on to the gold seed layer. First, the alloying-metal with the lower melting i.e.
Sn or In was deposited. On top of it, the base-metal with higher melting point i.e. Ag
was deposited and finally a second layer of Sn or In was deposited. The resultant foil
was in form of a 3-layer sandwich structure [93]. Moreover, multiple layers of alloyingmetal and base-metal were deposited alternatively to produce a 9-layer foil. The 9-layer
foil structure has been proposed with the expectation of faster and more homogeneous
diffusion throughout the joint without any subsequent annealing step after TLP bonding.
In the case of In-Ag multilayer foils, the final layer was always covered with a capping
film of Ag, with a thickness of 400 nm. This was done in order to prevent the oxidation
of In layer. The interlayer combinations were then peeled off from the stainless steel
plate. The foils were placed immediately in Isopropanol solution (purity 99.5 %) to
prevent them from oxidation and stored at 4 °C to minimize the diffusion of In and Sn
into Ag. A more detailed description of foil deposition procedures and process
parameters can be found in the master thesis work of Y. Qin [121].
51
Chapter 4
Experimental Procedures
Figure 4.23: Process flow for multilayer foil preparation
4.3.13 Electrochemical Deposition
The multilayer foils were produced using the electroplating method. The detailed
description of the optimized parameters for electroplating bath can be found in Master
thesis work of Y.Qin [121]. With the optimized process parameter, a reproducible foil
deposition process was achieved. The table 4.6 gives the material properties, thickness
and deposition times of the all the electroplated metals.
Table 4.6: Material properties of electroplated metals [121]
52
Metal
Au
Ag
Sn
In
Valence number, z
1
1
2
3
Molecular weight, M (g/mol)
196.6
107.8
118.7
114.8
Mass density (g/cm3)
19.3
10.5
7.4
7.3
Deposition thickness
250 nm
20 µm
4 µm
5 µm
Deposition time (min)ʹ (sec)ʺ
2ʹ30ʺ
1h 24ʹ48ʺ
34ʹ10ʺ
8ʹ19ʺ
4.3
Die-attachment Methods
Figure 4.24 shows a stainless steel carrier plate along with the green tape covering the
edges. The deposition area of the multi-layer foils is defined by the exposed stainlesssteel surface. The electroplating setup is depicted in figure 4.25.
Figure 4.24: Stainless steel carrier [121]
Figure 4.25: Electroplating setup
The figure 4.26 and figure 4.27 show the Sn-Ag multilayer layer foil before and after
peeling off the stainless steel carrier plate respectively.
Figure 4.26: Multilayer foil along with steel
carrier plate
Figure 4.27: Multilayer foil after peeling off
53
Chapter 4
Experimental Procedures
4.3.14 Micrographs of Multilayer Foils
3-layer Sn-Ag foil
3-layer In-Ag foil
Figure 4.28: Micrographs of 3-layer sandwich foils adopted from [121]
9-layer Sn-Ag foil
9-layer In-Ag foil
Figure 4.29: Micrographs of 9-lay foils adopted from [121]
54
4.3
Die-attachment Methods
The micrographs in figure 4.28 and figure 4.29 show that after electroplating, the
surfaces of Sn-Ag multilayer foils are more uniform as compared to In-Ag multilayer
foils. Very often, a delamination is found in In-Ag multilayer foils after deposition of
silver layer on indium layer. From view point of electrochemistry, it is hard to deposit a
more noble metal i.e. Ag on a less noble metal i.e. In. Silver is higher in electromotive
series as compared to indium as shown in table 4.7. If the first layer of deposition is
indium and thereafter it is brought in contact with a silver ion solution for silver
deposition. A possible reaction is that silver will create solid metal while indium would
be dissolved in the solution according to the following reaction [129].
2Ag   In  2Ag  In 2
4.5
Table 4.7: Electromotive series [129]
Electrode
Reaction
emf (V)
Silver (Ag)
Ag+ + e- → Ag
+0.80
Tin (Sn)
Sn+2 + 2e- → Sn
-0.14
Indium (In)
In+3 + 3e- → In
-0.34
The electromotive series is given in table 4.7. The indium in comparison with tin has
higher potential to lose electron and turn into ion, which leads to non-uniform
distribution of silver nanoparticles on indium layer. The reaction can be lessened if tobe-deposited surface is immediately placed in the silver electrolyte after the dc current in
turned on.
Figure 4.30: Assembly concept using TLP bonding
55
Chapter 4
Experimental Procedures
4.3.15 TLP Bonding Experimental Setup
Karl Suess SB6 substrate bonder was used for TLP bonding process as shown in figure
4.32. The multilayer foil, as bonding material, is placed between the chip and the
substrate. The assembly concept is shown in figure 4.30. The resulting assembly is then
loaded into the process chamber, which is equipped with two heating plates. The plates
can be subjected to a defined pressure with the help of a pneumatic cylinder in order to
ensure an intimate contact between the mating surfaces. The chamber has a
turbomolecular pump to achieve a high vacuum during the process. The schematics of
setup is shown in figure 4.31. The process parameters such as temperature, bonding
time, bonding temperature, external pressure and environmental conditions are
controlled with a computer, which is attached with the setup. During TLP bonding, first
the chamber is evacuated to a starting base pressure, which is in the range of 1 to 4 × 104
mbar. Once the base pressure is reached, the assembly is pressed to defined pressure
i.e. 5 MPa. Afterwards, the stack is heated from both sides (top and bottom) at a
relatively high heating rate to a temperature, which is usually above the melting point of
alloying metal i.e. tin or indium. Once the required bonding temperature is reached, both
temperature and pressure are maintained for a certain period of time, during which the
isothermal solidification of the alloy is expected. Thereafter, the pressure is removed and
the assembly is allowed to cool at a slow rate. The bonded device is then taken out of the
chamber and optionally annealed in an oven to achieve a further bond homogenization.
A detailed description of TLP bonding process is presented in the thesis work of Y. Qin
[121].
Figure 4.31: Schematics of TLP bonding
using substrate bonder
Figure 4.32: Karl Suess SB6 Substrate bonder
4.3.16 Process Parameter Optimization
The process parameters used for TLP bonding process of Sn-Ag and In-Ag multilayer
foils are described in table 4.8. The shear strength of TLP joint was chosen as the
56
4.3
Die-attachment Methods
comparison criterion during the optimization process. A detailed description of complete
parameter optimization process can be found in the thesis work of Y. Qin [121].
Table 4.8: Optimized process parameters [121]
Multilayer foil system
Sn-Ag
In-Ag
Temperature, T
240 ˚C
210 ˚C
Heating rate, dT/dt
35 ˚C/min
35 ˚C/min
Cooling rate, dT/dt
2.5 ˚C/min
2.5 ˚C/min
Bonding pressure, P
5 MPa
15 MPa
Bonding time, t
30 min
30 min
Chamber pressure
2 - 4 × 10-4 mbar
2 - 4 × 10-4 mbar
Annealing time and environment
48 h in air at 200 ˚C
48 h in air at 200 ˚C
Figure 4.33: Effect of bonding pressure
Figure 4.34: Effect of bonding time
It was found that increasing the bonding pressure and bonding time results in increased
bonding strength. The limits were found for both Sn-Ag and In-Ag joints until a further
increase of pressure or time does not contribute any increment of bonding strength. The
limits were 5 MPa and 30 min for Sn-Ag joints, whereas, 15 MPa and 30 min were
found for In-Ag joints. Indium and tin are both susceptible to oxidation at ambient air.
This results in the formation of thin oxide layers [40]. Although, preventive measures
were taken after the production of the foils to minimize the oxidation of indium or tin, it
was still necessary to prevent any further oxidation of indium or tin during the TLP
57
Chapter 4
Experimental Procedures
bonding process. Therefore, bonding in both cases was carried out under reduced
environmental pressure of 2 × 10-4 mbar.
Figure 4.35: Effect of chamber environmental pressure
4.4
Interconnection Methods
In this work, wire bonding has been adopted as the interconnection method for GaN and
SiC devices, which are aimed at operation at high-power and consequently hightemperature. There are challenges associated with the use of materials for high
temperature applications above 250 ºC. Metallurgical aspects are needed to be explored
for both the chips and substrates in order to avoid the formation of intermetallic
compounds and to reduce the interfacial diffusion. While operating at high temperatures,
the bonding materials must be mechanically stable and their electrical conductivities
must be good enough to allow high current densities. Moreover, some materials get
oxidized at high temperatures which results in reduction of the effective cross section
area of the conductor. Keeping in mind all these challenges, gold and palladium were
selected as interconnection materials for contacting of GaN devices. Whereas, AlX (a
novel Aluminum alloy from Heraeus) was selected as interconnection material for SiC
devices. In the following sections, the wire bonding processes and their parameter
optimization will be presented.
4.4.1 Gold and Palladium Wire Bonding.
Gold and palladium were investigated as materials for high-temperature and high power
GaN devices. The bonding wires with diameter of 50 µm were used during the
interconnection process. The bonding wires were obtained from Heraeus GmbH and a
Delvotec 5430 thermosonic wire bonder was used for bonding. Palladium has
significantly higher hardness than the gold at room temperature as shown in table 4.9.
[15]. During the bonding, the sample was mounted on to a heated chuck and an
58
4.4
Interconnection Methods
ultrasonic bonding process was used in combination. The temperature range varied from
180 ºC to 220 ºC for gold and palladium respectively. This range did not accede the
temperature range of die-attachment process (230 ºC to 240 ºC) in order to avoid
additional thermo-mechanical stresses in the package.
4.4.2 Process Parameter Optimization
The parameters that influenced the bonding quality of the interconnection were bonding
force, ultrasonic power, ultrasonic power and temperature. The optimized parameters for
the wedge-wedge bonding process are shown in table 4.9. The pull strength of the wire
bond was selected as the comparison criterion for the optimization process.
Table 4.9: Optimized bonding process parameters, 1st*: substrate side, 2nd** chip side
Material
Gold
Palladium
Hardness in HV at 25 ºC [15]
25
55
Bond
1st*
2nd**
1st*
2nd**
Bond metallization
Au
Au
Au
Au
Bonding force (g)
30
25
35
30
Ultrasonic power (W)
0.76
0.62
0.79
0.65
Ultrasonic time (ms)
90
80
100
95
Temperature (ºC)
180
180
220
220
Figure 4.36: Effect of bonding temperature
on bond pull strength at bonding time of
80 ms
Figure 4.37: Effect of bonding time on bond
pull strength at bonding temperature of
220 ºC
59
Chapter 4
Experimental Procedures
4.4.3 AlX Wire Bonding
The AlX, an aluminum alloy from Heraeus GmbH, bonding wire (ϕ = 300 µm) was used
for electrical interconnection of the SiC diodes. This material has been proven stable up
to 300 ºC [130]. Orthodyne Electronics 360A ultrasonic large wire bonder was used for
bonding. The ultrasonic wire bonding process, at room temperature, was optimized for
various bonding surfaces such as aluminum, gold, silver and copper. For bonding
parameter optimization, a sample set of 20 wire bonds was selected. The pull force of
the wire bonds was selected as the comparison criterion. The table 4.10 summarizes the
optimized bonding parameters for various bonding surfaces.
Table 4.10: Optimized bonding process parameters
Force (grams)
Time (ms)
US power
(mW)
Bonding
surfaces
First bond
600
90
80
Second bond
600
100
90 - 100
Aluminum,
gold, silver
and copper
4.5
Summary
This chapter focuses on process optimization and characterization of die-attachment
methods i.e. Ag-sintering and foil-based TLP bonding. The details of all the test chips,
test substrates and die-attach materials are given along with the experimental setups. The
optimization of various process parameters such as bonding temperature, bonding time
and bonding pressure etc. has been shown for both die-attachments. The effect of the
process parameters on the strength of the joint was studied. For comparison purposes,
the die-shear strength was selected as the performance parameter. Furthermore, the
design concept and fabrication methods of the new TLP multi-layer foils based on SnAg and In-Ag binary systems were studied. A 3-layer sandwich and a 9-layer structure
was successfully developed for both Sn-Ag and In-Ag binary systems. However, there
are still some difficulties in producing the Ag-In multilayer foils. Cracks in the
multilayer structures and non-uniformity of the layers were often encountered. At the
end the process optimization of gold, palladium and AlX bonding materials has also
been described.
60
5
Characterization Methods and
Results
After the successful optimization of the process parameters for the die-attachment
methods i.e. Ag-sintering and Transient Liquid Phase (TLP) bonding in chapter 4, a
detailed description of the die-attachment characterizations is presented here. The dieattachments in this thesis work are aimed at high-temperature and high-power operation
of GaN and SiC-based electronic devices. Therefore, several aspects of the dieattachment such as melting points, high-temperature stability, thermal resistance, and
thermo-mechanical stresses need to be investigated in order for the reliable operation of
the semiconductor. In this chapter the following characterization will be explored.
1. Die-Shear Tests
2. Differential Scanning Calorimetry (DSC)
3. Energy Dispersive X-ray Spectroscopy (EDX)
4. Thermal Resistance
5. Electrical Conductivity
6. Thermal and Bending Stresses
7. Mechanical Characterization
8. Micrographs of Ag-Sintered and TLP Bonded Joints
5.1
Shear Strength
In order to check the stability of the Ag-sintered and TLP bonded dies, the shear tests
were performed using the bond tester Series-4000PXY from Dage Semiconductor
GmbH, Germany. A load cell (DS 100) up to 1000 N was used during the tests. The
chips were sheared off the substrate using a 9 mm wide chisel. The substrate was fixed
on the sample holder and the whole assembly was held firmly with the help of vacuum
on the table of bond tester. The shear force was applied with a velocity of 500 µm/s. The
test was conducted according to the test method “IPC-TM-650” [121]. The contact tool
i.e. chisel is assured to be parallel to the edge as shown in figure 5.1 and the chisel head
complete covers the edge of the chip symmetrically to guarantee a uniform force
distribution.
61
Chapter 5
Characterization Methods and Results
Figure 5.1: Parallel placement of contact tool (side view)
Both Si and SiC chips with surface area of 16 mm2 were mounted on AlN and Al2O3
substrates using Ag-sintering and SnAg-based TLP bonding. A sample size of 20 chips
was used. The mounted dies were subjected to passive temperature cycling from -40 ºC
to +150 ºC. The die-shear strength for both Ag-sintered and TLP bonded Si and SiC
chips after passive shock cycling remained above 35 MPa as shown in figure 5.2 and
figure 5.3. The shear tests were performed for both Si and SiC chips with various chip
sizes i.e. 4 mm2, 9 mm2, 16 mm2 and 25 mm2 etc. The effect of surface area of chips on
the shear strength of Ag-sintered and SnAg TLP bonded samples was determined as
shown in figure 5.4 to figure 5.7. The dies were mounted on both AlN and Al2O3 DCBs.
For smaller chip areas the shear force was found to be higher and it decreased sharply as
the chip area is increased. As the die-attachment is aimed at high-temperature operation,
Ag-sintered and TLP bonded samples were subjected to temperature cycles up to 500 ºC,
with a ∆T = 470 K. The bonded dies were heated at 94 ºC/min in a radiation oven and
kept for 500 ºC for 5 min. Thereafter, they were cooled down to room temperature with
23.5 ºC/min. The complete passive temperature cycle took 30 minutes. It was found that
after 20 shock cycles, the AlN DCBs were damaged while the dies were still present on
the substrates. The upper and lower copper layers of the DCB were delaminated. The
shear strength was measured for the dies still mounted on the upper copper surface.
Figure 5.2: Average shear strength for Agsintered chips after 1000 TS with ∆T = 190 K
62
Figure 5.3: Average shear strength for TLP
bonded chips after 1000 TS with ∆T = 190 K
5.1
Shear Strength
Figure 5.4: Average shear strength for Agsintered chips on AlN DCB
Figure 5.5: Average shear strength for Agsintered chips on Al2O3 DCB
Figure 5.6: Average shear strength for TLP
bonded chips on AlN DCB
Figure 5.7: Average shear strength for TLP
bonded chips on Al2O3 DCB
Figure 5.8: τAvg for Ag-sintered and TLP bonded chips on AlN DCB with ∆T = 470 K
63
Chapter 5
5.2
Characterization Methods and Results
Differential Scanning Calorimetry
The Differential Scanning Calorimetry (DSC) measurements were performed to measure
the melting points of the intermetallic phases that are produced during Sn-Ag an In-Ag
TLP bonding process. These measurements also confirmed the presence of identified
intermetallic phases, which are found using EDX measurements. The DSC
measurements were carried out using a NETZSCH DSC 204 F1 Phoenix differential
scanning calorimeter. The samples consisted of a 3-layer Sn-Ag-Sn or In-Ag-In foil,
which was bonded between two Si chips of 9 mm2 area. The Si chips had a backside
metallization of Ti-Ni-Ag (20-100-200 nm). The TLP bonded samples were placed in an
aluminum pan with a diameter of 5 mm. The pan was also covered with an aluminum lid
with a piercing to allow the purging gas to fill the space. The sample cell was placed
along with an empty reference aluminum cell in the heating chamber. The nitrogen gas
was purged with a rate of 20 ml/min inside the chamber during the DSC measurements.
The heating rate was set to be 10 ºC/min and the sample was heated from 25 ºC to
500 ºC. This range of the temperature was within the accuracy limits of the equipment.
Figure 5.9: Schematic layout of a sample in
an Al pan (ϕ = 5 mm) on a sample carrier
Figure 5.10:.Top view of the sample along
with the aluminum pan
A systematic analysis starting from the Sn-Ag and In-Ag multilayer foils to the final
bonded joints, both annealed and unannealed, was made. The objective was to find the
high-temperature stable material phases in the bonded TLP joint. A successful TLP
bonding process can possibly contain high-temperature stable phases of Sn-Ag and InAg binary systems in the final joint. An annealing process can make the TLP joint more
uniform in terms of composition. Consequently high-temperate stable phases are formed
[40].
64
5.2
Differential Scanning Calorimetry
5.2.1 Sn-Ag TLP Bonded Joints
The DSC measurement of the Sn-Ag foil in figure 5.11 shows that two peaks occur at
203.4 ºC and 221.8 ºC. According to the phase diagram, melting peak at 221 ºC is
identified as a eutectic melting point of Ag and Sn. The melting process includes an
unidentified phase change, which occurs at 203 ºC. The DSC measurements were also
made for the bonded joints before and after the annealing process. In the unannealed SnAg bonded joint as depicted in figure 5.12, the major melting peak was found at 480 ºC,
which is indicative of Ag3Sn phase. A small peak at 221 ºC shows the presence of the
eutectic phase after the bonding process. The bonded samples were annealed at 200 ºC
for 48 hours. The objective was to obtain a uniform composition of Sn across the Sn-Ag
joint. The DSC measurement of an annealed joint in figure 5.13 shows the presence of a
small rest of Ag3Sn phase, which melts at 480 ºC. It can be stated that majority of the
phases have melting points beyond 480 ºC, which were identified as ζ-phase by EDX
measurement.
Figure 5.11: Melting points of TLP 3-layer Sn-Ag foil
Figure 5.12: Unannealed Sn-Ag bonded joint
Figure 5.13: Annealed Sn-Ag bonded joint at
200 C for 48 hours
65
Chapter 5
Characterization Methods and Results
5.2.2 In-Ag TLP Bonded Joints
The DSC measurements of the 3-layer multilayer foil in figure 5.14 shows the presence
of several intermetallic phases in the foil. The melting peak occurring at 145 ºC indicates
the eutectic melting phase of In and Ag. Whereas, the melting peaks at 171 ºC and
187 ºC represent the Ag2In and Ag3In phases. Literature reports fast diffusion of indium
into silver soon after the deposition process leading to Ag2In and Ag3In phases [105],
[131]. In the bonded In-Ag joint as shown in figure 5.15, small portions of eutectic and
Ag3In phases are still present in the joint. Once the joint is subjected to an annealing
process at 200 ºC for 48 hours as shown in figure 5.16, the melting peaks found in the
unannealed sample are vanished. Within the accuracy limits of the equipment it can be
stated that the material phases produced after the annealing process have melting points
beyond 450 ºC. These phase were identified as α and ζ phases by EDX measurements.
Figure 5.14: Melting points of TLP 3-layer In-Ag foil
Figure 5.15: Unannealed In-Ag bonded joint
66
Figure 5.16: Annealed In-Ag bonded joint at
200 C for 48 hours
5.3
5.3
Energy Dispersive X-ray Spectroscopy
Energy Dispersive X-ray Spectroscopy
In order to prove the TLP bonding principle and to analyze the composition of the
intermetallic phases in the bonded joints, Energy Dispersive X-ray Spectroscopy (EDX)
was performed. The sample for the EDX analysis consisted of a Si chip, which was TLP
bonded onto a Si substrate using a multi-layer Sn-Ag or In-Ag foil. Both Si chip and
substrate had a metallization of Ti-Ni-Ag (20-100-200 nm), which is essential for
interface connection. Several samples of both unannealed and annealed samples of SnAg and In-Ag TLP bonded joints were cross-sectioned and later on polished for the EDX
analysis. The average TLP joint thickness was about 30 µm. Firstly, the analysis will be
shown for the unannealed SnAg and InAg bonded joints. Later on, the effect of
annealing on the diffusion of Sn and In in to the Ag will be presented. Additionally, the
results of the 9-layer interlayer foil will also be presented, which are aimed at avoiding
the additional annealing step.
5.3.1 Sn-Ag TLP Bonded Joints
The EDX analysis of the 3-layer Sn-Ag TLP bonded joint (30 µm) after the bonding
process shows that the wt.% of Sn at both chip/foil and substrate/foil interface is about
35 % and it decreases to 8 % while moving 7 µm deep into the foil on either side. The
center of the joint consists of an almost pure Ag phase. The wt. % of Sn and Ag across
the complete joint are depicted in figure 5.17. The possible phases present at the
interface are Ag3Sn and ζ as indicated in figure 5.18.
Figure 5.17: Joint composition of unannealed 3layer Sn-Ag TLP bond
Figure 5.18: Unannealed 3-layer Sn-Ag
TLP bonded joint with material phases
[121]
For the annealed samples, the EDX analysis shows a uniform distribution of Sn across
the complete interface as shown in figure 5.19. The annealing of the joint at 200 ºC for
48 hours causes the Sn to diffuse deeper into the Ag layer resulting in the formation of
the ζ-phase, which has a melting point beyond 700 ºC. The possible intermetallic phases
67
Chapter 5
Characterization Methods and Results
are indicated in figure 5.20. The EDX measurements were confirmed by the DSC
measurement in section 5.2.1.
Figure 5.19: Joint composition of annealed 3layer Sn-Ag TLP bond at 200 ºC for 48 hours.
Figure 5.20: Annealed 3-layer Sn-Ag TLP
bonded joint with material phases [121]
5.3.2 9-layer Sn-Ag TLP Bonded Joints
The concept of the 9-layer Sn-Ag multilayer foil was developed to avoid the post
annealing step after the TLP bonding process. An EDX analysis was performed for a 9layer TLP bonded joint. The possible material phases found across the interface were Ag
and ζ-phase as shown in figure 5.22. It was found that a duration of 30 min at 240 ºC
was enough for the thin (1.3 µm) Sn layers to diffuse in to the Ag (2 µm). This resulted
in the formation of ζ-phase as indicated in figure 5.21.
Figure 5.21: Joint composition of unannealed
9-layer Sn-Ag TLP bond.
68
Figure 5.22: Unannealed 9-layer Sn-Ag TLP
bonded joint with material phases [121]
5.3
Energy Dispersive X-ray Spectroscopy
5.3.3 In-Ag TLP Bonded Joints
Figure 5.23: Joint composition of unannealed
3-layer In-Ag TLP bond
Figure 5.24: Unannealed 3-layer In-Ag TLP
bonded joint with material phases [121]
In a similar fashion, the EDX analysis of the In-Ag TLP bonded joints was also
performed. The analysis shows that weight percentage of indium at chip/foil interface is
about 40 % while it is about 35 % at the substrate/foil interface. Moving 3 µm into the
Ag metal, a weight percent of indium about 25 % is found and it decreases to 0 in the
center of the joint, which is pure silver. The compositions of In and Ag are shown in
figure 5.23. The possible phases in the joint are Ag2In and Ag3In as indicated in figure
5.24. The annealed In-Ag joint showed a uniform distribution of indium across the joint.
The weight percentage of indium varied between 8 % and 19 %, which indicates a ζphase as shown in figure 5.25. The possible intermetallic phases are indicated in figure
5.26. The EDX measurements were in agreement with the DSC measurements in section
5.2.2.
Figure 5.25: Joint composition of annealed 3layer In-Ag TLP bond at 200 ºC for 48 hours
Figure 5.26: Annealed 3-layer In-Ag TLP
bonded joint with material phases [121]
69
Chapter 5
5.4
Characterization Methods and Results
Thermal Resistance
The investigations were carried out in order to estimate the thermal resistance of the dieattach layer. For this purpose, Si diodes from Diotec Semiconductor were mounted on an
Al2O3 DCB substrate using both Ag-sintering and Sn-Ag based TLP bonding. The
electrical interconnections were made using aluminum wire bonds (ϕ = 300 µm). The
temperature on the surface of the chip was measured using a Pt-1000 sensor, which is
attached using a thermally conductive adhesive. The temperature at the bottom surface
of the DCB was measured using a Constantan wire in contact with the Cu surface, which
makes a thermocouple with a sensitivity of 39 µV/K. The materials and thicknesses of
all the layers in the assembly are given in table 5.1. The complete assembly was
mounted on a chuck with forced water cooling. The thermal resistance was calculated
using the equation 5.1. The thermal resistance of the assemblies was measured at
40 Watts for both TLP bonded and Ag-sintered diodes.
R th 
T Ttop(Chip surface) - Tbottom(DCB bottom)

P
Vd .Id
5.1
Where Ttop is the temperature measured on the chip surface, Tbottom is the temperature at
the bottom of the DCB, Vd is the diode forward voltage and Id is the diode forward
current. The principle of thermal resistance measurement is shown in figure 5.29.
Figure 5.27: Setup with mounted Pt-1000
sensor and with constantan wire
Figure 5.28: Si diode Ag-sintered on Al2O3
DCB substrate.
Table 5.1: Materials and thicknesses of the assembly layer for Rth measurement
Assembly
Materials
Thickness (µm)
Chip
Si
400
Ag-sintered
Die-Attach
70
Sn-Ag TLP bonded
30
5.4
Assembly
DCB Substrate
Thermal Resistance
Materials
Thickness (µm)
Cu
300
Al2O3
633
Cu
300
Figure 5.29: Principle of thermal resistance measurement
The measured thermal resistance of the Ag-sintered diode assembly, shown in figure
5.28, was slightly lower in comparison with the TLP bonded assembly. The difference in
thermal resistances ∆Rth, was found to be 0.014 K/W. We assumed that all layers in both
assemblies are identical except the die-attach layer. Thereby, the increase in thermal
resistance of the TLP bonded assembly can possibly be attributed to TLP bonded layer.
The thermal conductivity of Ag-sintered layer is reported from 100 to 200 W [31].
Relative to this value, the thermal conductivity of the TLP boned layer was calculated.
The thermal conductivity of a TLP bonded layer is calculated relative to Ag-sintered
layer with following equations.
R th,sintered 
d
sintered  A
 0.0074 K/W
R th  R th,TLP - R th,sintered  0.014 K/W
5.2
5.3
λ sintered = 200 W/mK
R th,sintered
R th,TLP
=
λ TLP
λsintered
5.4
λ TLP = 67 W/mK
The measured thermal resistances of the Ag-sintered and TLP bonded assemblies and
the calculated thermal conductivity of Sn-Ag TLP bonded layer relative to Ag-sintered
71
Chapter 5
Characterization Methods and Results
layer is shown in table 5.2. The thermal conductivity of TLP bonded layer is less than
the Ag-sintered layer. However, it is comparable to commonly used solders such
Au80Sn20, Au88Ge12 and Ag3.5Sn etc.
Table 5.2 Comparison of Rth and λ for Ag-sintered and TLP-bonded layers,
*: Literature values,**: Own values computed from measurements
Ag-Sintered layer
Sn-Ag TLP bonded
layer
Rth of complete assembly (K/W)
0.481
0.495
Thermal conductivity, λ
(W/mK)
200*
67**
Thermal conductivity, λ
(W/mK)
100*
54**
5.5
Electrical Conductivity
The electrical conductivities of Ag-sintered and TLP-bonded layers were also
characterized. The Ag-sinter paste LTS 275 3P-2 was screen printed in the form of a
meander on an Al2O3 substrate. After drying the paste at 160 ºC, the printed layer was
subjected to 5 cycles of 25 ºC to 350 ºC for 30 minutes. The thickness of the layer after
drying and temperature treatment was 18 µm, which was determined using a
profilometer. It was 250 µm wide and its total length was 440 mm. The substrate along
with the Ag-sintered pattern was placed in an oven and the 4-point method was used to
determine the resistance of the printed layers at various temperatures.
Figure 5.30: Screen printed Ag-sinter paste on Al2O3 substrate
72
5.6
Thermal Stresses in Die-Attachment
For TLP bonded layers, a special preform of Ag-Sn-Ag with layer thickness of 20-1020 µm was formed by electroplating. The perform was placed between two polyimide
foils of thickness 250 µm. 5 MPa of pressure along with a temperature of 240 ˚C was
applied under vacuum (2 × 10-4 mbar) to form a TLP bond. Later on, the preform was
annealed at 200 ˚C for 48 hours for TLP bond homogenization. Strips of size
(22 × 3 × 0.045 all in mm) were cut and a 4-point measurement was used to measure the
resistance of the strips.
Figure 5.31: Comparison of electrical
resistivity of TLP bonded and Ag-sintered
layer with bulk silver from [132]
Figure 5.32: Comparison of thermal
conductivity of TLP bonded and Ag-sintered
layer with bulk silver using WF Law
The figure 5.31 shows the electrical conductivities of both Ag-sintered and TLP-bonded
layers along with the comparison with the bulk silver properties [132]. The Ag-sintered
layer exhibited lower electrical resistivity in comparison with Sn-Ag TLP bonded layer.
The thermal conductivities of the Ag-sintered and the TLP-bonded layers were also
calculated from the measured electrical conductivities using the Wiedemann-Franz (WF)
Law [96], with equation 5.5. The Wiedemann-Franz law seems to overestimate the
thermal conductivity by 30 % for Ag-sintered and TLP bonded layers as shown in figure
5.32.
L

 2.44 10-8 W -2

5.5
Where λ, σ and T are thermal conductivity, electrical conductivity and absolute
temperature respectively.
5.6
Thermal Stresses in Die-Attachment
In this section, first the analytical equations for the thermal stresses will be discussed. A
comparison will be presented for the state-of-the-art high-temperature die-attachments
and the die-attachments used in this thesis work i.e. Ag-sintering and TLP bonding.
73
Chapter 5
Characterization Methods and Results
Thermal stress considerations need to be taken into account even in a perfectly executed
die-attach layer which is ideally free of voids. Due to mismatch in “Coefficient of
Thermal Expansion” (CTE) among the chip, die-attach and the substrate, the stress is
introduced in the cooling step of the bonding process. If the CTE of the substrate is
higher than the CTE of the chip, the substrate contracts more while cooling from the
bonding temperature to the room temperature. Consequently, the whole assembly bends
in a convex curvature a shown in figure 5.33. The stress that is generated in the chip may
cause cracking. Cyclic stresses are also produced in the mounted devices while they are
subjected to power cycling, thermal cycling or thermal shocks [10].
Figure 5.33: Bending during the assembly process [88]
5.6.1 Properties of Die-Attach Materials
The die-attach material requirements include high bonding strength, high thermal
conductivity and high electrical conductivity. Another key consideration is that the use
of die-attach material must not cause high stresses on the chip and the substrate.
Additionally, the die-attach material should be resistant to fatigue and creep rupture. The
bonding materials are classified as soft solders, hard solders and electrically conductive
adhesives etc. Depending on the application, each of these materials has its own
advantages and disadvantages. In the following sections, the emphasis is given to their
possible use in power electronics applications.
The most commonly used die-attachment materials in power electronic applications are
the soft solders such as Sn-Pb alloys. Others include various low melting lead-, tin- and
indium-based alloys. These materials generally have acceptable thermal and electrical
conductivities. The soldering temperatures are in the range from 220 ˚C - 350 ˚C. The
chips mounted with soft solders do not experience high stresses because the bonding
layers deform plastically to absorb the strains and hence to reduce stresses. Most of the
strains occur in the die-attach layer as it is much softer than the chip and the substrate.
74
5.6
Thermal Stresses in Die-Attachment
However, the plastic deformation in the solder layer makes it subjected to thermal
fatigue and creep rupture which causes long-term reliability problems [10]. During
thermal cycling, the solder layer degrades due to plastic deformation which is produced
by cyclic stresses. If voids and cracks exist in the solder layer, they will propagate
during cycling and cause an early device failure. Another concern is the presence of
possible intermetallic phases in the solder layer. These phases can be very brittle and if a
thick layer of this phase exists then it may cause cracks in the solder layer. The melting
points of these solders i.e. 250 ˚C restricts their use in high-temperature applications.
Moreover, the ban on lead-based toxic solders also prompts for alternative die-attach
solutions for power electronics [133].
Most commonly used hard solders include gold-tin (Au-Sn), gold-germanium (Au-Ge)
and gold-silicon (Au-Si) eutectic alloys. These solders have generally fair thermal
conductivities and they are free from the thermal fatigue because of high yield strength
which only results in elastic deformation instead of plastic deformation [10]. In
comparison with soft solders, the die-attach layer is not subjected to fatigue or creep
rupture during thermal cycling. Since the yield strength of the solder layer is high i.e.
200 MPa, so the stresses generated in the die-attach layer are not of great concern.
However, the chips mounted with hard solders have considerable amount of residual
stresses due to lack of plastic deformation in the solder layer. The thermal stresses
depend upon the bonding temperatures, which are usually 30 ˚C higher than the melting
points of the solders i.e. 310 ˚C for AuSn solder. Die-cracking can occur because of
stresses developed in the bonding process and also during the power cycling of the
device.
5.6.2 Analytical Considerations
A fundamental solution of the thermal stresses in a chip-substrate assembly was initially
proposed by Suhir [10], [134]–[136] . The analytical model was proposed for a die
mounted on a substrate with a die-attach layer. The schematics of the assembly are
shown in figure 5.34. The subscripts 1, 2 and 3 describe die, die-attach and substrate
respectively. The interfacial stresses between the die-attach and die (or substrate) are
shear stresses τ1 or τ2 and peel stress σ1 or σ2. The solution is based on the following
assumptions.
1. The loads are assumed to be isothermal.
2. In the assembly, each layer bends like a spherically thin plate.
3. The interfaces between the layers are considered to be perfectly bonded.
4. The die-attach material is assumed to be much more compliant compared to die
and substrate.
5. The thickness of the die-attach layer is much smaller in comparison with die and
substrate.
75
Chapter 5
Characterization Methods and Results
Figure 5.34: Schematics of a trimaterial
assembly structure [136]
Figure 5.35: Shear stresses τ and peel stresses
σ after ∆T [136]
Based on assumption 4 and 5, the coefficient of thermal expansion of die-attach material
α2 is insensitive to the stresses and therefore it can be excluded from formulations. As
thickness of die-attach layer is small compared to other two layers, the shear stresses and
peel stresses at die-attach/chip and die-attach/substrate interfaces in figure 5.35 are
assumed to be approximately equal, which are given by equations 5.6 and 5.7.
1  2  o
5.6
1  2  o
5.7
Where τo and σo are die-attach shear and peel stresses, respectively. The thermal load
∆T, and difference in coefficient of thermal expansion ∆α are expressed in equations 5.8
and 5.9.
T  Tb  Tg
5.8
  3  1
5.9
Where Tb and Tg are the bonding and initial given temperatures, whereas, α3 and α1 are
the CTEs of substrate and die respectively.
5.6.3 Die-Attach Shear Stress
According to Suhir [10], [135], the die-attach shear stresses can be computed
analytically from the center to the edge of the die-attach with the help of equation 5.10.
76
5.6
o (x)  k
Thermal Stresses in Die-Attachment
T
sinh kx
 cosh kl
5.10
Where x is edge length, k is the longitudinal compliance, which is described by equation
5.11.
k


5.11
Where λ is the axial compliance and κ is the interfacial compliance. Both are determined
by equations 5.12 and 5.13.
1  12 1  32
t



E1t1
E 2 t 3 4D

t1
2t t
 2 3
3G1 3G 2 3G 3
5.12
5.13
Where E is the elastic modulus, G is the shear modulus, ν is the Poisson’s ratio, t is the
total thickness, D is the total flexure rigidity and i = 1, 2, 3. These are described in
equations 5.14 to 5.17 respectively.
Ei
2(1  i )
5.14
Ei t i3
Di 
12(1  i )
5.15
t  t1  t 2  t 3
5.16
D  D1  D2  D3
5.17
Gi 
5.6.4 Die Stresses
The die stresses in the longitudinal directions can be calculated as proposed by Suhir
[10], [136]. The equation 5.18 and 5.19 describes the maximum normal stresses on the
top and the bottom of the die respectively.
top (x) 
tD1   cosh  kx  
T 

1  3
 1 
t 1 
t1D  
cosh  kl  
5.18
77
Chapter 5
Characterization Methods and Results
bot (x) 
tD1   cosh  kx  
T 

1  3
 1 
t 1 
t1D  
cosh  kl  
5.19
5.6.5 Warpage of Assembly
The warpage of the assembly occurs due to mismatch of CTEs of three layers in the
assembly, when they are cooled down from the bonding temperature to the room
temperature. The warpage w(x) from the center of the assembly to the edge is can be
obtained using the following equation 5.20 [136].
w(x) 
tT  x 2 cosh  kx   1 
 

2D  2 k 2 cosh  kl  
5.20
The bending radius of the curvature is inversely proportional to the second derivative of
warpage of the assembly and can be obtained by equation 5.21 [136].
(x) 
1
tT  cosh kx 

1
''
w(x)
2D  cosh kl 
5.21
5.6.6 Comparison of Analytical Solution
The aforementioned analytical equations were used to analyze thermal stresses in the
assembly for various die-attachment methods. In this work, the focus is given to
performance comparison of Ag-sintering and TLP bonding. Additionally, a comparison
is made with the current state-of-the-art high-temperature stable die-attachments, which
are Au80Sn20 and Au88Ge12 eutectic solders. The table 5.3 gives the process
temperatures of various die-attach methods along with the relevant materials properties
for chip, die-attach and the substrates. During our investigations, AlN DCB substrate
was used, with consists of a ceramic layer sandwiched between two copper layers.
Therefore, the elastic modulus and CTE of the three layered composite were
approximated according to equations 5.22 and 5.23 [137].
s 
2Cu ECu t Cu  AlN E AlN t AlN
2ECu t Cu  E AlN t AlN
5.22
2ECu t Cu  E AlN t AlN
2t Cu  t AlN
5.23
Es 
78
5.6
Thermal Stresses in Die-Attachment
Where, α E and t are CTE, Young’s modulus and thickness. The theoretically
approximated CTE and E-Modulus of AlN DCB according to equations 5.22 and 5.23
are 7.6 ppm/K and 220 GPa respectively.
Table 5.3: Materials properties, process temperatures and thicknesses of assembly. *own
measurement values
TProcess (oC)
E (GPa)
ν
α (ppm/K)
t (mm)
Si
/
162
0.25
2.6
0.35
AlN
/
310
0.24
4.7
0.63
Cu
/
120
0.34
17
0.30
Ag-sintered
layer
230
45*
0.3
20
SnAg-TLP
bond
240
40*
0.28
18*
AuSn
280
69
0.4
16.2
AuGe
356
73
0.3
13
Assembly
Chip
Substrate
Die-attach
Figure 5.36: Shear stresses in die-attach layer
0.02
Figure 5.37: Normal stresses in chip top
surface
The Suhir’s analytical equations were used to calculate thermal stresses for various dieattachment technologies. A square Si chip of size 9 mm × 9 mm mounted on AlN DCB
substrate was used for the analytical calculations. In this work, the die-attachment was
aimed for high-temperature and high-power applications. Consequently, Ag-sintered and
Sn-Ag based TLP bonded assemblies were compared to currently used hard Au-based
79
Chapter 5
Characterization Methods and Results
solders. It can be seen in figure 5.36 that high process temperatures in AuSn and AuGe
soldering resulted in high shear stresses in the die-attach as compared with sintered and
TLP bonded chips. In general, the shear stresses are negligible in the center of the chip.
Whereas, on the edges the shear stress is at its maximum value. However, the
compliance of the die-attach layer and size of the assembly also plays a significant role
in determining the shear strength.
Figure 5.38: Warpage of the assembly
In can be observed in figure 5.37 that normal stresses in the chip top surface are higher
than the sintered and the TLP bonded dies. In general, the die-stresses are maximum in
the center of the die and they fall to zero at the edges. These stresses are independent of
the die size. Moreover, the warpage in the Au-based assemblies are higher than the Agsintered and TLP bonded assemblies as shown in figure 5.38. It can be stated that the
possible bending stresses are higher for Au-based hard solders. Based on the analytical
calculations, it can be said that low processing temperatures in Ag-sintering and TLP
bonding result in low thermal stresses in the assemblies after cooling down to room
temperature i.e. 25 ºC. The results in figure 5.36 to figure 5.38 are valid for materials
properties and die-attachment process temperatures described in table 5.3.
5.6.7 Experimental Determination of Bending Stresses
In order to estimate the bending stresses developed during the assembly and hightemperature operation, out of plane warpage of the chips bonded with Ag-sintering and
TLP bonding were measured using digital image correlation (DIC) method [93].
The bending in the assembly occurs mainly due to CTE mismatch between the chip and
substrate. If the CTE of substrate is greater than the CTE of the chip, the substrate
contracts more than the chip while cooling the assembly from bonding temperature to
room temperature. This causes the assembly to bend in a convex curvature. Warping of
the chip surface is considered to be proportional to the bending stress in an assembly,
which is given by the following equation 5.24 [10].
80
5.6
σb =
Echip .t
2R
Thermal Stresses in Die-Attachment
5.24
Where σb is bending stress, Echip is the elastic modulus of the chip, R is the bending
radius calculated from measured warpage and t is the thickness of the chip.
Figure 5.39: DIC measurement setup [138]
Figure 5.40: IXYS Si RF transistor Sn-Ag
TLP bonded on AlN DCB [93]
Two silicon chips with the size of 7 mm × 9 mm were mounted on AlN DCB with Agsintering and SnAg-TLP bonding as shown in figure 5.40. The thickness of the dieattach material was 30 µm. The assembly was later on placed inside an evacuated
chamber and heated from 30 ˚C to 400 ˚C. During heating, the warpage on the chip
surface along the diagonal direction was measured with DIC setup as shown in figure
5.39. The out of plane deformation in the chip surface, for both Ag-sintered and TLP
bonded assemblies, at various temperatures is depicted in figure 5.41 to figure 5.44.
Figure 5.41: Warping of z-profile in Agsintered Si chip on AlN DCB at 30 ºC
Figure 5.42: Warping of z-profile in Agsintered Si chip on AlN DCB at 400 ºC
81
Chapter 5
Characterization Methods and Results
Figure 5.43: Warping of z-profile in TLP
bonded Si chip on AlN DCB at 30 ºC
Figure 5.44: Warping of z-profile in TLP
bonded Si chip on AlN DCB at 30 ºC
Figure 5.45: Out of plane warpage in Agsintered Si chip on AlN DCB using DIC.
Figure 5.46: Out of plane warpage in TLP
bonded Si chip on AlN DCB using DIC.
Figure 5.47: Bending stresses in Ag-sintered and TLP bonded Si chips on AlN DCB
82
5.6
Thermal Stresses in Die-Attachment
Increasing the temperature of the assembly from 30 ˚C to 400 ˚C, the warpage in Agsintered chip changed from convex to concave, with a stress free temperature nearly at
240 ˚C, as shown in figure 5.45. While, in TLP bonded samples the curvature changed
from more convex to less convex shape between 30 ˚C and 400 ˚C, as shown in figure
5.46. It can be seen in figure 5.47 that bending stresses, which are calculated from the
warpage, inside the Ag-sintered chip are lower than the Ag-Sn TLP bonded chip. This
shows that Ag-sintered die-attach layer is more ductile than the TLP bonded layer. In
general the stress levels were relatively low. Based on material properties in table 5.3, a
comparison of warpage in Ag-sintered and TLP bonded chips was made between the
DIC measurements, FE simulations using Ansys and analytical solution using equation
5.20. The outcomes from all three solutions are in close agreement for both Ag-sintered
and TLP bonded Si chips on AlN DCB substrate.
Figure 5.48: Comparison of warpage in Agsintered Si chip on AlN DCB at 30 ºC
Figure 5.49: Comparison of warpage in
TLP bonded Si chip on AlN DCB at 30 ºC
The finite element simulations using ANSYS were performed for warpage measurement
in the chip surface after the die-attachment process at room temperature. The assembly
consisted of a Si chip mounted on an AlN DCB with the same dimensions as used during
the DIC measurements. The material properties for individual assembly layers were used
as described in table 5.3. The static structural analysis was performed. The complete
assembly was subjected to a temperature load of 30 ºC while the reference temperature
was selected to be 240 ºC for Sn-Ag TLP bonding and 230 ºC for Ag-sintering, which
are same as the bonding temperatures. The simulation was aimed at analyzing the
thermal stresses and strains developed in the assembly while cooling from the bonding
temperature to the room temperature. The out-of-plane deformation, which in this case is
the directional deformation in z-direction as shown in figure 5.50, was measured on the
chip surface along the diagonal direction. The simulation results for both Ag-sintered
and Sn-Ag TLP bonded Si chips on AlN DCB are in closed agreement to the analytical
and measured values in figure 5.48 and figure 5.49.
83
Chapter 5
Characterization Methods and Results
Figure 5.50: FEM simulation, z-axis deformation in Sn-Ag TLP bonded assembly at 30 ºC
5.7
Mechanical Characterization
The mechanical characterization of TLP bonded foils was made using a Zwick Z010
tensile testing machine in combination with the Digital Image Correlation (DIC) system
for strain measurement as shown in figure 5.52. The samples consisted of Ag-(Sn/In)-Ag
TLP-interlayer foils, which were placed between two polyimide sheets and later on TLP
bonded in the substrate bonder under standard process conditions, as described in table
5.4. The foils were designed to keep the wt. % of Ag above 80 % in the final TLP
bonded joint after the annealing process.
Table 5.4: Details of foils and TLP bonding conditions
Foils
Ag-Sn-Ag
Ag-In-Ag
Thickness
20 µm – 10 µm – 20 µm
20 µm – 10 µm – 20 µm
Process conditions
84
Bonding temperature
240 ºC
210 ºC
Bonding pressure
5 MPa
8 MPa
Bonding time
30 min
15 min
Chamber pressure
4 × 10-4 mbar
4 × 10-4 mbar
Annealing conditions
48 h at 200 ºC
48 h at 200 ºC
5.7
Mechanical Characterization
The TLP bonded foils were then cut into bone shape samples using the laser cutting. The
sample details are depicted in figure 5.51. After TLP bonding process, the average
thickness of the samples was around 46 µm, due to squeeze out of Sn/In due to bonding
pressure.
Figure 5.51: Details of TLP bond material sample for mechanical characterization
For mechanical characterization of Ag-sintered layers, the strips of size 4 mm ×20 mm
were first prepared by screen printing Ag-sinter paste (LTS 275-3P2) on a silicon wafer
with silicon oxide on top. Thereafter, the strips were dried and subsequently sintered at
20 MPa and 230 ºC for 5 minutes. The thickness of the sintered samples after sintering
was nearly 60 µm. The measurements were made at the room temperature i.e. 25 ºC for
both TLP bonded and Ag-sintered samples with a sample set of 5. The sample under test
was pulled with a pull speed to 300 µm/min with the help of a load cell that could apply
forces up to 2.5 kN. The pull force range was selected to be between 1 N and 30 N in
order to keep the sample in the elastic range. During tests, the pull force was kept
constant for 5 seconds after an interval of 9 N. During this interval, the corresponding
uniaxial strain i.e. εy was measured using the DIC system. The stress-strain curves for
both TLP bonded foils and Ag-sintered samples measured with tensile testing machine
are shown in figure 5.54 and figure 5.55 respectively.
Figure 5.52: Setup along with the DIC system
to measure the strain.
Figure 5.53: Sn-Ag TLP boned foil in
tensile test.
85
Chapter 5
Characterization Methods and Results
Figure 5.54: Stress-strain curve for TLP
bonded foils at 30 ºC
Figure 5.55: Stress-strain curve for Agsintered strips at 30 ºC
The more accurate uniaxial in-plane strain measurements using DIC system were also
performed along with the strain measurements using tensile testing machine. The
calculated elastic modulus of TLP bonded layers is given in table 5.5.
Table 5.5: E-modulus measurement
5.8
TLP boned foils
E-Modulus using Zwick
machine
E-Modulus using DIC
method
Ag-sintered
40 GPa
/
Ag-Sn-Ag foil
45 GPa
60 GPa
Ag-In-Ag foil
30 GPa
40 GPa
Micrographs of TLP and Ag-Sintered Joints
Figure 5.56: SiC Schottky diodes Ag-sintered
86
Figure 5.57: IXYS Si RF transistor Sn-Ag
5.9
AlX Material Characterization
on AlN DCB
TLP bonded on AlN DCB [93]
Figure 5.58: Micrograph of SiC Schottky
diodes Ag-sintered on AlN DCB
Figure 5.59: Micrograph of IXYS Si RF
transistor Sn-Ag TLP bonded on AlN DCB
5.9
AlX Material Characterization
5.9.1 Mechanical Characterization
The mechanical characterization of the bonding wire was performed using the Zwick
Z010 tensile testing machine. A load cell of 2.5 kN was used for pulling. Multiple wire
samples of length (100 mm) and diameter (300 µm) were pulled at a pull-speed of
2 mm/min. The measurements were performed in a chamber, which was heated from
25 ºC to 160 ºC. The measured uniaxial strains and measured E-Modulus are shown in
figure 5.60 and figure 5.61 respectively.
Figure 5.60: Uniaxial strain measurement at
various temperatures
Figure 5.61: Measured E-Modulus at various
temperatures
87
Chapter 5
Characterization Methods and Results
The values of E-Modulus provided by Heraeus at room temperature was around 14 GPa,
which differs from the own measurements by factor of 2. Both values do not match the
theoretical data value i.e. 70 GPa for the pure aluminum metal.
5.9.2 Electrical Characterization
The AlX wire was also tested for its electrical resistivity. The wire was rolled onto a
ceramic block and placed inside the temperature oven. The length of the wire was
100 mm and nominal value of wire diameter was 300 µm, which was determined using a
micrometer screw gauge. The temperature inside the oven is monitored with a
thermocouple. The resistance of the wire was monitored through an Agilent 34401A
digital multimeter using 4-point measurement method. The measured electrical
resistivity at different temperatures is given in figure 5.62.
Figure 5.62: Electrical resistivity of AlX at various temperatures
5.10 Pull-Strengths of Wire bonds
The stability of wire bonds was analyzed using the bond pull tests. The tests were
performed using a Dage-4000 bond tester for the thin Au and Pd wire bonds, which were
made between chips and substrates. The metallization on both chips and substrates was
gold. The AlX wire bonds were made on different substrates such as Al, Ag and Cu etc.
The pull tests for these thick wire bonds were performed using Dage-Microtester22.
Later on, the wire bonds were subjected to passive temperature cycling from -40 to
+150 ºC. Both Au and Pd yielded pull strengths of above 300 mN and passed the
standard MIL-STD-883G 2011.7, which requires the minimum bond pull force limit to
be above 50 mN. The thick AlX wire bonds were bonded on various surfaces such as
Au, Al, Cu and Ag. The samples were later on stored in an oven at 300 ºC for 400 h. The
environment inside the oven was atmospheric air. The pull strength on Al, Al and Au
88
5.11 Summary
surfaces decreased slightly (3 – 8 %.) after the high-storage test. While for Cu surface,
the bonding strength decrease by 25 % mainly due to oxidation of copper.
Figure 5.63: Pull-strength of AlX wire bonds
after high-temperature storage at 300 ºC
Figure 5.64: Pull-strength of Au ad Pd wire
bonds after passive TS of ∆T = 190 K
5.11 Summary
In this thesis work, the die-attachments i.e. Ag-sintering and foil-based TLP bonding are
aimed at high-temperature and high-power applications. This chapter has been dedicated
to the various die-attachment characterization techniques.
Both Ag-sintered and Sn-Ag TLP bonded Si and SiC chips, the shear strength after
passive temperature cycling of ∆T = 190K was above 30 MPa. Both die-attachments
were also subjected to passive temperature cycling of ∆T = 470K. However, the DCB
substrates were destroyed before the die-attachments. The shear strength of the chips, on
the delaminated DCB copper after 20 cycles of ∆T = 470K, was about 25 MPa for both
die-attachments.
The DSC measurements were performed to measure the melting points of the resultant
binary phase alloys after the TLP bonding process. For unannealed In-Ag binary joints,
small traces of Ag3In and Ag3.2In96.8 phases were present. But these phases
disappeared after the annealing process. Consequently, it can be said that the melting
temperature of the binary phases in the joint are beyond 500 ºC. Likewise, the material
phases such as Ag3Sn and of Ag3.5Sn96.85 were present in the unannealed Sn-Ag joint
after TLP bonding process. A small melting peak remained at 480 ºC in the annealed
joint, which indicates the presence of small traces of Ag3Sn phase. It can be stated that
Sn-TLP joints can survive temperature up to 480 ºC.
The EDX analysis of the TLP bonded joints was performed to analyze the uniformity of
the joint before and after annealing process. The unannealed Sn-Ag TLP bonded joint
based on 3-layer sandwich foil indicated the presence of Ag3Sn, ζ and Ag phases. But
89
Chapter 5
Characterization Methods and Results
the joint consisted mostly of the ζ- and Ag-phases after the annealing process. The 9layer Sn-Ag foil structure showed the ζ- and Ag-phases without application of post
annealing step. In a similar fashion, the unannealed Ag-In joint showed the presence of
Ag3In, Ag2In and Ag phases. While, only the Ag and ζ phases were present after the
annealing process. Due to cracks and non-uniformities in 9-layer Ag-In foil, no further
investigations were performed. The EDX analysis and DSC measurements comply with
each other.
The thermal resistance of complete Ag-sintered and TLP bonded assemblies was
measured. The thermal resistance of the Ag-sintered assemblies was found to a factor of
3 – 4 % lower than Sn-Ag bonded assemblies. The literatures describes the thermal
conductivity of Ag-sintered layers from 100 – 200 W/mK. If all the layers in the
assembly are identical, then increase of the thermal resistance in TLP bonded assemblies
can be attributed to TLP bonded layers. The thermal conductivity of TLP bonded layer
relative to Ag-sintered layer (200 W/mK) was calculated to be 67 W/mK.
The electrical conductivity of both Ag-sintered and Sn-Ag TLP layer was measured in
the temperature range of 25 – 200 ºC and extrapolated to 500 ºC. Based on these values,
the thermal conductivity of both die-attachments was calculated according to
Wiedemann-Franz Law. The value calculated from Wiedemann-Franz Law seem to
overestimate the experimentally determined value of thermal conductivity by a factor of
30 %.
An important aspect of the packaging is the estimation of thermal and thermomechanical
stresses in the assembly, which originate during the die-attachment process and also due
to temperature cycling during operation. The analytical consideration of thermal stresses
was made for both Ag-sintered and Sn-Ag TLP bonded assemblies. A comparison with
the current state-of-the-art high-temperature stable die-attach solutions such as AuSn and
AuGe eutectic solders was made. The die-attachment shear stresses, die-normal stresses
and out-of-plane warpage in gold-based solders are higher as compared to Ag-sintering
and TLP bonding. The warpage in the chip surface after the assembly process and also at
various temperatures i.e. 30 – 400 ºC was experimentally determined through the DIC
method. In general the bending stresses in both Ag-sintered and TLP bonded chips on
AlN DCB substrates were low, which are calculated from out-of-plane warpage in the
chip surface. The values from analytical, experimental and FE simulations comply with
each other.
The mechanical characterization of the Ag-sintered and TLP bonded layers was also
performed. The uniaxial stress-strain measurements were performed at the room
temperature. Sn-Ag and In-Ag TLP bonded layers both exhibited plasticity. The DIC
method was used in combination with the tensile testing to measure the strains in the
samples. However, further investigation of the possible viscoplastic or creep behavior of
both Ag-sintered and TLP bonded layers has yet not been investigated in this work.
The characterization of the both Ag-sintered and TLP bonded layers showed that both
materials can survive temperature beyond 480 ºC. Both of them exhibit good electrical
90
5.11 Summary
and thermal properties. The micrographs indicate that both die-attachments are uniform
and void free. Moreover, they also fill out the surface irregularities of the substrates.
The mechanical and electrical characterization of the novel AlX wire, with higher
temperature stability, was also presented. The electrical characteristics are similar to
pure aluminum. While, the material was found to be more ductile than pure aluminum.
The pull strengths of the AlX wire bonds on Al, Au and Ag retained after hightemperature storage at 300 ºC. Both gold and palladium wires exhibited high pull
strengths after passive temperature cycling of ∆T = 190 K. The palladium wire has been
proven to be high-temperature stable up to 500 ºC in sensor applications [15]. But its
temperature dependent electrical resistivity is higher than gold, which hinders its use for
high-current applications.
91
6
Assembly and Packaging of SiC
Schottky Diodes
This chapter describes the assembly technologies for silicon carbide (SiC) diodes. The
Ag-sintering and transient liquid phase (TLP) bonding were tested as die-attachment
techniques. On the other hand, thick (300 µm) wire bonding based on a novel aluminum
alloy AlX from Heraeus GmbH was used for electrical interconnection. An electrical as
well as a thermal characterization of the assembled SiC devices on AlN DCB substrates
was performed. The diode assemblies were characterized with respect to forward IVcurves and maximum current capabilities. Moreover, the thermal resistance of the
assembled diodes with both die-attachments was measured. The passive temperature
cycling from -40 to +150 ºC and active power cycling with various junction temperature
differences ∆Tj were performed. An estimation of initial reliability of the SiC assemblies
is presented.
6.1
Motivation
With their superior electrical and physical properties, SiC-based semiconductors are
potential candidates to replace Si-based semiconductors. SiC-based electronic devices
have been demonstrated to operate at temperatures up to 300 ˚C [4]. The critical electric
field strength of SiC (3 MVcm-1) is ten times higher than for Si, which allows for a
thinner conduction region. This leads to a very low specific conduction resistance. The
high thermal conductivity (370 Wm-1K-1) of SiC allows higher power density with a
higher power-per-unit area to be handled as compared to Si (150 Wm-1K-1). The
saturated electron velocity of SiC (2 × 107 cms-1) is twice as compared to Si. The SiC
devices exhibit low reverse recovery currents which allows faster operating speed [6]. In
order to take advantage of these excellent electrical characteristics of SiC-devices, an
assembly process is needed, which enables device operation at higher temperatures and
minimizes thermal and thermo-mechanical degradation of the devices.
6.2
SiC Schottky Diodes
2nd generation SiC Schottky diodes (IDC08S60CE), which are also commercially
available, are used in this thesis work. These SiC diodes have a merged PN/Schottky
design as shown in figure 6.1, which uses a Schottky interface for nominal current
92
6.2
SiC Schottky Diodes
operation and a PN junction for high current operation. The embedded low ohmic pdoped islands have two principal advantages. First, they extend the peak current
handling capability of the diode by generating a bipolar current, which prevents the
diode from current overload thermal runaway. Second, the low resistivity and design of
p-islands in the merged Schottky structure guarantees the onset of avalanche before the
electric field at Schottky interface reaches a destructive value. A detailed description of
merged PN/Schottky design and SiC Schottky device characteristic has been given by
Bjoerk at el. [85].
Figure 6.1: 2nd Generation SiC Schottky diode
with merged p-doped islands by Bjoerk at el.
[85], [86]
Figure 6.2: SiC Schottky diodes attached to
an AlN-DCB using Ag-sintering and AlXwire bonding
The SiC Schottky diode (IDC08S60CE) has a chip area of 1.66 mm × 1.52 mm and a
chip thickness of 355 µm. The diodes are rated for a continuous forward current of 8 A
and a reverse blocking voltage of 600 V. The forward voltage drop ranges from 1.5 to
1.7 V, whereas, the leakage current varies between 1 and 100 µA. The rated operational
junction temperature of these devices is 175 ºC. The metallurgical aspects of the chip are
summarized in table 6.1.
Table 6.1: Metallurgy of SiC Schottky diodes
SiC Schottky Diodes
Name
Source
IDC08S60CE
Infineon
Metallization
Thickness
Pad
AlSiCu
3200 nm
Backside
Ni-Ag
n.a
93
Chapter 6
6.3
Assembly and Packaging of SiC Schottky Diodes
Assembly Process for SiC Schottky Diodes
The SiC Schottky diodes were mounted on AlN DCBs using Ag-sintering and SnAg
based TLP bonding. The average thicknesses of the Ag-sintered and the SnAg TLP
bonded layers were 15 µm and 25 µm respectively. For electrical interconnection, AlX
thick wire with diameter of 300 µm was used. A maximum of 2 wire bonds was used.
6.4
Electrical Characterization
A detailed analysis of the electrical characteristics of SiC Schottky diodes was
performed after the assembly process. The thermal dissipation behavior of the assembled
diodes is expected to be improved as compared with on-wafer bare diodes.
Consequently, self-heating effects of the devices are reduced . This leads to the fact that
the on-state resistance reduces significantly. Moreover, maximum on-state currents are
increased which results in higher power-per-unit area. The electrical characteristics such
as forward IV-curves, maximum forward currents and reverse blocking voltage were
measured for the assembled SiC diodes on AlN DCBs.
6.4.1 Forward Characteristics
Both pulse mode- and continuous mode- forward characteristics (IV-curves) were
measured during the experiments. For pulse-mode measurements the forward current If
with a pulse width of tpls = 0.1 – 1 ms was applied. A 4-point measurement setup was
used to measure the on-state resistance Rds,on with high resolution and to eliminate the
resistive contribution of cables and needles. The schematic of the test setup is shown in
figure 6.3. For continuous mode, the characterizations were also made at various
temperatures in a range from 20 – 160 ºC
Figure 6.3: Equivalent circuit diagram of measurement setup for characterization of diodes
94
6.4
Figure 6.4: Comparison of pulsed and
continuous IV-characteristics for a SiC diode
Ag-sintered on AlN-DCB
Electrical Characterization
Figure 6.5: Comparison of continuous IVcharacteristics for an Ag-sintered and SnAg
TLP bonded SiC diode on AlN-DCB
During the pulsed (0.1 – 1 ms) IV-measurements of SiC Schottky diodes, the pulsed
forward currents up to 100 A were achieved without any device failure. The advantage
of merged PN/Schottky structures is evident in both pulsed (tpls = 1 ms) and continuous
IV-measurements. In figure 6.4, an increase of forward current above 50 A during
pulsed (tpls = 1 ms) IV-measurements and an increase of forward current above 20 A
during continuous IV-measurements is attributed to the bipolar conduction of current
due to the merged structure design. Thus a thermal runaway of the devices is prevented
during high surge current conditions [85]. The continuous IV-measurements of Agsintered and SnAg TLP bonded SiC diodes on AlN DCB shows that the on-state
resistance of Ag-sintered assembly is slightly lower than the SnAg TLP boned assembly.
However, both are in the same range as shown in table 6.2. The electrical tests were
performed on 25 devices and they exhibited the similar characteristics.
Table 6.2: On-state resistance Ron for an Ag-sintered and SnAg TLP bonded SiC diode on AlN
DCB in linear region (1.4 – 2.2 V) during continuous IV-measurement
Ag-sintered SiC assembly
Forward voltage, Vd (V)
Forward current, Id (A)
On-state resistance, Ron (mΩ)
1.4
5.6
250
1.5
7.7
194
1.8
11.3
159
1.9
12.6
150
2.2
15.6
141
95
Chapter 6
Assembly and Packaging of SiC Schottky Diodes
SnAg TLP bonded SiC assembly
Forward voltage, Vd (V)
Forward current, Id (A)
On-state resistance, Ron (mΩ)
1.4
4.5
311
1.6
7.5
213
1.8
10.4
173
2.0
12.8
156
2.1
14.3
146
Both Ag-sintered and TLP bonded assemblies were fixed onto a hot plate using thermal
grease. While increasing the temperature of the hot plate from 20 – 160 ºC, an increase
of on-state resistance was observed which shows a decrease in electron mobility at
higher temperatures as shown in figure 6.6 and figure 6.7 [13].
Figure 6.6: Continuous IV-characteristics for
an Ag-sintered SiC diode on AlN-DCB at
various chuck temperatures
Figure 6.7: On-state resistance in linear
region (1.3 – 1.8 V) in figure 6.8 for an Agsintered SiC diode on AlN-DCB, P = Vd × Id
6.4.2 Maximum Continuous Forward Current
The Ag-sintered and SnAg TLP-bonded SiC diodes mounted on AlN DCB, with two
AlX wire bonds (ϕ = 300 µm) per single diode, were tested for maximum continuous
forward current. A maximum continuous forward current ranging from 34 – 36 A was
found for both TLP bonded and Ag-sintered assemblies respectively. The maximum
power-per-unit-area up to 72 W/mm2 could be achieved without any damage to the die
and die-attachment. At this condition, the wire bonded started to melt (Tmelt = 660 ºC)
and SiC diodes began to emit blue light [13]. An Ag-sintered SiC diode on AlN-DCB
during high power operation is depicted in figure 6.8.
96
6.5
Thermal Resistance of SiC Assemblies
Figure 6.8: Ag-sintered SiC diode on AlN-DCB during operation at high power dissipation of
60 W/mm2, Vd = 4.8 V, Id = 32 A
6.4.3 Breakdown Characteristics
No effect on breakdown characteristics of diodes was observed for both Ag-sintered and
TLP bonded SiC diode assemblies. For both cases, breakdown voltages were measured
in the range from 740 – 760 V along with avalanche currents ranging from 1 – 5 mA.
The breakdown characteristics of an Ag-sintered SiC diode are shown in figure 6.9.
Figure 6.9: Breakdown characteristics for an Ag-sintered SiC diode on AlN-DCB
6.5
Thermal Resistance of SiC Assemblies
In order to investigate the thermal dissipation behavior, the thermal resistance of the
completed SiC diode assemblies was measured. SiC diodes were mounted on to the AlN
DCB using the Ag-sintering as well as the SnAg-based TLP bonding. The electrical
interconnection was made with two AlX wire bonds per diode. The surface temperature
97
Chapter 6
Assembly and Packaging of SiC Schottky Diodes
of the diode was measured using an infrared camera, QFI MWIR-512 from
InfrascopeTM. The complete SiC assembly was mounted onto a chuck with a constant
temperature of 40 °C. The details of the various layer thicknesses in the assembly are
summarized in table 6.3. The DCB was held onto the chuck with a pressure contact. The
thermal resistance of the assembly was measured using equation 6.1.
R th 
T Ttop(Chip surface) - Tbottom(DCB bottom)

P
Vf .If
6.1
Here, Ttop is the diode’s surface temperature, Tbottom is the fixed temperature at the
bottom of the DCB, Vf is the forward voltage and If is the forward current.
Table 6.3: Materials and thickness of assembly layers
Assembly
Material
Thickness (µm)
Chip
SiC
355
Ag-sintered layer
20
Sn-Ag TLP bonded layer
28
Cu
300
AlN
633
Cu
300
Die-attachment
DCB substrate
Figure 6.10: Thermographic image of
SiC diode at 68 W of power
Figure 6.11: Temperature distribution along the line
on the chip surface with Tavg = 220 ºC
The thermographic image is shown in figure 6.10. The measured thermal resistance for
both Ag-sintered and SnAg-TLP bonded assemblies was in the same range as shown in
98
6.5
Thermal Resistance of SiC Assemblies
table 6.4. For both tests the diodes and the substrates were identical, while only
difference was the die-attach layer. The thermal conductivity of the Ag-sintered layer
λsintered is reported from 100 to 200 W/mK [31]. Relative to this value the thermal
resistance of the SnAg-TLP bonded layer was calculated in the same manner as in
section 5.4.
Table 6.4: Comparison of Rth of assembled SiC diodes. *: Literature **: Calculated
Ag-sintered
TLP bonded
Rth (K/W)
2.32
2.43
λth (W/mK)
100*
54.3**
6.5.1 Junction Temperature Characterization
For low forward currents i.e. from micro-amperes to few tens of milli-amperes, the
forward voltage of the diode decreases linearly with increasing temperature [13], [139].
In order to characterize the junction temperature of SiC diode, the diode assembly was
placed in an oven and low forward biasing currents ranging from 1 µA to 25 mA were
applied at different temperatures. Consequently, a decrease in forward voltage was
observed with increasing temperature as shown in figure 6.12. The low currents were
applied to avoid the self-heating effects [13]. The measurements were performed to
determine the junction temperatures during power cycling.
Figure 6.12: SiC diode forward voltage versus temperature
99
Chapter 6
6.6
Assembly and Packaging of SiC Schottky Diodes
Active Power Cycling
The circuit schematic in figure 6.13 was used during the power cycling of SiC diodes. A
DC precision current source 6220 from Keithley with a low current value of
ISense = 10 mA was attached to the diode, which caused a constant forward voltage drop
during the measurement. The objective was to measure the temperature-dependent
forward voltage characteristics of the diode. A second voltage source PS 2042-20B from
Elektro-Automatik GmbH, was attached in parallel to the diode which could be switched
for a specified period of time i.e. 1-10s. The purpose was to heat up the diode up to a
specific junction temperature. During the on-state and the off-state, the voltage across
the diode was measured using a digital multimeter Agilent 34401A. When the voltage
source is switched off, the current from the DC current source still flows through the
diode, causing a certain forward voltage drop. The heating of the diode causes this
forward voltage drop to decrease. This voltage was measured using a microcontroller
ATMEGA328 from Atmel, which allowed voltage measurements within a few
microseconds. The setup is controlled using a LabVIEW program developed for this
work.
Figure 6.13: Circuit diagram for the power cycling setup
Power cycling tests were performed on SiC diode assemblies mounted with both Agsintered and SnAg TLP bonding. The power was constantly switched on and off for the
duration of 2.5 sec and 3 sec respectively. The diode’s rated current was 8 A. For test
purposes, the diodes were heated with 125 % to 240 % of the rated current to set the
junction temperature swing ∆Tj from 80 K to 140 K. Stress conditions such as ton and
Iload were kept constant during the tests. The failure criterion was set to be an increase of
the forward voltage Vf by 5 to 10 % of the initial value during the test duration as shown
in figure 6.14.
During power cycling, for ∆Tj above 100 K, module failure occurred due to wire bonds
lift-off before any considerable damage of the die-attach layer as shown in figure 6.15.
This was because of higher CTE mismatch between SiC (4.2 ppm/K) and
AlX (22 ppm/K). In this case, the modules were re-bonded and subjected to further
power cycles until a damage to the die-attach layer was observed, which is indicated by
an increase in forward voltage by 10 %. The Ag-sintered and TLP bonded SiC diodes
showed high power cycling capability as shown in figure 6.16. Ag-sintered samples
100
6.6
Active Power Cycling
survived a factor of 1.5 times longer than the TLP bonded samples. A performance
comparison of power cycling capability was made with other die-attachments. Both Agsintered and TLP bonded samples survived a factor of 6 times higher than adhesive
bonded SiC diodes and a factor of 4 times the higher than Ag3.5Sn solder [140] until the
die-attach failure occurred. The criteria of failure was 10 % increase of diode forward
voltage.
Figure 6.14: Forward voltage drop of a TLP
bonded SiC assembly during power cycling
with ∆T = 70 K
Figure 6.15: Micrograph of a wire bond liftoff during power cycling
Figure 6.16: Power cycling reliability of various die-attachments with failure criteria of Vf by
10 %. Own results along with Herold et al.[140]
It was found out that cracks started in the die-attach layer at the edge of the devices and
propagated towards the center. The crack initiation and propagations occurs due to the
CTE mismatch between the bonded materials during cyclic loading and unloading [133].
101
Chapter 6
Assembly and Packaging of SiC Schottky Diodes
Figure 6.17: Micrograph of an Sn-Ag TLP
bonded SiC diode on AlN DCB after 50000
cycles at ∆T = 100 K
Figure 6.18: Micrograph of an Ag-sintered
bonded SiC diode on AlN DCB after 60000
cycles at ∆T = 100 K
6.6.1 Crack Propagation Rates
The crack rates of the die-attachments i.e. Ag-sintered and Sn-Ag TLP bonded layers
were experimentally determined by making the cross sections of the assembly after the
die-attachment failure. The criterion for the die-attach failure was 10% increase of
diode’s forward voltage. The average thicknesses of the TLP bonded layer and Agsintered layers were 25 µm and 15 µm respectively. The cracks appeared in the chip/dieattach and substrate/die-attach interfaces. The crack rates were determined by dividing
the total crack length by the total number of power cycles to failure. The crack rates
were determined for various junction temperature differences ∆Tj, as shown in figure
6.19.
Figure 6.19: Experimental determination of crack rates in Ag-sintered and SnAg TLP bonded
die-attach layers at various ∆Tj on AlN DCB
102
6.7
6.7
Summary
Summary
An overview of complete electrical and thermal characterization of the SiC diode
assemblies has been presented in this chapter.
Ag-sintering and SnAg-TLP bonding were used as die-attachment methods, while AlX
wire bonding (ϕ = 300 µm) was used for electrical interconnection. The diodes were
mounted on AlN DCB substrates. The devices completely survived the assembly
processes.
The electrical characterization such as forward IV-characteristics (both pulsed and
continuous) and breakdown voltages were performed for both Ag-sintered and TLP
bonded diodes. The on-state resistances for Ag-sintered diodes were slightly less than
the TLP bonded diodes. The breakdown voltages for the assembled diodes were in the
range from 740 – 760 V.
The thermal resistance of the sintered SiC assemblies was lower than that of the TLP
bonded assemblies, which indicates better thermal dissipation behavior of sintered
assemblies.
The power cycling of the SiC assemblies was performed in order to analyze the fatigue
in the die-attach layers. The testes were performed at various junction temperature
swings ∆Tj i.e. 80 K, 100 K, and 120 K etc. The failure criterion was selected to be an
increase of diode’s forward voltage by 10 %. Thereafter, the cross sections of the
assemblies were made to analyze the crack lengths and associated crack-rates at various
junction temperature swings ∆Tj.
103
7
Assembly and Packaging of GaN
HEMTs
This chapter describes the electrical and thermal characterization for assembled GaN
devices. Silver sintering and transient liquid phase bonding were used as die-attachment
methods. Whereas, gold, and palladium were investigated as interconnect materials. A
systematic electrical characterization was performed from the on-wafer measurements
up to the final assembly process. The influence of thermal effects on the electrical
properties such as on-state resistance at various power levels was studied before and
after the assembly process. Moreover, the thermal resistance of the assemblies was
measured for various die-attachments. The surface temperature characterization was
performed for active GaN devices using infrared thermography and surface mounted Pt1000 temperature sensors. The real junction temperatures of the devices were measured
using micro-Raman spectroscopy. An important correlation between the actual junction
temperature and the surface temperature was made, as high channel temperatures limit
the reliability of the device itself. Passive temperature cycling from -40 to +150 ºC and
active power cycling at various surface temperature differences were performed with the
assembled GaN devices as an indication of initial reliability. Finally a complete package
for the GaN is demonstrated, in which the packaging materials survived temperature up
to 480 ºC.
7.1
GaN-on-Si HEMTs
Gallium nitride (GaN) based high electron mobility transistors (HEMTs) on inexpensive,
large-diameter silicon (Si) substrates are predestined for the use in power electronics
applications [79], [84]. These devices achieve high breakdown voltages in the off-state,
whereas, low on-state resistance and high on-state currents are achievable due to high
sheet carrier density and high electron mobility in the AlGaN/GaN hetrojunction
transistor channels. In this study, GaN-on-Si HEMTs [80] have been used for the
assembly process. The objective was to develop an assembly process, which can take
full advantage of the aforementioned device’s electrical characteristics. Moreover,
assembly must minimize the thermal and thermo-mechanical influences on the device
performance. The GaN structures are grown by Metal-Organic Chemical Vapor
Deposition (MOCVD) on 4-inch diameter Si (111) substrates [80], [141], with a
thickness of 675 µm. The grown structures consist of an AlN-nucleation layer, a thick
GaN buffer layer with a thickness in the range from 3 – 5 µm, an AlGaN barrier layer
104
7.2
Assembly Process for GaN-on-Si HEMTs
with a typical thickness of 25 nm and thin 3 nm GaN cap layer. The transistor contains a
Schottky gate and has a negative threshold voltage of VTH = -3 V. The devices have a
lateral design with an interdigital finger layout structure and a total gate width ranging
from W = 134 – 260 mm. The drain to gate length is LDG = 20 µm, whereas, the gate
length is in the range from LG = 1 – 2 µm. In order to reduce the electric field peaks and
dynamic dispersion, a gate and a source field plate are incorporated. These devices are
capable of delivering maximum drain currents over 70 A and breakdown voltages of
900 V. An overview of the high potential of such GaN-on-Si devices is published by
Ikeda et al. [79].
Figure 7.1: Top view of the GaN-on-Si
device
7.2
Figure 7.2: Cross section of GaN-on-Si HEMT
Assembly Process for GaN-on-Si HEMTs
For the assembly purposes, the used GaN-on-Si HEMTs had a die size of 3 mm × 4 mm.
The metallurgy of the chip backside and frontside, which are suitable for the dieattachment and interconnection respectively, are described in table 7.1.
Table 7.1: Metallurgy of GaN-on-Si HEMTS
GaN-on-Si HEMT
Metallization
Thickness (nm)
Suitability
Ti-Au
10-400
Ag-sintering
Ti-Ni-Ag
20-100-200
TLP bonding
Au (Electroplated)
7000
Au and Pd wires
Backside
Frontside
GaN HEMTs were mounted on AlN DCBs using Ag-sintering and TLP bonding. The
thickness of the Ag-sintered and the TLP bonded layer were on average 20 µm and
105
Chapter 7
Assembly and Packaging of GaN HEMTs
28 µm respectively. For electrical interconnection, gold and palladium thin wires with a
diameter of 50 µm were used. On both drain and source sides, a total of 18 wire bonds
was used. While, 2 wire bonds were used for the gate connections. The layer thicknesses
of various assembly layers are described in table 7.2. During electrical characterization,
the assembly was mounted on a chuck with a fixed temperature of 25 ºC, which was
continuously monitored using a thermocouple.
Table 7.2: Materials and thickness of assembly layers
Assembly
Material
Thickness (µm)
Chip
GaN-on-Si
150
Ag-sintered layer
25
Sn-Ag TLP bonded layer
28
Cu
300
AlN
633
Cu
300
Die-attach
DCB substrate
7.3
Electrical Characterization
A systematic analysis of the electrical characteristics was performed from the on-wafer
measurements to the final assembly process. The GaN HEMTs were epitaxialy grown on
a 4-inch Si-wafer with a thickness of 675 µm. Initially the measurements were
performed with the on-wafer devices. Later on, the wafer was diced into two halves. One
half was kept as it is and other half was thinned down to 150 µm. For the sake of
consistency, the measurements were performed for both thinned (150 µm) and thick half
(675 µm). The objective was to study the self-heating effects of the devices due to
various wafer thicknesses. Later on the backside metallization was performed and both
halves were diced into individual devices. Finally, the individual devices were mounted
on AlN DCBs with various die-attachment and interconnection techniques and later on
electrically characterized. The systematic analysis was aimed at studying the influence
of thermal effects on the electrical properties of GaN HEMTs. For instance, the selfheating effects of the transistors cause a reduction of the electron mobility in the
transistor’s channel [142]. Consequently, an undesired increase of on-state resistance
occurs.
106
7.3
Electrical Characterization
7.3.1 Wafer Statistics
A GaN-on-Si wafer was provided by Fraunhofer Institute of Applied Solid State Physics
(IAF) Freiburg, Germany. The wafer consisted of various designs of HEMTs with
different gate widths. The table 7.3 shows the statistics of the devices used during the
experiments.
Table 7.3: Details of GaN-on-Si device wafer
Wafer details
GaN-on-Si
Wafer No: M0263-3
Run No: PW120126
Layout name
Gate width (mm)
Total number of
devices
C1
134
35
C2
260
32
C3
217
33
B2
220
35
B3
194
35
7.3.2 Forward Characteristics
Figure 7.3: Equivalent circuit diagram of measurement setup for pulsed (tpls = 0.1 ms) IVcharacteristics
The pulse-mode forward characteristics (IV-curves) were measured during the
experiments. A drain to source current Ids, with a pulse width of tpls = 100 µs was
applied. While, a continuous gate to source voltage Vgs was stepped from -3 V to +1 V
with a step size of 1 V. The measurements were performed with a defined ground
potential and a 4.7 µF capacitor was attached between the gate and source to suppress
the instabilities, which can occur due to inductances of the cables and other parasitic
107
Chapter 7
Assembly and Packaging of GaN HEMTs
effects. A 4-point measurement setup was used to measure the on-state resistance Rds,on
with high resolution and to eliminate the resistive contribution of cables and needles.
The schematic of the test setup is shown in figure 7.3. The details of the configurations
for drain to source voltage Vds and gate to source voltage Vgs during pulse-mode
measurement are given in table 7.4.
Table 7.4: Test conditions during measurement of pulsed IV-curves
Vgs Configuration
Vds Configuration
Vgs,start (V)
-3
Vds,start (V)
0
Vgs,end (V)
1
Vds,end (V)
10
`Step size (V)
1
Step size (V)
1
Icompliance (mA)
10
Icompliance (A)
98
Pcompliance (mW)
100
Pcompliance (W)
3000
/
/
tpls (µs)
100
Figure 7.4: Pulsed (tpls = 100 µs) forward characteristics of on-wafer and assembled GaN
HEMTs
During the course of experiments the measurements were performed for all the
devices in the wafer. However, in this work the measurement data will be presented
for the layout B2 with the gate width of 220 mm. The figure 7.4 shows the comparison
108
7.3
Electrical Characterization
of forward characteristics for the thick (675 µm) and thin (150 µm) devices before and
after the assembly process. It can be seen that by thinning the wafer from 675 µm to
150 µm, the self-heating effects are reduced as indicated by decrease in on-state
resistance. For both the thin and the thick devices, a further decrease of on-state
resistance after the assembly process shows that thermal dissipation behavior of the
devices is improved. This trend was observed for all the devices in the wafer. The
systematic analysis was performed for both sintered and TLP bonded GaN HEMTs.
The B2 (Gate width: 220 mm) devices were mounted with SnAg-TLP bonding on an
AlN DCB and interconnections were made using gold wire bonds with the diameter of
50 µm.
7.3.3 Effect of Interconnect Resistivity
The GaN HEMTs are aimed at high-power applications. The electrical resistivity of the
interconnection material strongly affects the on-state resistance of the devices. During
the experiments, Au and Pd-based thin wire (50 µm) bonding was used as
interconnection technology. The resistance offered by the wire bonds is added in series
with the on-state resistance of the GaN transistor. During the device operation at high
temperatures, the resistance of the bonding wires increases and becomes comparable to
the on-state resistance of the GaN HEMT. Consequently, the on-state resistance is
increased which causes additional losses. Due to its stability at high temperatures, Pd has
been chosen an alternative to Au wire bonding [15]. The drawback of Pd is that its
electrical resistivity is higher than Au. The figure 7.5 gives the comparison of electrical
resistivity of Au and Pd. It can be seen that at high temperatures, the resistivity of the Pd
increases more sharply as compared with gold [132]. The table 7.5 summarizes the
analytical calculation of the resistances, which are offered by the Au and Pd wires.
Table 7.5: Calculated resistance of the bonding wires
Material
ρ at 20 ºC
(10-8 Ωm)
Au
(50 µm)
2.2
Pd (50 µm)
10.5
Chip side
No of wire
bonds
Bond length
(mm)
Calculated
resistance
(mΩ)
Drain
18
4
2.5
Source
18
6
3.7
Drain
18
4
11.8
Source
18
6
17.7
109
Chapter 7
Assembly and Packaging of GaN HEMTs
Figure 7.5: Temperature dependent electrical resistivity of Au and Pd [132]
In order to investigate the effect of interconnect resistivity, two 675 µm GaN (B2 layout
and gate width: 220 mm) devices were mounted on an AlN DCB using SnAg-based TLP
bonding. One device was bonded with gold wire bonds, whereas, the other device was
bonded with palladium wires. The pulsed (100 µs) IV-characteristics were measured for
both assembled devices, with different interconnect materials. The test configurations
were the same as described in table 7.4. It can be seen in figure 7.6 that on-state
resistance as well as the maximum drain to source current Ids decreased in case of Pdbased wire bonded HEMT. With the increasing current, the dissipated power results in
high temperatures in the wire. The increase of on-state resistance is attributed to the high
electrical resistivity of Pd wire at higher temperatures as compared to Au wire.
Figure 7.6: Pulsed (tpls = 100 µs) forward
characteristics of GaN HEMTs with Au and
Pd wire bonds
Figure 7.7: Rds,on of GaN HEMT at Vgs = 1 V
with Au and Pd bond wires during pulsed
(tpls = 100 µs) IV-measurements
In order to analyze the effect of interconnect resistivity, the on-state resistance of the
GaN HEMT at Vgs = 1 V was plotted against the power dissipated during the pulsed-IV
110
7.3
Electrical Characterization
measurements. In can be seen that in the linear operational range of the device i.e. from
0 to 325 Watts, the on-state resistance of the Pd-bonded HEMT is higher than Aubonded HEMT and it enters the saturation region earlier than the Au-bonded HEMT.
This effect at higher current densities can be attributed to the increasing electrical
resistivity of the Pd-wires, which is temperature dependent. Once the device enters the
saturation region, the reduced electron mobility inside the transistor channel causes
further increase of on-state resistance of the device [80]. The interconnect resistance and
channel resistance are added in series, which results in exponential increase of on-state
resistance.
7.3.4 Effects of Assembly on Electrical Characteristics
In the systematic analysis from on-wafer measurements to the final assembly, the
influence of thermal effects on the electrical properties of GaN HEMT was carried out.
The comparison is made for on-wafer thin (150 µm) and on-wafer thick (675 µm)
devices at Vgs = 1 V during pulsed-IV (0.1 ms) measurement in figure 7.4. The on-state
resistance of the on-wafer thin (150 µm) devices is lower than the on-wafer thick
(675 µm) devices as shown in figure 7.9. This shows that thinning of the wafer reduces
the self-heating effects of the devices.
Figure 7.8: On-state resistance of on-wafer
GaN HEMTs at Vgs = 1 V during pulsed
(0.1 ms) IV-measurements
Figure 7.9: On-state resistance of assembled
GaN HEMTs at Vgs = 1 V during pulsed
(0.1 ms) IV-measurements
The analysis was also made for the assembled thin (150 µm) and thick (675 µm) GaN
HEMT (B2: Gate width: 220 mm). The assemblies consisted of SnAg-TLP bonded
HEMTs with gold wire bonds (ϕ = 50 µm). The figure 7.9 shows that in the linear
operating region, the on-state resistance of the thin and thick devices at low power levels
i.e. 0 to 300 W, is similar. Whereas, at high power levels i.e. above 350 W, the on-state
resistance of the thick assembled HEMT starts increasing more rapidly and it enters the
saturation region earlier than the thin device. This implies that for the thicker devices,
111
Chapter 7
Assembly and Packaging of GaN HEMTs
the self-heating effects significantly influence the on-state resistance. The electron
mobility in transistor channels goes down with increasing temperature. Hence, the
device thinning is necessary to improve the thermal behavior of the devices. Moreover,
the maximum saturation currents Idsat,max are also directly related to the on-state
resistances. The table 7.6 gives a comparison of on-state resistances and maximum
saturation currents for various combinations of assembly process.
Table 7.6: Assembly effects on electrical characteristics. The comparison is made at high power
at Vgs = 1V and Vds = 6V
7.4
Devices
Rds,on (mΩ)
Idsat,max (A)
On-wafer HEMT, 675 µm
112
55
On-wafer HEMT, 150 µm
104
61
HEMT, 675 µm, TLP, Au wire
103
58
HEMT, 150 µm, TLP, Au wire
97
67
HEMT, 675 µm, TLP, Pd wire
112
54
HEMT, 150 µm, TLP, Pd wire
107
55.5
HEMT, 675 µm, Ag-Sinter, Au wire
102
59
HEMT, 675 µm, Ag-Sinter, Au wire
96
69
HEMT, 675 µm, Ag-Sinter, Pd wire
110
54
HEMT, 675 µm, Ag-Sinter, Pd wire
105.5
56
Thermal Resistance of Assembled GaN
HEMTs
In order to investigate the thermal dissipation behavior of the assembled GaN HEMTs
(B2: Gate width: 220 mm), the thermal resistance of the complete assembly was
measured. GaN HEMTs were mounted on to the AlN DCB using the Ag-sintering and as
well as the SnAg-based TLP bonding. The details of the various layer thicknesses in the
assembly are previously summarized in table 7.2. The electrical interconnections were
made using the gold wire bonds. The assembled transistors were mounted on a chuck
with a constant temperature of 40 ºC. A thin layer of grease was applied between the
DCB and the hot chuck. A constant voltage to -2.6 V was applied between the gate and
112
7.4
Thermal Resistance of Assembled GaN HEMTs
the source to open the gate slightly. While the drain to source voltage was varied from
5 V to 25 V in order to get the dissipated power between 5 W and 130 W. The surface
temperature of the HEMT was measured using an infrared camera, QFI MWIR-512
from InfrascopeTM.
Figure 7.10: Thermographic image of GaNon-Si HEMT at 100 W of power
Figure 7.11: Temperature distribution along the
line on the chip surface
The thermal resistance of the assembly was measured using equation 7.1.
R th 
T Ttop(Chip surface) - Tbottom(DCB bottom)

P
Vds .Ids
7.1
Where, Ttop is the chip’s surface temperature, Tbottom is the fixed temperature at the
bottom of the DCB, Vds is the applied drain to source voltage and Ids is the applied drain
to source current. The thermographic image is shown in figure 7.10. For both Agsintered and SnAg-based TLP bonded assemblies, the chips and the substrates were
identical, while only difference was the die-attach layer. The measured thermal
resistance for both die-attachments was in the same range. The thermal conductivity of
the Ag-sintered layer λsintered is reported from 100 to 200 W/mK [31]. Relative to this
value the thermal resistance was calculated using equations 7.2 to 7.4 .
R th,sintered 
d
sintered  A
 0.0125 K/W
R th  R th,TLP - R th,sintered  0.031 K/W
R th,sintered
R th,TLP

 TLP
sintered
7.2
7.3
7.4
 TLP  59 W/mK
113
Chapter 7
Assembly and Packaging of GaN HEMTs
The difference in thermal resistance of the Ag-sintered and TLP bonded assemblies was
found to be 0.031 K/W. Assuming that all layers in both assemblies are identical except
the die-attach layer. Consequently, the increase in thermal resistance of TLP bonded
GaN assembly, can possibly be attributed to TLP bonded layer. During the
measurements, it was found that thermal dissipation behavior of the Ag-sintered and
TLP bonded layers was promising. The real power dissipation is in a GaN HEMT occurs
in the channel caused by the electron drag. The surface temperature measurements can
possibly include the reflections from the gold lines and field plates above the gate and
the source. A major concern with these kind of measurement is the emissivity. The
values for emissivity for different materials on chip surface i.e. gold (0.49) and
polysilicon (0.6) varies [143]. Therefore, micro-Raman spectroscopy for the same
devices without field plates was performed to get the actual junction temperatures [144].
7.4.1 Surface Temperature Characterization
The surface temperature of the HEMT was measured using Pt-1000 temperature sensor,
which was mounted on top of chip surface using a thermally conductive adhesive. A
correlation was made between the Pt-1000 sensor readings and the readings measured
with InfrascopeTM QFI MWIR-12 infrared thermal camera. In both cases, the base plate
temperature is maintained at 25 ºC and gate voltage is adjusted to dissipated appropriate
power between drain and source. Both surface temperature profiles closely match with
each other as shown in the figure 7.12.
Figure 7.12: Surface temperature characterization with IR camera and Pt-1000 sensor
114
7.4
Thermal Resistance of Assembled GaN HEMTs
7.4.2 Micro-Raman Spectroscopy
Infrared (IR) thermography is a suitable method for determination of surface
temperatures in an active device. However, there are some drawbacks with this
technique. The wavelength regions of the IR imaging are limited with a wave length of
2 – 5 µm [143], [145]. Consequently, the determination of the hot spots of the size
0.5 µm or less are nearly impossible [146], which occurs inside the transistor channels.
Moreover, the field plates in GaN HEMTs cover the gate and source region and no direct
access to the transistor channels can be made. For GaN HEMTs, infrared thermal
imaging is only limited to surface temperature distribution. Micro-Raman Spectroscopy
has already been demonstrated as a promising method for investigating the channel
temperatures in a GaN HEMT with a higher special resolution [147], [144]. This
technique is based on Raman scattering, in which a phonon scatters inelastically from a
crystal structure with the creation or annihilation of one or more phonons. The spectra of
the scattered phonons are temperature dependent and are different from those of incident
phonons [143]. The change in phonon frequency as a function of temperature can be
explained by the equation 7.5.
  o 
A
e
Bho /k BT
1
7.5
Where, ωo is the phonon frequency at 0 K, T is the absolute temperature, kB and h are
Boltzmann and Planck constants respective, A and B are material dependent fitting
parameters [148].
The Micro-Raman Spectroscopy was performed for a GaN-on-Si HEMT device with a
gate width (Wg) of 10 mm. The measurements were made at Bristol University, UK.
Four of such devices were present on the chip with an area of 2 mm × 2 mm. There were
no gate and source field plates present on the devices. So the hot spots in the transistor’s
channel could be monitored directly. The measurement points were selected in the center
of the structure. The gate to source voltage was set at 0 V and drain to source voltage
was varied to get two dissipated power levels at 24 W and 35 W. The chips were
mounted on AlN DCB using Ag-sintering. The DCB was mounted on an active thermal
chuck with a silver heat transfer compound. The DCB temperature was monitored at the
corner using a thermocouple. The set chuck temperature was kept with in a variation of
4 ºC at maximum dissipated power. The GaN channel temperature was measured
0.25 µm away from the gate edge as shown in figure 7.13. The measured temperature was
a volumetric average within a cylinder of diameter 0.5 µm approximately and through
the thickness of GaN layer.
115
Chapter 7
Assembly and Packaging of GaN HEMTs
Figure 7.13: Scheme for channel temperature measurement using Raman Spectroscopy
Due to high special resolution of 0.5 µm, more accurate temperature measurements in
the transistor’s channel were possible. The measured junction temperature for the device
(Gate width: 10 mm) was plotted against the normalized power dissipation per
millimeter square area of the chip. A linear interpolation for Raman measurements was
made for power dissipations between 1 and 11 W/mm2. The Raman measurements were
correlated to the surface temperature measurements using the IR thermography and the
mounted Pt-1000 sensor for the 12 mm2 devices as shown in figure 7.14. The
measurement shows that the peak Raman temperature is by approximately 50 % higher
than the peak temperature measured by IR camera and Pt-1000 sensor. A similar
correlation of Raman versus IR thermography has been shown by Sarua et al., where
40 % higher peak temperature values for Raman measurements were found [149].
Figure 7.14: Correlation between junction and surface temperatures for estimating
temperatures in the active transistor channels from the surface temperature
116
7.5
Passive Temperature Cycling
Figure 7.15: GaN HEMT TLP bonded on AlN DCB using gold wire bonds. Pt-1000 sensor is
mounted on chip surface
7.5
Passive Temperature Cycling
The assemblies were subjected to passive temperature cycling with ∆T of 190 K. It was
found that both die-attachments and interconnections passed the shear and pull tests.
According to MIL-STD-750-2, the minimum die shear strength with a chip area of
12 mm2 must be at least 6 MPa, while, minimum bond pull strength for wire diameter of
ϕ = 50 µm must be at least 30 mN.
Table 7.7: Average shear strength after passive temperature cycling
Average shear strength
Dei-attachments
After 1000 TC of ∆T = 190 K
Ag-sintering
TLP bonding
39 MPa
36.5 MPa
Average pull strength
Wire bonds
After 1000 TC of ∆T = 190 K
Au wire
Pd wire
310 mN
430 mN
117
Chapter 7
7.6
Assembly and Packaging of GaN HEMTs
Active Power Cycling
An experimental setup was built for the power cycling of GaN HEMTs. The setup
consisted of two programmable power supplies. The PS-2042-20B from ElektroAutomatik GmbH & Co. KG was used for dissipating power between drain and source.
Whereas, a voltage source HM8142 from HAMEG Instruments GmbH was used for
controlling the gate of the GaN HEMT. During the power cycling, the temperature
sensor (Pt-1000) readings from the chip’s surface and the cooling plate were acquired
using a data acquisition unit Agilent 34970A. While, the voltage readings between the
source and drain were measured using a digital multimeter Agilent 34401A. All the
devices were connected with a personal computer using appropriate general purpose
interface bus (GPIB) as shown in block diagram in figure 7.18. The control was
generated using a self-written LabVIEW Software program. The assembly consisted of
sintered and TLP bonded HEMTs bonded on AlN DCB using gold wire bonds. The
assembly was mounted on a cooling plate using a thermally conductive grease with
forced water convection. The temperature of the cooling plate always remained at
16.7 ºC. The sizes of various assembly layers are described in table 7.8.
Figure 7.16: Schematics of the mounted assembly
Table 7.8: Materials, thicknesses and areas of assembly layers
Assembly
Material
Thickness (µm)
Area (mm2)
Chip
GaN-on-Si
150
12
Ag-sintered layer
25
12
Sn-Ag TLP bonded
layer
28
12
Cu
300
400
Die-attach
DCB substrate
118
7.6
Assembly
Thermal grease
Active Power Cycling
Material
Thickness (µm)
Area (mm2)
AlN
633
420
Cu
300
400
Matrix filled with
Ag particles
50
400
Figure 7.17: Circuit diagram for the power cycling setup
Various bias settings were selected for GaN HEMTs for various surface temperature
differences i.e. 80 K, 100 K and 120 K. The condition for ∆TSurface of 80 K is shown in
table 7.9.
Table 7.9: Power cycling conditions with Vgs = 1V
Assembly
Vds (V)
Ids (A)
P (W)
On-state
TSurface (ºC)
Off-state
TSurface (ºC)
∆TSuface
(ºC)
Ag-sintered
4.6
16.6
76.3
138.4
17.1
121.3
TLP-bonded
4.7
16.8
79
141
17.3
123.7
119
Chapter 7
Assembly and Packaging of GaN HEMTs
Figure 7.18: Block diagram of power cycling setup
During the course of power cycling, the on-state and off-state times were selected to 3
and 3.5 seconds respectively. The time duration were selected to get a stable steady state
Pt-1000 temperature sensor response. Along with the surface temperature difference, the
thermal resistance of the whole assembly was monitored during the power cycling. The
failure criterion was selected as the increase of gate leakage current beyond 50 mA was
regarded as the device failure condition as shown in figure 7.20. An x-ray inspection of
the die-attach layer did not indicate any considerable damage to the layer, which was
later confirmed by the metallographic cross sections.
During the power cycling tests, the GaN devices failed before any considerable damage
to the die-attach layer, which was later investigated using x-ray inspections as shown in
figure 7.21. No crocks were seen at the interface. The devices mounted with Ag-sintering
and TLP bonding showed comparable power cycling capability. However, Ag-sintered
GaN HEMTs showed 16 %, 14 % and 25 % more cycles as compared to TLP bonded
HEMTs at ∆Tsurface of 80 K, 100 K and 120 K respectively. This behavior can be related
to high thermal conductivity of the Ag-sintered layer as compared to TLP bonded layer,
which dissipates heat quickly to the heat sink. With a correlation factor of 1.5 from
surface temperature measurements to Raman spectroscopy, the approximated junction
temperatures are also plotted along with the surface temperatures in the power cycling
curve as shown in figure 7.19.
120
7.7
Short-Term High-Temperature Tests
Figure 7.19: No of power cycles to failure for sintered and TLP bonded HEMTs
Figure 7.20: Device failure of a TLP bonded
GaN HEMT on AlN DCB indicated by
increased gate current
7.7
Figure 7.21: X-ray image of the die-attach
through the device mounted with sensor
Short-Term High-Temperature Tests
The assembled Ag-sintered and SnAg-TLP bonded GaN HEMTs along with the Au-wire
interconnects were subjected to short-term high-temperature active power cycles. The
assembly was mounted on an aluminum cooling plate with convective water cooling.
The temperature of the cooling water was 16.7 ºC. 130 W of electrical power was
dissipated in the HEMT with on-state time of 5 seconds and off-state time of
121
Chapter 7
Assembly and Packaging of GaN HEMTs
5.5 seconds. The surface temperature of 230 ºC was measured using a Pt-1000 sensor,
which is mounted on the chip surface using a thermal adhesive. According to correlation
with Raman measurements, the actual peak junction temperature of the device is
expected to be around 340 ºC. This operational temperature range is already up to the
limit of operational reliability of device. The devices were destroyed after 20 cycles,
while the assembly survived the active high temperature cycles completely.
7.8
Complete Package
Commercially available discrete package components, consisting of a copper base plate,
AlN DCB substrate and copper interconnects, were obtained from Arkansas Power
Electronics International (APEI), Inc. These components had a surface metallization of
electroplated Ni-Ag. If these components are obtained in the form of an assembled
package, the AlN DCB is mounted on the base plate using a Sn96.5Ag3.5 solder and
also the copper interconnects are attached on the DCB using the same solder. This
package is designed to operate safely at 200 ºC with current carrying capabilities up to
50 A [150].
Figure 7.22: Complete package for GaN HEMT
The package components were attached using Ag-sintering and TLP bonding methods.
The DCB to base plate attachment was realized by using TLP bonding. The foil-based
TLP process provided the advantage of bonding large surfaces of area 180 mm2, with a
uniform thickness of 30 µm. The copper interconnects were mounted on the front side of
DCB using Ag sintering. For GaN chip attachment, both sintering and TLP bonding
were used, while gold wire bonding was used for electrical interconnections between the
chip and the Ag-sintered copper interconnects. Figure 7.22 shows the assembled GaN
HEMT along with the complete package and the cross section is depicted in figure 7.23.
122
7.8
Complete Package
Figure 7.23: Cross section of the new package
7.8.1 Thermal Modelling
The complete package was designed to exhibit good thermal dissipation behavior, so
that a high power-per-unit area of the GaN-on-Si HEMT can be achieved. The
Sn96.5Ag3.5 solder layers in the commercially available package were replaced by Agsintered and TLP bonded, which have higher thermal conductivities in comparison with
the solder. The data for layer thicknesses and their thermal conductivities are shown in
table 7.10.
Table 7.10: Thickness and thermal conductivity of assembly layers
Assembly
Thickness (µm)
Thermal Conductivity
(W/mK)
Chip
150
148
Ag-sintered
20
100 – 200 [19]
TLP bonded
28
67
Cu (DCB)
150
385
AlN
350
175
Cu (DCB)
150
385
DCB-to-base plate TLP
bonded connection
28
67
Cu (Base plate)
2000
385
Die-attach
123
Chapter 7
Assembly and Packaging of GaN HEMTs
Assembly
Thickness (µm)
Thermal Conductivity
(W/mK)
Thermal Grease
50
10
For the complete package in figure 7.22, the thermal equivalent circuit is depicted in
figure 7.24. The package was mounted on a heat sink using a thermal grease. The
temperature of the heat sink was assumed to be identical to the ambient temperature i.e.
25 ºC. Moreover, an infinite thermal conductivity of the heat sink was assumed.
Figure 7.24: Equivalent thermal circuit for the package
The theoretical 1-dimensional thermal resistance was calculated for a sintered GaN
HEMT (B2, Gate width: 220 mm) with an area of 12 mm2. In addition, the thermal
resistance measurement of the complete package was measured. The package was
mounted on a cooling plate with a fixed temperature of 25 ºC using thermal grease. The
surface temperature of the chip was measured using a Pt-1000 temperature sensor and
later on correlated with Raman measurements to get actual junction temperature. The
measured value of thermal resistance was 2.5 K/W. This is higher than the 1dimensional theoretical value i.e. 1.2 K/W, which is based on equivalent thermal circuit.
The electrical characteristics of the assembled device were also measured after the
assembly process. The measured parameters are summarized in table 7.11.
Table 7.11: Electrical characteristics after assembly
Electrical parameters
Values
Pulsed (0.1 ms) IV-characteristics
Rds,on at Vgs = 1V and Vds = 1V
54 mΩ
Pulsed (0.1 ms) IV-characteristics
Ids,max at Vgs = 1V,
70 A
Ids,max at Vgs = 1V
Continuous IV-characteristics
124
32.5 A
7.9
Electrical parameters
Rds,on at Vgs = 1V and Vds = 1V
Continuous IV-characteristics
Maximum power-per-unit-area
Continuous IV-characteristics
Chapter Summary
Values
66.7 mΩ
11 W/mm2
Figure 7.25: Ag-sintered GaN-on-Si HEMT (Gate width 260 mm) on new package with Au
wire bonds
7.9
Chapter Summary
A systematic electrical characterization from the on-wafer GaN HEMTs to the final
assembly process leads to the following conclusions.
The device thinning from 675 µm to 150 µm is essential to avoid self-heating effects as
indicated by a decrease of on-state resistance. A further decrease of on-state resistance
for the assembled devices as compared to on-wafer devices indicates the improvement in
thermal dissipation behavior.
During the pulsed-IV measurement, the on-state resistance for the assembled thick
(675 µm) and thin (150 µm) devices in the low power regions i.e. 0 to 300 W remains
similar. Whereas, at high power levels i.e. above 350 W, the self-heating effects in the
thick devices greatly influence the on-state resistance. Consequently, the electron
mobility in the transistor channel goes down [80].
The surface temperature measurements from the IR thermal camera (Tsurface,IR) and
surface mounted Pt-1000 sensor (Tsurface,Pt1000) only gives the temperature distribution on
the surface of the chip. The actual junction temperature inside the transistor channels
125
Chapter 7
Assembly and Packaging of GaN HEMTs
(Tchannel,Raman) is obtained through Micro-Raman Spectroscopy. A correlation was
between the Raman and surface temperature was made. The actual junction temperature
exceed by 50 % as compared to the surface temperature.
GaN HEMTs survived the Ag-sintering and TLP bonding process. The electrical
characteristics were retained after the mounting process.
The thermal resistance of the Ag-sintered HEMTs on AlN DCBs was better than the
TLP bonded HEMTs by a factor of 4 %. The Au wire bonds proved superior to Pd-wire
bonds in terms of current carrying capability. At high current densities, the temperature
dependent electrical resistivity of Pd wire increases more rapidly than gold [132].
After passive temperature cycling of ∆T = 190 K, both die-attachments exhibited dieshear strengths above 30 MPa for an area of 12 mm2, while, both gold and palladium
wires (ϕ = 50 µm) exhibited wire pull strengths above 300 mN. Both die shear strengths
and wire bond pull strengths are above the minimum limits of 6 MPa and 30 mN
respectively, according to MIL-STD-750-2.
Initially the power cycling tests were aimed at analyzing the fatigue in the dieattachment. However, all the devices failed before any considerable damage to the dieattach layer indicated by the x-ray inspection. The devices were operated at the surface
temperature (Tsrface,Pt-1000) of 150 ºC. The surface correlated channel temperature
(Tcorrelated-channel) is 220 ºC, which is approaching the channel reliable operational limits
i.e. 175 – 225 ºC [151].
The high-temperature short term tests indicated that operating the device near the surface
temperatures (Tsrface,Pt-1000) of 230 ºC is detrimental to the devices, where the surface
correlated channel temperature (Tcorrelated-channel) is 350 ºC.
The complete package along with the base plate was demonstrated for GaN HEMTs.
The package materials could survive temperatures up to 480 ºC. With good thermal
properties of Ag-sintered and TLP bonded layers, an excellent thermal dissipation
behavior for the complete package was obtained. With a combination of packaging
materials and thermal management scheme, the devices can obtain the maximum powerper-unit are of 11 W/mm2.
126
8
Discussion and Conclusions
This thesis work was aimed at the development of assembly techniques for high-power
and high-temperature GaN and SiC devices. In this chapter, the results from this thesis
work will be compared to the current state-of-the-art high-temperature stable assembly
methods and materials. The die-attachment and interconnection techniques were the
focus of investigations.
8.1
Die-Attachment Methods
For die-attachment, Ag-sintering and foil-based transient liquid phase (TLP) bonding
were investigated. Based on the performance parameters described in chapter 1, the
comparison of process parameters and properties of the die-attach layers with the current
state-of-the-art die-attachment methods is presented.
8.1.1 Foil-based Interlayer TLP Material
For foil-based TLP bonding process, the TLP-interlayer material was successfully
produced via electroplating in the form of Sn-Ag and In-Ag multilayer foils. Two
multilayer foil designs, consisting of a 3-layer sandwich structure and a 9-layer structure,
were successfully produced. A more homogeneous joint was obtained using the 9-layer
foil, where the diffusion of Sn or In was much faster in the thin Ag layer as compared to
sandwich foil structure. Consequently, the post-bonding annealing step can be avoided.
Compared to the sate-of-the-art TLP bonding processes, which mostly use TLPinterlayer systems based on evaporation and sputtering [27], [40], [59], the in-house
produced foil-based interlayer systems offer several advantages such as easy handling
and cost-effectiveness. The process complexity of foil production using electroplating is
less compared to interlayer-systems produced using thin film depositions. Furthermore,
they are a potential candidate for commercialization.
8.1.2 Comparison of Process Parameters
For both Ag-sintering and TLP bonding, complete process optimization and
characterization was performed. The process parameters greatly contribute to the
thermal and thermo-mechanical stresses during the die-attachment process. A
127
Chapter 8
Discussion and Conclusions
comparison of process parameters for the state-of-the-art die-attachments with the
currently investigated Ag-sintering and foil-based TLP bonding is given in table 8.1.
Table 8.1: Comparison of process parameters [19], [27], [39], [96], [98] - [101]
Die-attachments
Bonding
temperature
(ºC)
Bonding time
(min)
Bonding
pressure
(MPa)
Environment
State-of-the-art die-attachments
Ag3.5Sn96.5
250
1 – 1.2
No
Air
Au80Sn20
320
0.5 – 4
No
Nitrogen,
Argon
Au88Ge12
410
0.5 – 4
No
Nitrogen,
Argon
Ag-sintering
(Nano-particles)
280 – 350
15 – 60
No pressure
Air, Nitrogen
Ag-sintering
(Micro-particles)
225 – 275
3 – 15
5 – 40
Air, Nitrogen
In-Ag TLP
interlayer systems
180 – 220
1 - 120
>1
Nitrogen
Vacuum
>1
Nitrogen,
Hydrogen,
Vacuum
Sn-Ag TLP
interlayer systems
250 – 350
1 – 30
Die-attachments used in the thesis work
Ag-sintering
(Micro-particles,
230
3
10
Air, Nitrogen
Foil-based Sn-Ag
TLP bonding
240
30
5
Vacuum
Foil-based In-Ag
TLP bonding
210
15
8
Vacuum
The bonding temperatures and bonding pressures of the die-attachments used in this
thesis work are comparable with other state-of-the-art Ag-sinter processes and TLP
128
8.1
Die-Attachment Methods
bonding processes. While in comparison with eutectic AuSn and AuGe solders, the
bonding temperatures of die-attachments used in this work are lower. Consequently, low
thermal stresses are produced during the die-attachment processes and during device
operation. From the analytical calculations in chapter 5, which are greatly influenced by
the process temperature, it is evident that both Ag-sintering and TLP bonding processes
result in low die-attach shear stresses, low die normal stresses and low warpage in the
assembly as compared to AuSn and AuGe solders. The actual bonding time during the
TLP bonding lasts from few seconds to minutes [40]. However, the longer process
temperatures possibly contribute to the annealing of the joint, which can be optionally
made after the TLP bonding process.
GaN-on-Si HEMTs and SiC Schottky diodes successfully survived the high-stress
conditions during the bonding processes i.e. bonding temperatures and bonding
pressures. No damage to the devices occurred during bonding process using the
optimized process parameters. In addition, both processes can also be applied to largearea Si-based high-power devices i.e. IGBTs, MOSFETs etc. For demonstration
purpose, IXYS RF transistors (64 mm2) were bonded using both Ag-sintering and TLP
bonding.
8.1.3 Comparison of Die-Attach Properties
The Ag-sintering and foil-based TLP bonding were aimed at high-temperature operation.
Numerous die-attachment characterizations were performed to determine the properties
of the die-attach layers. The melting points of the TLP bonded die-attach layers were
measured using the differential scanning calorimetry (DSC) and the compositions of
TLP bonded joints before and after the annealing process were determined using energy
dispersive X-ray (EDX) spectroscopy. For both Ag-sintered and foil-based TLP bonded
assemblies, the out-of-plane warpage in the chip surface along the diagonal direction
was measured using the digital image correlation (DIC) method. The warpages were
measured at room temperature i.e. 30 ºC and at high temperatures up to 500 ºC. The
objective was to determine the bending stresses after the assembly process and also
during the high-temperature operation. In addition, the DIC method was also used to
determine the in-plane uniaxial strains during the tensile testing.
The tensile tests were performed at room temperature i.e. 25 ºC to determine the
mechanical properties such as elastic modulus. The thermal resistances of the complete
assemblies, with both die-attachments, were measured and thermal conductivity of foilbased TLP bonded layers was calculated relative to the Ag-sintered die-attach layer.
Based on the performance parameters described in Chapter 1, the comparison of material
properties of Ag-sintered and foil-based TLP bonded layers are made with the current
state-of-the art die-attachments and depicted in table 8.2.
129
Chapter 8
Discussion and Conclusions
Table 8.2: Comparison of material properties [4], [102] - [107]
Die-attachments
Melting
points (ºC)
Thermal
conductivity
(W/mK)
Electrical
conductivity
105(Ω.cm)-1
Elastic modulus
(GPa)
State-of-the-art die-attachments
Ag3.5Sn96.5
221
78
0.8 – 1
50 – 56
Au80Sn20
280
57
0.63
69
Au88Ge12
356
44
Ag-sintering
961
100 – 240
2.6 – 3.9
9 – 60
Cu-Sn TLP
(intermetallics)
> 415
34 – 70.4
/
112 – 134
Ag-In TLP
(intermetallics)
> 800 ºC
/
/
89 – 124
Ag-Sn TLP
(intermetallics)
> 600 ºC
/
/
78
74
Die-attachments used in the thesis work
Ag-sintering
961
100 – 200
2.3
40 – 50
Sn-Ag TLP
bonded foil
480 ºC
54 – 67
1.6
40 – 60
In-Ag TLP
bonded foil
> 500 ºC
45
1.3
30 – 40
Both Ag-sintering and foil-based TLP bonding were better than Ag3.5Sn96.5,
Au80Sn20 and Au88Ge12 solders in terms of high-temperature stability, electrical and
thermal properties. Moreover, they were more elastic than AuSn and AuGe solders.
Consequently, they can possibly take up thermal and thermo-mechanical stresses during
the die-attachment process and also during the thermal cycling in active device
operation.
Within the accuracy limits of the DSC equipment, both foil-based Sn-Ag TLP and In-Ag
TLP bonded joints showed high-temperature stability up to 480 ºC and 500 ºC
respectively. Moreover, due to the presence of ζ-phases in both Sn-Ag and In-Ag TLP
130
8.1
Die-Attachment Methods
bonded joints, it is expected that the actual melting points are much higher than 500 ºC
[128]. Hence, it can be concluded that high-temperature stable phases are produced
using foil-based TLP process and their melting points are in the range of the current
state-of-the-art Sn-Ag and In-Ag TLP intermetallic systems. However, in comparison
with other Cu- and Au-based TLP systems the melting points are higher.
So far no detailed investigation on electrical and thermal properties of TLP bonded
joints exists in literature, except for Cu-Sn intermetallics. In this thesis work, both
thermal and electrical properties of foil-based TLP bonded joints were determined. The
thermal conductivity of the TLP bonded layers was calculated relative to the Ag-sintered
layers and it came out to be in the same order or even better than Au-based eutectic
solders. For Ag-sintering, the electrical and thermal properties were comparable to the
other state-of-the-art Ag-sintered layers.
The literature mostly reports on the mechanical properties of the intermetallic phases,
which are determined mostly by “Nanoindentation” method [104], [106]. In this thesis
work, the mechanical properties of the TLP-bonded foils such as Sn-Ag, containing
multiple high-temperature material phases i.e. ζ (Ag85Sn15) and ε (Ag3Sn), were
measured. The tensile tests in combination with in-plane uniaxial strain measurements
determined both elastic and plastic behavior at room temperature. The foil-based Sn-Ag
TLP joints and In-Ag joints were found to be more elastic as compared to literature
values of Sn-Ag and In-Ag intermetallics [105].
In our investigations, the Ag-In multilayer foils were very often detected with cracks
inside. The existing research indicates a rapid indium diffusion into the base silver metal
after the deposition process, which leads to formation of brittle intermetallic phases
[105], [131]. In case of foil-based Ag-In TLP bonded joints, the possible existing cracks
in the interlayer system weakened the final joints during the bonding process. From the
viewpoint of electrochemistry, it is difficult to deposit a more noble metal (Ag) on a less
noble metal (In). Indium has higher potential to lose electrons and turn into ion, which
leads to non-uniform distribution of silver metal on indium layer during electrochemical
deposition. This can possibly be another factor contributing to the weakened strength of
Ag-In TLP bonded joints. Consequently, in this work foil-based Sn-Ag TLP bonding
was mostly adopted during the die-attachment of active GaN and SiC devices.
The bending stresses were calculated from the out-of-plane warpage of Si chips, bonded
with Sn-Ag TLP bonding and Ag-sintering, during the temperature change from 30 ºC to
500 ºC as described in chapter 5. It was found that generally the stress levels (1 –
20 MPa) for both die-attachments were low. But for Ag-sintered chips they were
slightly lower than the Sn-Ag TLP bonded chips. The measurement results are in
complete agreement with the analytical and finite elements simulations as shown in
chapter 5.
131
Chapter 8
Discussion and Conclusions
8.1.4 Reliability of Die-Attachments
Reliability studies for both Ag-sintered and Sn-Ag TLP bonded die-attach layers were
performed. The die-attachments were subjected to both passive temperature cycling
(TC) and active power cycling (PC) tests. The die-shear strength was selected as
comparison criteria during passive temperature cycling, which is determined through
shear tests according to test method “IPC-TM-650”. During the accelerated tests the dieattach layer is subjected to fatigue. Consequently, a crack is generated along the dieattach layer under the corner of the chip, where the shear stresses are maximum [64].
The shear strength of the die-attach layer goes down due to cracks. The comparison of
passive temperature cycling capability of the current die-attach methods with the stateof-the-art die-attachments is given in table 8.3.
Table 8.3: Comparison of passive temperature cycling capability
Die-attachment
τAvg (MPa)
τAvg (MPa)
(After TC)
Comments
State-of-the-art die-attachments
> 20 MPa
Ag-sintering
[19], [96], [97]
30 - 50
Au80Sn20 [122]
42 MPa
Au88Ge12 [123]
41 MPa
Au-In TLP [124]
>40 MPa
4000 TS (+50 to +250 ºC)
1000 TS (-40 to +160 ºC)
38 MPa
2000 TS (-65 to +150 ºC)
>17 MPa
2000 TS (+40 to +360 ºC)
> 30 MPa
120 TS (+35 to +400 ºC)
Si and SiC chips
sintered on AlN
and Al2O3 DCB
Si chips on AlN
DCBs
Si chips on Au
metallized Si3N4
substrates.
SiC on Al2O3 DCB
substrate
Die-attachments used in the thesis work
Ag-sintering
35 - 45
Foil-based Sn-Ag
TLP Bonding
30 - 40
132
> 30 MPa
1000 TS (-40 to +150 ºC)
> 30 MPa
1000 TS (-40 to +150 ºC)
Si and SiC chips
sintered on AlN
and Al2O3 DCB
Si and SiC chips
sintered on AlN
and Al2O3 DCB
8.1
Die-Attachment Methods
After passive temperature cycling, the shear strength of both Ag-sintered and foil-based
Sn-Ag TLP bonded chips proved to be similar or better than the state-of-the-art dieattachments. The power cycling of both GaN HEMTs and SiC Schottky diode
assemblies were performed at various junction temperature differences ∆Tj i.e. 80 K,
100 K and 120 K. In case of GaN-on-Si HEMTs, the device failure occurred before any
considerable damage to the die-attach layer, which was confirmed though x-ray
inspection and metallographic cross-sections. Therefore, only the power cycling test
results for SiC Schottky diode assemblies are compared to the other state-of-the-art SiC
assemblies. Herold et al. performed power cycling tests on SiC Schottky diode
assemblies with similar die-sizes and similar power cycling test conditions i.e. ton =3 sec
[140]. During the test, the increase of diode forward voltage Vf by 10 % was selected as
the failure criterion of the die-attach layer. In case of earlier wire bond lift-off in the
assemblies, the diodes were bonded again. The power cycling was performed until an
increase of 10 % of diode’s forward voltage from the initial value was measured.
Table 8.4: Comparison of power cycling capability
Die-attachment
method
Ag-sintering
Material
Novel Agsinter paste
LTS 275-3P2
∆Tj
TLP bonding
Soldering
(Herold et al.
[140])
Conductive
adhesive
SnAg-TLP 3layer foil
Ag3.5Sn96.5
PC-3001
No of power cycles to failure
70 K
366194
272842
80000
/
80 K
180630
159521
70000
45348
100 K
71000
61235
/
11556
120 K
34325
31241
/
3442
Both Ag-sintering and Sn-Ag TLP bonding showed superior power cycling reliability as
compared to soldering and conductive adhesives. The crack lengths and subsequently the
crack rates at various junction temperature swings ∆Tj were determined for the failed
samples during power cycling. The literature describes the crack rates for Ag-sintered
layers for various porosities (15 – 30 %) mostly during passive temperature cycling with
∆T = 160 – 230 ºC. Experimentally determined crack rates as low as 25 nm/cycle and as
high as 1 – 5 µm/cycle are reported for Si chips mounted on copper and DCB substrates
[68], [69], [152]. The crack rates for Ag-sintered and Sn-Ag TLP bonded layers during
short power cycling at various ∆Tj were in the range from 1.4 – 2.6 nm/cycle.
133
Chapter 8
Discussion and Conclusions
8.1.5 Modelling of Crack Propagation Rates
Based on plastic material models of Ag-sintered and SnAg TLP bonded layers, finite
element simulations were performed to determine the equivalent plastic strain
amplitudes (∆εp) for die-attach layers. The crack rates in the die-attachment layers were
modelled using Paris’ Law [64], which is given by equation 8.1.
da
= c1 (Δε p )c2
dN
8.1
Where da/dN is the experimentally determined crack rates, ∆εp is the equivalent plastic
strain range, while c1 and c2 are the material parameters.
Table 8.5: Material properties at T = 20 ºC for simulation
Assembly
Materials
E (GPa)
α (ppm/K)
ν
λ (W/mK)
Chip
6H-SiC
448
4
0.18
438
AlN
310
4.7
0.24
180
Cu
120
17
0.34
385
Ag-sintered
layer
40
19
0.3
100
SnAg-TLP
bond
45
18
0.28
67
Substrate
Die-attach
The plastic strain range (∆εp) in the die-attach layer was determined by finite element
simulations. A coupled thermal-mechanical simulation was performed to emulate the
power cycling of the SiC diodes mounted on AlN DCB. The material’s data is
summarized in table 8.5. Based on earlier mechanical characterization of both sintered
and TLP bonded layers, the materials were modelled with elastoplasticity. For
implementing plasticity in ANSYS simulations, multilinear kinematic hardening model
was used. The plasticity data was determined from the earlier uniaxial stress – strain
curves at room temperature. For more accurate material modelling, the experimental
stress – strain data at high temperature values has to be incorporated as well.
The finite element simulations provided data about the distribution of stresses and strains
in the assembly and especially in the die-attach layer. The maximum stress and strain
values occurred at the chip corners as shown in figure 8.2. A plot of stress versus strain
provides the hysteresis loop, which defines the cycling deformation in the die-attach
layers. All six stress (σx, σy, σz, σxy, σyz, σzx) and strain (εx, εy, εz, εxy, εyz, εzx) components
have to be taken into account. From the hysteresis loops, the equivalent values of the
134
8.1
Die-Attachment Methods
stress, strain and strain amplitude ∆εp were calculated in accordance with von Mises
formulas. The formula used for calculating equivalent plastic strain is given in equation
8.2 [153].
ε eq,pl =
2
3
(Δε x - Δε y ) 2 + (Δε y - Δε z ) 2 + (Δε z - Δε x ) 2 + 6 (Δε 2xy + Δε 2yz + Δε zx2 )
1/2
8.2
Where ∆εx, ∆εy, ∆εz, are the plastic strain amplitudes in x, y and z direction, while ∆εxy,
∆εyz, ∆εzx are the plastic shear strain amplitudes. The experimentally measured crack
rates were subsequently plotted against the strain amplitudes determined from finite
element simulations in a log-log graph as shown in figure 8.3. Consequently, the
materials parameters c1 and c2 were determined for both TLP bonded and Ag-sintered
layers and are mentioned in table 8.6.
Figure 8.1: Plot of plastic strain vs stress (in xdirection) after 3 power cycles of ∆T= 120 K
in Sn-Ag TLP bonded layer
Figure 8.2: Maximum equivalent plastic
strain at ∆T= 120 K in Sn-Ag TLP bonded
layer
Figure 8.3: Crack rate (experimental) vs plastic strain amplitude (simulation) for Ag-sintered
and SnAg TLP bonded layers
135
Chapter 8
Discussion and Conclusions
Table 8.6: Material parameters for modelling
Material parameters
Ag-sintered
SnAg-TLP bonded
C1
3.89
4.21
C2
0.23
0.22
8.2
Interconnection Methods
The gold and palladium thin wire (ϕ =50 µm) bonding was investigated as the
interconnection method for the die-attachment of GaN HEMTs. The gold is the standard
interconnection material for GaN HEMT packaging. The primary reason for selecting
palladium was that it is a proven high-temperature stable material [15]. The major
drawback is that at high-temperatures the resistivity of the palladium increases more
rapidly in comparison with the gold [132]. Consequently, the resistance of palladium
wire bonds at high-current densities and high-temperatures becomes comparable to the
on-state resistance of the GaN-on-Si HEMTs, which significantly reduces its maximum
current capability. For similar GaN-on-Si HEMTs (Layout: B2, Gate width: 220 mm),
the maximum continuous forward currents of 36 A and 27 A were measured for gold
and palladium wire bonds, respectively. The bond wires, on both source and drain sides,
were equal in numbers and lengths. The process temperatures during thermionic wire
bonding of Au and Pd were 180 Cº and 230 Cº, which do not accede the process
temperatures of the die-attachment. As a result, additional thermal stresses were avoided.
For interconnection of SiC devices, a novel aluminum alloy AlX from Heraeus GmbH
was used. The diameter of the wire was 300 µm. This material has been proven to be
stable up to 300 ºC [130]. This electrical resistivity of this material was found to be
similar to pure aluminum.
Table 8.7: Comparison for novel Al alloy material (AlX) with pure Al
Electrical resistivity
ρ (10-8 Ωm) at 25 ºC
Al
AlX
2.7
2.8
Decrease in pull strength after 300 C storage for 500 h in air
On Al bondpads
/
2.3 %
On Au bondpads
Up to 50 % [17]
6.3 %
Power cycling capability at various ∆Tj for AlX vs Al (Scheuermann et al.) [14]
136
8.3
SiC Schottky Diode Packaging
Al
AlX
70 K
380,000
420,000
110 K
60,000
68,000
135 K
21,000
26,000
The bonding of AlX wire on gold surface seemed to be improved greatly as compared to
Al wire. The decrease of bonding strength for Al wire on gold bond surface is a wellknown problem. Bonding of aluminum wire on gold surface leads to the formation of
AuAl2 intermetallic compound, which is referred to as the purple plague due to visible
color change. The formation of these intermetallics lead to formation of voids along the
bond line and weakens the bond [17]. The power cycling capability of AlX bond wires
was found to be equivalent to the pure aluminum wire.
8.3
SiC Schottky Diode Packaging
Due to their superior electrical and physical properties, SiC-based diodes are potential
candidates to replace Si-based devices in high-temperature and high-power applications.
So far Ag3.5Sn soldering and Ag-sintering are the state-of-the-art die-attachment
techniques for SiC diodes [140]. The literature reports on SiC diodes mounted using Agsintering on AlN and Al2O3 DCB substrates [28], [30]. The Ag-sintered die-attach layer
exhibits excellent electrical and thermal properties [4]. Recently, Infineon has
demonstrated the use of Cu-Sn diffusion soldering for mounting of their 5th generation
SiC diodes in TO-220, TO-247 and ThinPAK 8×8 packages [154]. The Cu-Sn diffusion
soldering has also been used for Si-based IGBTs [155]. These joints can sustain
temperatures up to 415 ºC. The major drawback associated with Cu-Sn diffusion
soldering is the formation of brittle Cu3Sn (ε) and Cu6Sn5 (η) intermetallic phases. The
E-Moduli of theses material phases vary in range from 112 – 134 GP [92].
Consequently, high thermo-mechanical stresses are produced during the temperature
cycling. Thereby, the cracks can easily develop in these die-attach layers [155]. The lead
frames in commonly used TO-220, TO-247 and ThinPAK 8×8 packages types are based
on copper alloy [156]. Consequently, the major concern in these packages is the large
CTE mismatch between the substrate material and SiC chip. Depending on the pad
metallization, often gold or aluminum wire bonding is used for electrical interconnection
[30]. The reliability of the package is limited by cracks in the die-attach layers and wire
bonds lift-off during active and passive temperature cycling.
In this work, SiC Schottky diodes obtained from Infineon Technologies AG, were used.
The packaging scheme proposed in this thesis work consisted of an AlN DCB substrate,
Ag-sintered or Sn-Ag TLP bonded layer as die-attachment and AlX wire bonds as
electrical interconnects. The electrical characterization of the assembled SiC diodes,
137
Chapter 8
Discussion and Conclusions
using both Ag-sintering and TLP bonding, showed improved thermal dissipation
behavior indicated by low on-state resistances during pulsed (tpls = 0.1 ms) and
continuous IV-measurements. The high forward currents, i.e. 100 A during pulsed
(tpls = 0.1 ms) IV-measurements and 36 A during continuous IV-measurements, were
obtained. Both sintered and TLP bonded diodes exhibited break down voltages in the
range of 740 – 760 V.
The sintered-Ag layer can survive high-temperatures similar to the bulk silver 961 ºC
[4], while, foil-based Sn-Ag TLP bonded joint survived high temperatures up to 480 ºC.
Both Ag-sintered layer and SnAg TLP joint intermetallics were found to be ductile than
brittle Cu-Sn intermetallics. The E-moduli for both die-attachments were in the range
from 40 – 60 GPa. Consequently, the thermal and thermo-mechanical stresses can be
significantly reduced in the package. The mounting of SiC chips on AlN DCB offers
better CTE matching as compared to Cu lead frames. Due to excellent electrical and
thermal properties of die-attachments the high power-per-unit-area [PA = (Vd × Id)/A] up
to 70 W/mm2 could be achieved in the SiC assembly. The AlX wire showed similar
electrical properties in comparison with Al, while it could survive temperatures up to
300 ºC. The reliability of the SiC assembly was improved by using the Ag-sintering and
Sn-Ag TLP bonding, as both die-attachments show high passive and active power
cycling capabilities. The crack propagation rates in the Ag-sintered and TLP bonded
layers could be modelled with Paris’ Law. Consequently, the lifetime modelling using
such a packaging scheme is possible for other SiC and Si devices as well.
8.4
GaN-on-Si HEMT Packaging
The GaN-on-Si high electron mobility transistor (HEMTs) have increasingly become an
attractive choice due to their cost-effectiveness and their ability to be fabricated on
large-diameter Si wafers. So far the GaN-on-Si HEMTs have been assembled in a TO220 package [127], which consists of a copper substrate, an Au80Sn20 die-attach layer
and
interconnections
based
on
gold
wires
(ϕ = 25 µm)
or
ribbon
bonds (A =12 µm ×100 µm). One of the major concerns in this package was the CTE
mismatch, as GaN-on-Si (2.6 ppm/K) HEMT is directly mounted on the copper
(16.5 ppm/K) substrate. Consequently, large thermo-mechanical stresses are developed
in the package during the device operation at high junction temperature swings ∆Tj.
Furthermore, high processing-temperatures during soldering process induce additional
thermal stresses in the package. The Au80Sn20 eutectic solder has high E-modulus and
very often the stresses are transferred to the mounted chips. All these factor reduce the
life time and reliability of the package. These devices are aimed for their use in highpower and high-frequency applications, where high power-reflections can possibly occur
due to sudden impedance mismatch. As a result, instantaneous high-temperature
(500 ºC) peaks, which last from few micro seconds to milliseconds, can possibly melt
the die-attach layer (Tmelt =280 ºC). Moreover, the cost of AuSn solder is relatively high.
Cree [157] also has reported on using AuSn eutectic solder for mounting of GaN
138
8.4
GaN-on-Si HEMT Packaging
HEMTs. For substrates and base plates, copper-tungsten and copper-molybdenumcopper based materials have been used. These materials have thermal conductivities in
the range from 190 – 200 W/mK, whereas, both possess the CTE in the range from 8 –
10 ppm/K.
The goal of the research was to improve the high-temperature stability, to minimize the
thermal and thermo-mechanical stresses and simultaneously achieving a good thermal
dissipation behavior. The packaging scheme proposed in this thesis work consists of an
AlN DCB substrate, Ag-sintering or Sn-Ag TLP bonding as a die-attachment layer, thin
gold and palladium bond wires (ϕ = 50 µm). Additionally, the Ag-sintering and TLP
bonding can used to make substrate-to-base plate connections. The use of AlN DCBs
(7 ppm/K) greatly reduced the CTE mismatch between the GaN-on-Si (2.6 ppm/K)
HEMTs. Moreover, the thermal conductivity (λ =180 W/mK) of AlN is fairly high.
Hence, the thermal dissipation behavior is not greatly compromised in comparison with
using copper. Both Ag-sintering and Sn-Ag TLP bonding have proven to be stable up to
961 ºC and 480 ºC respectively. Moreover, they induce relatively low thermal and
thermo-mechanical stresses. The thermal conductivity of both die-attachments is higher
than the AuSn solder, which greatly improves the thermal dissipation behavior. The
material costs as compared to Au-based solutions are less.
GaN-on-Si HEMTs in this research work were provided by Fraunhofer IAF Freiburg.
These devices are capable of delivering high currents above 70 A measured during
pulsed (tpls = 100 µs) IV-characteristics and above 35 A during continuous IVcharacteristics. In addition, they exhibit breakdown voltages up to 900 V. In order to
take advantage of their excellent electrical characteristics, the assembly techniques have
been proposed in this work, which overcome the discrepancies of existing technologies.
A systematic electrical characterization of on-wafer GaN-on-Si HEMTs to the final
assemblies revealed a significant improvement in the thermal dissipation behavior of the
devices as indicated by decrease in on-state resistance at low and high power levels. It
was found that Si-wafer thinning from 675 µm to 150 µm is necessary to avoid the selfheating effects. The thermal resistance of complete assemblies for both Ag-sintered and
TLP bonded HEMTs were low, thereby indicating good thermal dissipation behavior.
The die-attach layers in both cases were uniform and void free, as indicated by x-ray
inspection. The surface temperature of the active HEMTs were measured using the IRthermography and using a mounted Pt-1000 sensor. An important correlation was made
between the surface temperature (Ts) and the actual channel temperature (Tj) measured
by micro-Raman Spectroscopy. It was found that actual junction temperatures are 50 %
higher than those present on the chip’s surface. The assembled HEMTs were subjected
to power cycling tests with powers as high as 130 W (Ids = 20 A, Ids = 6.5V). The surface
temperatures were measured up to 145 ºC. From correlation with Raman measurements,
the channel temperatures up to 225 ºC were expected. At a surface temperature swing of
120 K, the devices failed above 33000 cycles (ton = 3 sec, toff = 3.5 sec). The failures
were indicated by increased gate currents above 50 mA and above. But there were no
139
Chapter 8
Discussion and Conclusions
considerable assembly failures as indicated by x-ray inspection and metallographic
cross-sections.
The commercially available discrete package components, consisting of an AlN DCB
substrate, the copper interconnects and a copper base plate, were obtained from
Arkansas Power Electronics International (APEI). The chip/substrate, Cuinterconnect/substrate and substrate/based plate attachments were realized using Agsintering and foil-based SnAg TLP bonding. The crack propagation rates in the novel
attachments can be modelled with Paris’s Law. Consequently, the lifetime prediction of
the new package is possible. The electrical interconnections in the new scheme were
made using gold wire bonds. Such a scheme can be used for other GaN as well as the Si
power devices.
8.5
Conclusions
In comparison with current state-of-the-art die-attachments, both Ag-sintering and new
foil based SnAg TLP bonding were found to be suitable die-attachment methods for
mounting of SiC and GaN devices. Both methods can also be applied to mount the
current Si-based power devices. Both die-attachments showed excellent electrical and
thermal properties. The die-attach materials can withstand temperatures up to 480 ºC and
above. Moreover, they exhibit good passive and active temperature cycling reliability.
The fatigue in the die-attach layers can be modelled with the lifetime models such as
Paris’ Law. Both die-attachments can act as suitable candidates for their implementation
in industrial processes.
For electrical interconnection of GaN HEMTs, the Au (ϕ = 50 µm) wire bonds showed
better current carrying capabilities at high-power levels as compared to Pd (ϕ = 50 µm)
wire bonds. The increased electrical resistivity of Pd at high-temperatures limits highcurrent densities through the wire bonds. For SiC Schottky diodes, the novel aluminum
alloy “AlX” (ϕ = 300 µm) can be used as an alternative material instead of Al for hightemperature applications up to 300 ºC. It exhibits similar electrical characteristics as Al,
while, it’s bondability on gold surface is superior. Moreover, its power cycling
capability is equivalent to pure Al.
With the use of Ag-sintering and foil-based TLP bonding, the excellent electrical
characteristics of GaN-on-Si HEMTs and SiC Schottky diodes can be achieved. The dieattachments are suitable for both lateral GaN-on-Si HEMTs and vertical SiC Schottky
diodes. With better thermal dissipation behavior of both die-attachments, high powerlevels are achieved in these devices. The package high-temperature stability and
reliability can be increased by realizing both chip/substrate and substrate/base-plate
connections with Ag-sintering and TLP bonding. Furthermore, better CTE matching
realized by using AlN DCB substrates decreases the thermal and thermo-mechanical
stresses, thereby increasing the lifetime of the assemblies.
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Journal
1. A. A. Bajwa, Y. Qin, R. Reiner, R. Quay and J. Wilde “Assembly and packaging
technologies for high-temperature and high-power GaN Devices,” IEEE
Transactions on Components Packaging and Manufacturing Technologies, vol. 5,
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plasma polymerized films on the adhesion of Parylene-C to substrates”, Journal of
Plasma Processes and Polymers, vol. 10, no. 12, pp. 1081-1089, 2013.
Conference
1. A. A. Bajwa, R. Zeiser and J. Wilde, "Process optimization and characterization of
a novel micro-scaled silver sintering paste as a die attach material for high
temperature high power semiconductor devices,” in Proc. 36th IEEE International
Spring Seminar on Electronics Technology (ISSE), May. 2013, pp. 53-58.
2. A. A. Bajwa, Y. Y. Qin, R. Zeiser, J. Wilde, “Foil based transient liquid phase
bonding as a die-attachment method for high temperature devices,” in Proc. 8th
International Conference on Integrated Power Electronic Systems (CIPS), Feb.
2014, pp. 359-364.
3. A. A. Bajwa, Y. Qin, J. Wilde, R. Reiner, R. Waltereit, R. Quay, “ Assembly and
packaging technologies for high-temperature and high-power GaN HEMTs,” in
Proc. 64th IEEE Electronics Components and Technology Conference (ECTC),
May. 2014, pp. 2181-2188.
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4. E. Möller, A. A. Bajwa, E. Rastjagaev, J. Wilde, “Comparison of new dieattachment technologies for power electronic assemblies,” in Proc. 64th IEEE
Electronics Components and Technology Conference (ECTC), May. 2014, pp.
1707-1713.
5. A. A. Bajwa, E. Moeller, J. Wilde, “Die-attachment technologies for hightemperature applications of Si and SiC devices,” in Proc. 65th IEEE Electronics
Components and Technology Conference (ECTC), May. 2015, pp. 2168-2174.
6. E. Möller, A. A. Bajwa, J. Wilde, “Vergleich alternativer Verbindungstechniken für
leistungselektronische Bauelemente”, 2014 IMAPS Herbskonferenz München.
7. E. Möller, A. A. Bajwa, J. Wilde, “Performance-Vergleich von TLP-Bonding,
Sintern, Kleben und Löten”, DVS-Tagung, Weichlöten 2015, DVS-Berichte Band
310, pp. 121-128, March, 2015, Hanau.
8. E. Möller, A. A. Bajwa, J. Wilde, “Niedertemperatur-Bondverfahren für thermischelektrische Hochleistungssysteme”, submitted paper in MST Kongress , October 2628, 2015, Karlsruhe, Germany. (Paper ID: 1570104037).
9. A. A. Bajwa, J. Wilde, “Reliability of Ag-Sintering and Sn-Ag TLP-bonding for
mounting of SiC and GaN Devices,” submitted abstract in 9th CIPS, March 2016,
Nuremberg, Germany. (Paper ID: 1570173725).
10. D. Zeniieh, A. Bajwa, F. Olcaytug, G. Urban, “Parylene-C thin film for
biocompatible encapsulations with very strong adhesion and super barrier
properties”, in Proc. 21st International Symposium on Plasma Chemistry (ISPC),
August, 2013, pp. 1-4.
156