IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 22, NO. 4, OCTOBER 2007
2457
PLL-Less Active Power Filter Based on One-Cycle
Control for Compensating Unbalanced Loads in
Three-Phase Four-Wire System
Sachine Hirve, Kishore Chatterjee, B. G. Fernandes, M. Imayavaramban, and Suman Dwari
Abstract—In this paper, a shunt active power filter (APF) based
on unified constant frequency integration or one-cycle control [1]
for compensating unbalanced loads in a three-phase four-wire
system is explored. The APF provides compensation currents in
such a way that the utility supplies only the balanced fundamental
current at unity power factor, even if the load draws reactive and
harmonic currents. The scheme neither requires the service of a
phase-locked loop nor requires to sense the utility voltages. This
makes the scheme insensitive to the distortions that are generally
present in the utility voltages. First, the one-cycle control technique
is applied to a topology involving a four-leg converter for the proof
of concept. Then it is utilized to control a conventional three-leg
converter having a split-capacitor dc link. The effectiveness and
the viability of the schemes are demonstrated through detailed
simulation and experimental verification.
Index Terms—Active power filter, load compensation, one-cycle
control, resistance emulation, three-phase four-wire system.
I. INTRODUCTION
O
VER the years, there has been a continuous proliferation
of nonlinear type of loads due to intensive use of power
electronic control in all branches of industry as well as from
general consumers of electric energy. As a result, the utility
supplying these loads has to provide large reactive volt-amperes. Also, the utility gets polluted by harmonics generated
by the load. The punitive tariff levied by utilities against excessive var and the threat of stricter harmonic standards have
led to extensive research in the field of compensation. The basic
requirement of the compensation process involves precise and
continuous reactive volt-ampere control having fast response
time, avoidance of resonances created by peripheral low-frequency current sources, and the on-line elimination of the effect
of load harmonics. To satisfy the above criterion, the traditional
methods of compensation consisting of a switched capacitor or
fixed capacitor and phase controlled reactor coupled with passive filters have been increasingly replaced by new converter
based approaches, known as STATCOM.
Manuscript received June 2, 2005; revised July 21, 2006. This paper was presented in part at the 11th IEEE International Conference on Harmonics and
Quality of Power, Lake Placid, NY, Sept. 12-15, 2004. Paper no. TPWRD00332-2005.
S. Hirve is with SoftDel Systems, Mumbai, India.
K. Chatterjee, B. G. Fernandes, M. Imayavaramban, and S. Dwari are with
the Indian Institue of Technology Bombay, Electrical Engineering Department,
Bombay, India (e-mail: kishore@ee.iitb.ac.in).
Digital Object Identifier 10.1109/TPWRD.2007.893450
If the primary objective of the STATCOM is to compensate
for the load or harmonics present in the utility voltages, it is
popularly known as the active power filter (APF) [2]. The dc
to ac converter of the STATCOM can be either manipulated as
a controlled current source or as a controlled pulsewidth modulation (PWM) voltage source. Operation of the converter as
a controlled PWM voltage source is generally not preferred for
applications involving load compensation. This is due to the fact
that such schemes based on indirect current control technique
have a poor transient response [3], [4]. Therefore for these applications, the dc to ac converter of the STATCOM is manipulated as a controlled current source. Typical control methods
are linear current control, digital deadbeat control and hysteresis
current control [5], [6]. However, in the aforementioned cases,
the service of a phase-locked loop (PLL) is required either to
generate the reference current template or to synchronize the
PWM voltage waveform with that of the utility. Presence of the
PLL reduces the robustness of the controller. Although schemes
based on instantaneous reactive power theory [7] do not require
the service of a PLL, they fail to perform if the utility voltages
are distorted and/or unbalanced [8]. Moreover, schemes based
on p-q theory and it’s modifications require complicated control
structure for implementation.
Schemes based on one-cycle control (OCC) do not require
the service of PLL. This feature makes them robust and hence
have acheived considerable significance [9]–[12]. Further, in
one-cycle controlled converters, the semiconductor devices
are operated with constant switching frequency, which is an
added attraction to employ them for medium and high-power
applications. As OCC is basically a current control scheme but
with constant switching frequency, the harmonic spectrum of
the current is superior compared to current controlled schemes
with variable switching frequency. In addition to these, the
control structure is considerably simple and the core control
structure does not require the service of intelligent controller.
APF based on OCC has been mainly utilized for compensating
single phase and three-phase three-wire loads. An effort has
been made in [12] to utilize OCC for compensating three-phase
four-wire loads. However in this case, a four-legged converter
involving eight devices has been used. Moreover, it requires to
sense the utility voltages in order to derive the sector information. This increases the cost as well as control complexity of the
APF. In an effort to overcome aforementioned limitations, OCC
technique has been employed to control the three legged converter based APF having split capacitor at the dc link proposed
in [13]. The removal of a converter leg not only reduces the
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IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 22, NO. 4, OCTOBER 2007
cost but also simplifies the control structure, thereby enhancing
the reliability of the scheme. In this paper, a four-leg converter
based APF negotiating three-phase four- wire nonlinear load
is first analyzed so as to ascertain the viability of OCC in
compensating three-phase four-wire loads. Then the standard
three legged converter based APF having split dc link capacitor
utilizing one-cycle controller is developed. The viability of the
scheme is verified through detailed simulation and experimental
studies.
II. ONE-CYCLE CONTROLLED APF USING
FOUR-LEG CONVERTER
The schematic circuit diagram of an APF based on OCC compensating loads in a three-phase, four-wire system is shown in
Fig. 1. The fourth leg of the converter is connected to the neutral point of the system through a filter inductor to control the
neutral current drawn from the source. The duty ratio of the conto
are varied within a power cycle in such
verter switches
a way that the combination of load and compensator appears as
a balanced resistive load to the utility. The control equations for
modulating duty ratios of the switches of the three limbs of the
converter as given in [1] are as follows:
(1)
(2)
(3)
where
, and
are the line currents drawn from the
is the gain of the current sensors and
is the output
source,
of the PI controller. Input to the PI controller is the difference
between the reference and the actual dc link voltages. Hence
contains the information regarding the
the magnitude of
magnitude of real component of load current. The duty ratios of
the lower switches associated with phase a, b, and c are
and respectively. This implies that
remains ON for
seconds, while
for
seconds; where
is the switching frequency of the devices. In order to realize
(1), (2) and (3), the sensed source currents are compared with a
.
is generated
sawtooth waveform, , having amplitude
through a re-settable integrator having time
by integrating
constant equal to . The schematic control block diagram for
the APF is also shown in Fig 1. The relationship between
and
is maintained as
(4)
It should be noted that the switching frequency of the devices is the same as that of the frequency of the sawtooth waveform which is
. This control philosophy and its implementation issues are covered in [1], [9]. The amplitude of the
, and , depends on the amplitude of
source currents,
the sawtooth waveform, which is same for all the three phases.
Hence, the APF tries to balance the source currents even if the
three-phase load is having zero sequence currents. The presence
and
to
of zero sequence current makes the sum of
be nonzero. This sum can be nonzero only if the fourth converter limb is connected to the neutral point as shown in Fig. 1.
, is made equal to
If the current flowing through this limb,
, then current in source neutral reduces to zero. To
Fig. 1. APF for three-phase four-wire system using hysteresis current control
for neutral current compensation.
realize this, the load neutral current is sensed and the fourth
limb APF current is made to follow it within a hysteresis band.
to
remains the same as that folThe control algorithm for
lowed in one-cycle controlled three-phase three-wire APF [9].
As the zero sequence current component of the load finds a path
through the fourth leg of the APF converter, the current flowing
through the supply neutral conductor, , becomes effectively
zero.
III. SIMULATED PERFORMANCE
In order to predict the performance of the APF using a
four-leg converter, detailed simulation studies on MATLAB/
Simulink platform are carried out. A 400-V, 50-Hz three-phase
four-wire system is chosen for this study. A full bridge diode
rectifier feeding a load of 11 and 20 mH is connected between
kVA load is connected
phase-a and neutral. A
between phase-b and neutral of the system. In addition to this, a
13 A current source having a frequency of 150 Hz is connected
in parallel to this load. To phase-c, a parallel combination of
kVA and 13 A current source having frequency
of 150 Hz is connected. The reference dc link voltage of the
converter is maintained at 700 V and the frequency of sawtooth
waveform is chosen to be 10 kHz. Fig. 2 shows phase-a utility
voltage and the currents in three phases when the APF is not
in operation. Fig. 3 shows the same set of currents when the
APF is compensating the load. It can be inferred from Figs. 2
and 3 that the APF is able to compensate a highly unbalanced
and nonlinear three-phase load. Fig. 4 depicts phase-a voltage,
load neutral current, current in the fourth leg of the APF and
source neutral current. It can be seen that the magnitude of
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HIRVE et al.: PLL-LESS APF BASED ON OCC FOR COMPENSATING UNBALANCED LOADS
Fig. 2. Simulated results of four-leg converter: Converter is out of the circuit.
(a) Phase-A utility voltage. (b) Phase-A source current. (c) Phase-B source current. (d) Phase-C source current.
Fig. 3. Simulated results of four-leg converter: Converter is in operation. (a)
Phase-A utility voltage. (b) Phase-A source current. (c) Phase-B source current.
(d) Phase-C source current.
the fourth leg current of the converter is almost the same as
that of the load neutral current but are in phase opposition. As
a result, the source neutral current has become almost zero
as depicted in Fig 4(d). The actual dc link capacitor voltage
and the reference dc link capacitor voltage along with phase-a
voltage are presented in Fig. 5.
IV. SPLIT-CAPACITOR TOPOLOGY
2459
Fig. 4. Simulated results of four-leg converter: Converter is in operation. (a)
Phase-A utility voltage. (b) Load neutral current. (c) APF neutral current. (d)
Source neutral current.
Fig. 5. Simulated results of four-leg converter: Converter is in operation. (a)
Phase-A utility voltage. (b) Reference dc link voltage (V ). (c) Sensed dc link
voltage (V ).
reduced by two if a split-capacitor topology [13] is adopted for
the converter configuration as depicted in Fig. 6. This configuration is obtained by removing the fourth leg of the converter
and replacing the dc link capacitor by two capacitors connected
in series. The mid-point of these capacitors is connected to
the system neutral point. Lower device count along with its
allied gate driver circuitry will lead to reduced cost, size, and
improved system reliability.
If three-phase load is drawing unbalanced currents having
zero sequence component, , then
The number of semiconductor devices required for the
four-leg APF configuration discussed in Section II can be
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(5)
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IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 22, NO. 4, OCTOBER 2007
The above analysis shows that while balancing the three line
and , the fourth line of the APF, connected
currents,
between the mid-point of the dc link capacitor and the supply
neutral, supplies the zero sequence current component required
by the load. As a result, the source neutral conductor is relieved
of carrying the zero sequence current.
V. CONTROL PHILOSOPHY
Due to the involvement of the split capacitor in the converter
configuration and the pertinent connection of the split-capacitor
mid point to the supply neutral, the control equation needs to be
slightly modified from that of [9]. Assuming the switching frequency to be much higher than the line frequency, the switching
cycle average voltages at nodes A, B and C referred to the midpoint of the capacitor N can be written as
(13)
Fig. 6. APF utilizing split-capacitor topology for three-phase four-wire system.
It has already been discussed in Section II that as the amplitude of the sawtooth wave, , would be maintained same for
all the three phases, the amplitude of the three source currents,
and , are same and they are balanced, therefore
where
, and are the duty ratios for switches
, and
, respectively. The duty ratios for the upper three switches
and
are
and
respectively.
The voltages across the upper and lower dc link capacitors, are
and
respectively.
The voltages at nodes A, B and C referred to the mid-point of
the dc link capacitor, N, can be represented as phasors in terms
of utility voltages as
(6)
Applying KCL at the Gaussian curve, G1
(7)
therefore
(14)
where
, and
are the filter inductances and is the angular frequency of the supply. As these filter inductances are
small, the line frequency voltage drop across them can be neglected for the sake of analysis [9]. Hence, (14) can be approximated as
(8)
(15)
Again applying KCL at the Gaussian curve, G2
(9)
In time domain
Now
(10)
hence
(11)
(16)
where is the rms value of line to neutral voltage. In order to
achieve unity power factor, the control goal to be achieved is
therefore
(12)
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(17)
HIRVE et al.: PLL-LESS APF BASED ON OCC FOR COMPENSATING UNBALANCED LOADS
2461
where
is the emulated resistance. Combination of (13), (16),
and (17) yields
(18)
Now
(19)
Considering
defining
to be the gain of the current sensor and
(20)
and
(21)
equation set (18) can be written as
Fig. 7. Simulated results of active filter using split-capacitor topology: Filter
is out of the circuit. (a) Phase-A utility voltage. (b) Phase-A source current. (c)
Phase-B source current. (d) Phase-C source current.
(22)
and
are estimated by using two PI conThe voltages
and sensed
is
trollers PI-1 and PI-2. The error between
, while
is obtained from the
used by PI-1 to estimate
error existing between
and sensed
. Having estimated
and
, the above set of equations can be implemented
using a resettable integrator, a free running clock, three comparators and three flip flops as shown in Fig. 6. The resettable
.
integrator having an integration time constant is fed with
The rising edge of the free running clock, having a time period
, is used to turn-on all the lower half switches,
and
of the converter; and hence the three currents,
and
start increasing. The rising edge of the same clock is also
used to reset the integrator. Therefore from this time onwards,
. The output of the integrator
the integrator starts integrating
is subtracted from the output of PI-1 to obtain . The respective sensed source currents are then compared with . Whenever a particular phase current becomes higher than , the lower
switch of that particular phase is turned off and the upper switch
is turned on. The instants of switching transition from lower to
upper switches in three phases can therefore be represented by
the following set of equations:
Fig. 8. Simulated results of active filter using split-capacitor topology: Filter is
in operation. (a) Phase-A utility voltage. (b) Phase-A source current. (c) Phase-B
source current. (d) Phase-C source current.
VI. SIMULATED PERFORMANCE
(23)
Choosing
to be equal to
and noting that
remains
essentially constant over a switching time period, (23) actually
realizes (22).
Detailed simulation studies on MATLAB/Simulink platform
are carried out to obtain the performance characteristics of the
APF based on split-capacitor topology. Input to the APF and the
type of load chosen are the same as that of three-phase four-wire
system. The magnitude of the reference dc link voltage and
are kept at 700 V and 350 V, respectively.
voltage across
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IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 22, NO. 4, OCTOBER 2007
TABLE I
HARMONIC CONTENT OF THE COMPENSATED SOURCE CURRENT
Fig. 11. Experimental results of active filter using split-capacitor topology:
Filter is out of the circuit [Trace1]: Phase-A Supply Voltage, 175 V/div [Trace2]:
Phase-A source Current, 2 A/div [Trace3]: Phase-B source current, 2 A/div
[Trace4]: Phase-C source current, 2 A/div. x-axis scale: 10 ms/div. [The topmost waveform is referred to as Trace1 and the last waveform at the bottom is
referred to as Trace4].
Fig. 9. Simulated results of active filter using split-capacitor topology: Filter
is in operation. (a) Phase-A utility voltage. (b) Load neutral current. (c) Current
flowing through the conductor connected between the mid point of the DC link
and the system neutral. (d) Source neutral current.
Fig. 12. Experimental results of active filter using split-capacitor topology:
Filter is in operation [Trace1]: Phase-A Supply voltage, 175 V/div [Trace2]:
Phase-A source Current, 2 A/div [Trace3]: Phase-B source current, 2 A/div
[Trace4]: Phase-C source current, 2 A/div. x-axis scale: 10 ms/div. (The topmost waveform is referred to as Trace1 and the last waveform at the bottom is
referred to as Trace4).
Fig. 10. Simulated results of active filter using split-capacitor topology:
Filter is in operation. (a) Phase-A utility voltage. (b) Total dc link capacitor
voltage(V ). (c) Voltage across the upper split capacitor (C ).
Fig. 7 shows the phase-a utility voltage and the source currents of the three phases when the APF is not in operation. The
same set of currents along with the phase-a utility voltage when
the APF is in operation are shown in Fig. 8. The magnitude
of the low order harmonics present in the three phases of the
compensated source current are provided in Table I. By comparing Figs. 7 and 8 alongwith the harmonic contents provided
in Table I, it can be inferred that the proposed compensator is
able to effectively compensate highly unbalanced and nonlinear
three-phase load. Fig. 9 depicts the phase-a voltage, load neutral
current, and current flowing through the conductor connected
between the mid-point of the dc link split capacitors and the
and the load neutral cursource neutral. It can be seen that
rent are almost of the same magnitude but they are in phase opposition. This leads to the reduction in the source neutral current to almost zero, as shown in Fig 9(d). Total dc link capacitor
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HIRVE et al.: PLL-LESS APF BASED ON OCC FOR COMPENSATING UNBALANCED LOADS
2463
Fig. 13. Experimental results of active filter using split-capacitor topology:
Filter is in operation [Trace1]: Phase-B Supply voltage, 175 V/div [Trace2]:
Load neutral current, 1.75 A/div [Trace3]: Current flowing through the conductor connected between the mid point of the DC link and the system neutral
1.75 A/div [Trace4]: Source neutral current 1.75 A/div. x-axis scale: 10 ms/div.
[The topmost waveform is referred to as Trace1 and the last waveform at the
bottom is referred to as Trace4].
Fig. 14. Experimental results of active filter using split-capacitor topology:
Filter is in operation [Trace1]: Phase-B supply voltage, 175 V/div [Trace2]:
Total dc link capacitor voltage(V ), 35 V/div [Trace3]: Voltage across the
upper split capacitor (C ), 35 V/div. x-axis scale: 10 ms/div. [The topmost
waveform is referred to as Trace1 and the last waveform at the bottom is referred to as Trace3].
voltage and upper half split-capacitor dc link voltage along with
the phase-a utility voltage are shown in Fig. 10. This shows that
equal voltages are impressed across each of the dc link split capacitors.
Fig. 15. Harmonic spectrum of the source currents without APF in service [a]
Phase-A source current [b] Phase-B source current [c] Phase-C source current.
Vertical axis: 20 db/div, zero level is located at 1 div from top, Horizontal axis:
500 Hz/div.
VII. EXPERIMENTAL RESULTS
In order to confirm the viability and effectiveness of the
scheme, detailed experimental studies are carried out. An
IGBT-based scaled laboratory prototype for the split-capacitor
converter topology is developed for the purpose. The clock
frequency and hence the switching frequency of the devices
is maintained at 10 kHz. A three-phase nonlinear unbalanced
load is connected to the utility. Fig. 11 shows phase-a utility
voltage and the three- phase source currents when the APF
is not in operation. The same set of currents along with the
phase-a source voltage when APF is in operation are shown
in Fig. 12. By comparing Figs. 11 and 12, it can be inferred
that the compensator is able to effectively compensate highly
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IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 22, NO. 4, OCTOBER 2007
phase-b utility voltage is shown in Fig. 14. This shows that
equal voltages are impressed across each of the dc link split
capacitors. Fig. 15 shows the harmonic spectrum of the source
currents of phase a, b and c while the APF is not in service.
Harmonic spectrum of the same set of currents while the APF
is in service are depicted in Fig. 16. By comparing Figs. 15 and
16, it can be inferred that the APF is able to balance a highly
unbalanced load, and at the same time is also able to reduce
the lower order harmonic components of the source currents
considerably.
VIII. CONCLUSION
In this paper, APFs using OCC to compensate unbalanced
nonlinear load in three-phase four-wire system are explored. In
order to validate the proof of the concept, a four-leg converter
is first used in order to realize whether the APF is suitable for
three-phase four-wire system. The semiconductor devices of the
fourth leg of the converter are operated in hysteresis current
control mode to control the current through source neutral. In
an effort to reduce the number of devices involved, a standard
three-phase bridge converter topology involving six semiconductor devices is employed. This eventually leads to reduced
cost and size while imparting enhanced system reliability. The
performance characteristics of the scheme are evaluated through
detailed simulation studies. A scaled laboratory prototype of the
APF system is developed. The viability of the system is demonstrated through detailed experimental validation.
REFERENCES
Fig. 16. Harmonic spectrum of the source currents with APF in service [a]
Phase-A source current [b] Phase-B source current [c] Phase-C source current.
Vertical axis: 20 db/div, zero level is located at 1 div from top, Horizontal axis:
500 Hz/div.
unbalanced and nonlinear three-phase loads. Fig. 13 depicts
, and the source neuphase-b voltage, load neutral current,
tral current. It can be seen that
and load neutral current are
almost of the same magnitude but they are in phase opposition.
This leads to the reduction in source neutral current, as can
be verified from trace 4 of Fig. 13. The total dc link voltage
and the voltage across the upper split capacitor along with the
[1] K. M. Smedley, L. Zhou, and C. Qiao, “Unified constant-frequency
integration control of active power filters-steady-state and dynamics,”
IEEE Trans. Power Electron., vol. PE-16, pp. 428–436, May 2001.
[2] N. G. Hingorani and L. Gyugi, Understanding Facts. Piscataway, NJ:
IEEE Press, 2000.
[3] L. T. Moran, P. D. Ziogas, and G. Joos, “Analysis and design of a threephase synchronous solid-state var compensator,” IEEE Trans. Ind. Applic., vol. IA-25, pp. 598–608, Jul./Aug. 1989.
[4] L. T. Moran, P. D. Ziogas, and G. Joos, “Performance analysis of a
PWM inverter var compensator,” IEEE Trans. Power Electron., vol.
PE-6, pp. 380–391, Jul. 1991.
[5] S. Buso, L. Malesani, and G. Joos, “Comparison of current control techniques for active filter applications,” IEEE Trans. Ind. Electron., vol.
45, pp. 722–729, Oct. 1998.
[6] K. Chatterjee, B. G. Fernades, and G. K. Dubey, “An instantaneous
reactive volt-ampere compensator and harmonic suppressor system,”
IEEE Trans. Power Electron., vol. PE-14, pp. 381–392, Mar. 1999.
[7] H. Agaki, Y. Kanazawa, and A. Nabae, “Instantaneous reactive power
compensators comprising switching devices without energy storage
components,” IEEE Trans. Ind. Appl., vol. IA-20, pp. 625–630, May/
Jun. 1984.
[8] S. Bhattacharya and D. Divan, “Synchronous frame based controller
implementation for a hybrid series active filter system,” Proc. IEEE/IAS
Annu. Meeting, pp. 2531–2540, 1995.
[9] C. Qiao and K. Smedley, “Three-phase bipolar mode active power filters,” IEEE Trans. Ind. Appl., vol. IA-38, pp. 149–158, Jan./Feb. 2002.
[10] G. Chen and K. M. Smedley, “Steady-state and dynamic study of onecycle controlled three-phase active power filters,” IEEE Trans. Ind.
Appl., vol. 52, no. 2, pp. 355–362, Apr. 2005.
[11] L. Zhou and K. M. Smedley, “Unified constant-frequency integration
control of active power,” APEC, vol. 1, no. 1, pp. 406–412, Feb. 2000.
[12] K. M. Smedley, G. Chen, and Y. Chen, “Three-phase four-leg active
power quality conditioner without references calculation,” APEC, vol.
1, pp. 587–593, Feb. 2004.
[13] C. A. Quinn, N. Mohan, and H. Mehta, “Acitive filtering of harmonic
currents in three-phase, four-wire systems with three-phase and singlephase nonlinear loads,” APEC, pp. 829–836, Feb. 1992.
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on December 31, 2008 at 01:31 from IEEE Xplore. Restrictions apply.
HIRVE et al.: PLL-LESS APF BASED ON OCC FOR COMPENSATING UNBALANCED LOADS
Sachine Hirve received the M.Tech. degree from the Indian Institute of Technology, Bombay, in 2004.
He is currently with in SoftDel Systems, Mumbai, India.
Kishore Chatterjee was born in Calcutta, India,
in 1967. He received the B.E. and M.E. degrees in
power electronics from M.A.C.T., Bhopal, India, and
Bengal Engineering College in 1990 and 1992, respectively, and the Ph.D. degree in power electronics
from the Indian Institute of Technology, Kanpur, in
1998.
From 1997 to 1998, he was a Senior Research
Associate at the Indian Institute of Technology,
Kanpur, where he was involved with a project on
power factor correction and active power filtering,
which was being sponsored by the Central Board of Irrigation and Power, India.
He was an Assistant Professor in the Department of Electrical Engineering,
Indian Institute of Technology, Bombay, since 1998 and has been as Associate
Professor there since 2005. His current research interests are modern var
compensators, active power filters, utility-friendly converter topologies, and
induction motor drives.
2465
M. Imayavaramban was born in Pondicherry, Tamil
Nadu, India, in 1977. He received the B.E. degree in
electrical and electronics engineering from the University of Madras, Madras, India, in 1999 and the
M.E. degree from Anna University, Chennai, India,
in 2004.
He is currently a Research Assistant with the Indian Institute of Technology, Bombay. His fields of
interest are direct ac-ac power conversion and power
electronics converters for reactive power compensation.
Suman Dwari received the M.Tech. degree from the
Indian Institute of Technology, Bombay, in 2003.
He then worked as Design Engineer and Senior
Design Engineer, respectively, at Hical Magnetics
Private Limited and Celectronix Power India Private
Limited. Currently, he is a Senior Research Assistant
in the Department of Electrical Engineering, Indian
Institute of Technology, Bombay. His research
interests include efficient high-frequency power
converters, power factor correction techniques,
active power filters, and high-performance ac drives.
B. G. Fernandes received the B.Tech. degree from
Mysore University, Mysore, India, in 1984, the
M.Tech. degree from the Indian Institute of Technology, Kharagpur, in 1989, and the Ph.D. degree
from the Indian Institute of Technology, Bombay, in
1993.
He then joined the Department of Electrical Engineering, Indian Institute of Technology, Kanpur, as an
Assistant Professor. In 1997, he joined Department
of Electrical Engineering, Indian Institute of Technology, Bombay, where he is currently an Associate
Professor. His current research interests are in permanent magnet machines,
high-performance ac drives, quasi-resonant link converter topologies, and power
electronic interfaces for nonconventional energy sources.
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