eGaN® FET DATASHEET
EPC2035
EPC2035 – Enhancement Mode Power Transistor
VDSS , 60 V
RDS(on) , 45 m
ID , 1 A
NEW PRODUCT
EFFICIENT POWER CONVERSION
HAL
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment
leveraging the infrastructure that has been developed over the last 55 years. GaN’s exceptionally
high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device
structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a
device that can handle tasks where very high switching frequency, and low on-time are beneficial
as well as those where on-state losses dominate.
EPC2035 eGaN® FETs are supplied only in
passivated die form with solder bumps
Die Size: 0.9 mm x 0.9 mm
Maximum Ratings
VDS
ID
VGS
TJ
TSTG
Drain-to-Source Voltage (Continuous)
60
Drain-to-Source Voltage (up to 10,000 5ms pulses at 125° C)
72
Continuous (TA = 25˚C, R θJA= 1600 ˚C/W)
1
Pulsed (25˚C, TPULSE = 300 µs)
24
Gate-to-Source Voltage
6
Gate-to-Source Voltage
-4
Operating Temperature
-40 to 150
Storage Temperature
-40 to 150
Applications
• High Speed DC-DC conversion
• Wireless Power Transfer
• High Frequency Hard-Switching and
Soft-Switching Circuits
• LiDAR/Pulsed Power Applications
V
A
Benefits
• Ultra High Efficiency
• Ultra Low RDS(on)
• Ultra low QG
• Ultra small footprint
V
˚C
www.epc-co.com/epc/Products/eGaNFETs/EPC2035.aspx
Static Characteristics (TJ= 25˚C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
60
TYP
MAX
UNIT
BVDSS
Drain-to-Source Voltage
VGS = 0 V, ID = 300 µA
IDSS
Drain Source Leakage
VDS = 48 V, VGS = 0 V
20
250
µA
Gate-to-Source Forward Leakage
VGS = 5 V
0.1
1
IGSS
Gate-to-Source Reverse Leakage
VGS = -4 V
VGS(TH)
Gate Threshold Voltage
VDS = VGS, ID = 0.8 mA
RDS(on)
Drain-Source On Resistance
VSD
Source-Drain Forward Voltage
VGS = 5 V, ID = 1 A
IS = 0.5 A, VGS = 0 V
0.8
V
20
250
mA
µA
1.4
2.5
V
35
45
mΩ
V
2
All measurements were done with substrate shorted to source.
Thermal Characteristics
TYP
UNIT
RθJC
Thermal Resistance, Junction to Case
6.5
˚C/W
RθJB
Thermal Resistance, Junction to Board
65
˚C/W
RθJA
Thermal Resistance, Junction to Ambient (Note 1)
100
˚C/W
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
| PAGE 1
eGaN® FET DATASHEET
EPC2035
Dynamic Characteristics (TJ= 25˚C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
95
115
60
90
3
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
2
RG
Gate Resistance
0.5
QG
Total Gate Charge
VDS = 30 V, VGS = 0 V
VDS = 30 V, VGS = 5 V, ID=1 A
QGS
Gate-to-Source Charge
QGD
Gate-to-Drain Charge
QG(TH)
Gate Charge at Threshold
QOSS
Output Charge
QRR
Source-Drain Recovery Charge
UNIT
pF
Ω
880
1150
250
VDS = 30 V, ID = 1 A
160
270
pC
170
VDS = 30 V, VGS = 0 V
2600
3900
0
All measurements were done with substrate shorted to source.
Figure 1: Typical Output Characteristics 25°C
VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V
15
20
ID – Drain Current (A)
20
ID – Drain Current (A)
Figure 2: Transfer Characteristics
10
5
0
15
5
0
0.5
1.0
1.5
2.0
2.5
0
3.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VGS – Gate-to-Source Voltage (V)
4.0
4.5
5.0
Figure 4: RDS(on) vs. VGS for Various Temperatures
Figure 3: RDS(on) vs. VGS for Various Drain Currents
140
140
ID = 0.5 A
ID = 1 A
ID = 1.5 A
ID = 2 A
120
100
RDS(on) – Drain-to-Source Resistance (mΩ)
RDS(on) – Drain-to-Source Resistance (mΩ)
VDS = 3 V
10
VDS – Drain-to-Source Voltage (V)
80
60
40
20
0
25˚C
125˚C
2.0
2.5
3.0
3.5
4.0
VGS – Gate-to-Source Voltage (V)
4.5
5.0
120
25˚C
125˚C
100
ID = 1 A
80
60
40
20
0
2.0
2.5
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
3.0
3.5
4.0
VGS – Gate-to-Source Voltage (V)
4.5
5.0
| PAGE 2
eGaN® FET DATASHEET
EPC2035
Figure 5b: Capacitance (Log Scale)
Figure 5a: Capacitance (Linear Scale)
160
140
Capacitance (pF)
120
Capacitance (pF)
100
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
100
80
60
10
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
1
40
20
0
0
10
20
30
40
50
0.1
60
0
10
20
30
40
50
60
VDS – Drain-to-Source Voltage (V)
VDS – Drain-to-Source Voltage (V)
Figure 6: Gate Charge
Figure 7: Reverse Drain-Source Characteristics
20
ID = 1 A
VDS = 30 V
4
ISD – Source-to-Drain Current (A)
VGS – Gate-to-Source Voltage (V)
5
3
2
1
0
0
0.5
0.4
0.6
0.8
QG – Gate Charge (nC)
15
10
5
0
1.0
Figure 8: Normalized On Resistance vs. Temperature
1.30
ID = 1 A
VGS = 5 V
Normalized Threshold Voltage
Normalized On-State Resistance RDS(on)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VSD – Source-to-Drain Voltage (V)
4.5
5.0
1.40
1.6
1.4
1.2
1.0
0.8
0
Figure 9: Normalized Threshold Voltage vs. Temperature
2.0
1.8
25˚C
125˚C
ID = 0.8 mA
1.20
1.10
1.00
0.90
0.80
0.70
0
25
50
75
100
TJ – Junction Temperature (°C)
125
150
0.60
0
25
50
75
100
TJ – Junction Temperature (°C)
125
150
All measurements were done with substrate shortened to source.
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
| PAGE 3
eGaN® FET DATASHEET
EPC2035
Figure 10: Gate Leakage Current
3.5
IG – Gate Current (mA)
3.0
25˚C
125˚C
2.5
2.0
1.5
1.0
0.5
0
0
1
2
3
4
5
VGS – Gate-to-Source Voltage (V)
6
Figure 11: Transient Thermal Response Curves
ZθJB, Normalized Thermal Impedance
Junction-to-Board
1 Duty Cycle:
0.5
0.1 0.1
0.05
0.02
0.01
0.01
PDM
t1
0.001
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
Single Pulse
0.0001
10-5
t2
10-4
10-3
10-2
10-1
1
10+1
tp, Rectangular Pulse Duration, seconds
ZθJB, Normalized Thermal Impedance
Junction-to-Case
1 Duty Cycle:
0.5
0.2
0.1
0.05
0.02
0.01
0.01
0.1
0.001
PDM
t1
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJG + TC
Single Pulse
0.0001
10-6
t2
10-5
10-4
10-3
10-2
10-1
1
tp, Rectangular Pulse Duration, seconds
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
| PAGE 4
eGaN® FET DATASHEET
EPC2035
Figure 12: Safe Operating Area
I D – Drain Current (A)
100
10
Limited by RDS(on)
Pulse Width
Pulse
100Width
ms
100 ms
10 ms
ms
10
ms
11100
ms
µs
1
100 µs
0.1
0.1
1
10
100
VDS - Drain-Source Voltage (V)
TAPE AND REEL CONFIGURATION
b
4mm pitch, 8mm wide tape on 7” reel
e
d
g
f
Loaded Tape Feed Direction
7” reel
YYY
c
AA
a
a
b
c (see note)
d
e
f (see note)
g
8.00
1.75
3.50
4.00
4.00
2.00
1.5
7.90
1.65
3.45
3.90
3.90
1.95
1.5
max
8.30
1.85
3.55
4.10
4.10
2.05
1.6
Gate
solder bump is
under this
corner
Die is placed into pocket
solder bump side down
(face side down)
EPC2035 (note 1)
Dimension (mm) target min
Die
orientation
dot
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
DIE MARKINGS
Die orientation dot
Gate Pad bump is
under this corner
AA
YYY
Part
Number
EPC2035
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
Laser Markings
Part #
Marking Line 1
Lot_Date Code
Marking line 2
AA
YYY
| PAGE 5
eGaN® FET DATASHEET
EPC2035
A
DIE OUTLINE
DIM
g
Solder Bump View
2
A
B
c
d
e
f
g
d
B
4
1
Pads 1 is Gate;
Pad 3 is Drain;
Pads 2, 4 are Source
3
c
930
930
450
450
240
240
229
815 Max
(625)
SEATING PLANE
900
The land pattern is solder mask defined
Solder mask is 10μm smaller per side than bump
190
X4
(measurements in µm)
MAX
900
900
450
450
225
225
208
165+/- 17
Side View
RECOMMENDED
LAND PATTERN
Nominal
870
870
450
450
210
210
187
f
e
MIN
Pads 1 is Gate;
1
3
Pad 3 is Drain;
450
900
Pads 2, 4 are Source
225
RECOMMENDED
STENCIL DRAWING
242
4
225
2
450
900
Recommended stencil should be 4mil (100µm) thick, must
be laser cut, openings per drawing.
200
Intended for use with SAC305 Type 3 solder, reference 88.5%
metals content.
225
450
Additional assembly resources available at
http://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx
225
450
900
R6
0
(measurements in µm)
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
U.S. Patents 8,350,294; 8,404,508; 8,431,960; 8,436,398; 8,785,974; 8,890,168; 8,969,918; 8,853,749; 8,823,012
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |
Information subject to
change without notice.
Revised April, 2015
| PAGE 6