DATASHEET
ADF-D1000/D1600/D1800/D2000
Dual 1.0 - 2.0 Gsps, 12-bit ADC FMC
The ADF-Dxx00 family of ADC receivers from DEG provide the
highest available conversion resolution for sample rates above
1 Gsps. Optimized to support Texas Instruments ADC12D1000,
ADC12D1600, ADC12D1800, and ADC12D2000 devices, the
ADF-Dxx00 family enables you to select the sample rate optimized
for your application and obtain the best dynamic performance
available today.
BENEFITS
 Achieve the best performance over 1 Gsps
 Rapidly build single board 1 - 4 channel
solutions
 Deliver rugged and conduction-cooled
systems
As a VITA 57-compliant FPGA Mezzanine Card (FMC), the
ADF-Dxx00 family converts two channels of up to 2.3 GHz analog
input bandwidth at 1.0 - 2.0 Gsps and 12-bit resolution, providing
direct coupling of unparalleled analog-to-digital conversion
capability with the PCIe/VME/VXS/VPX carrier board of your choice.
You can also use this FMC in single channel mode and sample up to
4 Gsps. The ADF-Dxx00 family and associated HDL firmware work
with both Altera® and Xilinx® FPGA processors.
Flexible, cost-effective solution
FEATURES
 Dual-channel 1.6 - 2.0 Gsps, 12-bit ADC
 Single-channel 2.0 - 4.0 Gsps, 12-bit ADC
 Works with carrier board of your choice
 VITA 57 compliant FMC works with Altera
and Xilinx FPGAs
 AC or DC coupling available
PERFORMANCE
 150 Msps to 4 Gsps sampling rate
DEG engineers leveraged the proven design and intellectual
property from the highly successful ADF-2500 board to bring the
ADF-Dxx00 family to market in record time.
By coupling this core architecture with the compact and flexible
FMC form factor, DEG has enabled customers to rapidly and costeffectively build compact and rugged systems with 1 - 4 channels of
high-speed digitization in a single high-performance FPGA carrier
board.
The front panel of the ADF-Dxx00 family has four 50 Ω connections
that serve as ports for analog sources, clock input or external
reference clock, and trigger input. This flexible approach reduces
the overall power consumption footprint and cost while increasing
ruggedness and reliability.
 Up to 2.3 GHz input bandwidth
 ENOB = 8.4 effective bits, Fin = 500 MHz
 4 channels of high-speed digitization in a
single VME/VXS/VPX/PCIe slot
Analog Input
Each analog input is single-ended with a full-scale input of 1 Vpp.
The analog input signal bandwidth extends up to 2.3 GHz. Software
-controllable attenuation may be available for select customers.
Maximum input is 2 Vpp.
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Clocks
The ADF-Dxx00 includes an onboard synthesizer to provide
the clock as well as the option for a user-provided clock. The
clock input allows frequencies between 150 and 2000 MHz.
ADF-Dxx00 Family Performance Specifications
Analog Specifications
Number of channels
2
Reference signal must be a sine or square wave with
amplitude from 200 mVpp to 3.5 Vpp. Frequencies between
10 and 100 MHz are allowed in 10 MHz increments. The
following sources can be selected for the synthesizer:
Sampling rate
150 Msps - 2000 Msps
Input bandwidth
4 MHz - 2.3 GHz (AC), 800 MHz (DC)
Input impedance
50 Ω, AC-coupled
• Onboard reference – 1 ppm accurate in the entire
temperature range of the product
Full-scale input
Single-ended, 1 Vpp (AC), 0.56 Vpp (DC)
Maximum input
2 Vpp (low), 3.5V (high attenuation)
• Front-panel clock input
SNR (typical)
55 dB @ Fin = 1448 MHz
• Carrier reference through FMC connection; this enables
board synchronization without external cabling.
SFDR (typical)
55 dB @ Fin = 1448 MHz
ENOB (typical)
8.4 effective bits @ Fin = 500 MHz
Triggers
Trigger input must be 200 mV to 3.3 V peak-to-peak signal.
Rise time of less than 10 nanoseconds is recommended. A
trigger event is initiated by a positive transition on the trigger
input. At the end of a capture event, the trigger circuitry is
reset to wait for another trigger event. An auto-trigger
function enables signal capture without an external trigger.
Trigger input is AC-coupled. DC coupling is available for select
customers. Trigger threshold is software-controllable in a
wide range for both DC- and AC-coupled versions of the
product.
Clock and Trigger Specifications
Connectors
Clock input
Clock input frequency
150 - 2000 MHz
Internal clock
20 MHz ± 1 ppm
Std PLL frequency
150 - 2000 MHz
Trigger input
Single-ended 50 Ω
ADCLink
Part Number
FMC modules are distinct and separate from the FPGA
devices that support them. Initiation and control of the ADFDxx00 is accomplished with ADCLink. Board support packages
are required for each unique host card.
The capabilities of ADCLink include clock phase adjustment,
onboard/external reference clock control, trigger input delays
and thresholds, sampling delay adjustments, and variable
ADC gain.
50 Ω, AC-coupled
Coupling
Rugged Level
Conformal Coat
ADF-Dxx00
AC
Commercial
—
ADF-Dxx00-C
AC
Commercial
√
ADF-Dxx00-R
AC
Rugged
—
ADF-Dxx00-RC
AC
Rugged
√
ADF-Dxx00-CC
AC
Conduction
—
ADF-Dxx00-CCC
AC
Conduction
√
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ADF-D1000/D1600/D1800/D2000 Environmentals
Environmental
Specifications
Commercial
Rugged
Conduction-Cooled
Operating temperature
0°C to +50°C (inlet air)
-40°C to +71°C (inlet air)
-40°C to +71°C (at card edge)
Storage temperature
-55°C to +85°C
-55°C to +125°C
-55°C to +125°C
Humidity (non-condensing)
0 to 95%
0 to 100%
0 to 100%
Vibration (random)
0.01g2/Hz, 15-2,000 Hz
0.04g2/Hz, 15-2,000 Hz
0.04g2/Hz, 15-2,000 Hz
Shock
20 g peak
30 g peak
40 g peak
Based on MIL-STD-810F
ADF-D1000/D1600/D1800/D2000 Block Diagram
About DEG
The Delphi Engineering Group (DEG) provides a full range of high-performance COTS-based and customized digital receiver
technology, products, and services for mission-critical applications in the aerospace, defense, and communications industries.
A Signal of Greater Interest is a trademark of Delphi Engineering Group. Altera is a registered trademark of Altera Corporation. Xilinx is a registered trademark
of Xilinx Inc. Other products mentioned may be trademarks or registered trademarks of their respective holders.
485 East 17th Street, Ste 400, Costa Mesa, CA 92627
Tel: 949.791.4000 Email: sales@delphieng.com
www.delphieng.com
ADF-Dxx00-DS-0602
Copyright © 2014 Delphi Engineering Group