4 Elementary Structures of analog IC Building Blocks
4–1
Analog and Mixed-Signal IC Design
Hans L. Zapf
Hochschule München / University of Applied Sciences
Department of Electrical Engineering and Information Technology,
Lothstrasse 64, D-80335 Munich, Germany
zapf@ee.hm.edu
4 Elementary Structures of analog IC Building Blocks
Contents
4
Elementary Structures of analog IC Building Blocks .........................................................4 -1
4.1 MOSFET Basics and Elementary Circuit Structures ...................................................4 -2
4.1.1 The MOS Transistor .............................................................................................4 -2
4.1.2 Elementary Circuit Structures ..............................................................................4 -6
4.2 Basic amplifier stages ..................................................................................................4 -7
4.2.1 Common-Source Stage (CS Stage) with resistive Load ......................................4 -8
4.2.2 Common-Source Stage with active Load ............................................................4 -9
4.2.3 Common-Source Stage with Source Degeneration (CS + RS ) ........................4 -10
4.2.4 Common-Drain (CD) Stage (Source Follower) with resistive load ..................4 -11
4.2.5 Common-Drain Stage (Source Follower) with active Load ..............................4 -12
4.2.6 Common-Gate (CG) Stage with resistive Load .................................................4 -13
4.2.7 Cascode Stage ...................................................................................................4 -15
4.3 Current Mirrors and Differential Amplifiers .............................................................4 -17
4.3.1 Current Mirrors [Raz01], Ch. 5 ......................................................................4 -17
4.3.2 Differential Amplifiers .......................................................................................4 -21
4.4 Operational Amplifiers ..............................................................................................4 -26
4.4.1 Simple two-stage op amps ................................................................................4 -27
4.4.2 Folded-cascode op amps ...................................................................................4 -30
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4–2
4.1 MOSFET Basics and Elementary Circuit Structures
4.1.1 The MOS Transistor
MOSFETs or MOS transistors (so called because of their layer sequence Metal – Oxide – Silicon) are the most important electronic devices in integrated circuits (ICs). 95 % of all ICs, produced today, are manufactured in CMOS technologies. (CMOS = Complementary MOS).
Fig. 1 shows a cross section through a modern MOSFET.
The most modern CMOS technologies allow the production of up to 109 transistors into a single
IC (size up to 20x20 mm²); the channel lengths (L -2·LD) are currently in the range of 40-60 nm;
the gate oxide thickness tox is in the range of about 2 nm.
G
tox
S
L - 2·LD
D
B = Bulk (Substrat)
Fig. 1. Cross section through a modern MOSFET
The SPICE Level 1 -Model
The Level 1 model is only suitable for simple hand calculations. It neither describes subthreshold
behaviour nor any short channel effects [Raz01], Chapters. 2.2.2, 2.3, and 16.3.1.
Fig. 2 shows the symbols used, the conventions for voltage and current directions, the transfer
characteristics for NMOS and PMOS transistors, and the output characteristic curves with the
different regions of operation.
SymSPICE
Name
bol
Parameter
Dimen
sion
Sym- SPICE
Name
bol
Parameter
Dimen
sion
W
Channel Width
mm
L
Channel Length
m
Transconductance Parameter
A/V²
Drain source saturation
voltage
V
Oxide Thickness
m
LD
LD
Lateral Diffusion
m
KP
UTH0
VTO
Threshold Voltage
V
UDSsat
µ
UO
Channel Mobility
cm2 /V
tox
λ
2Φ
LAMBDA Channel length mod- V -1
ulation coefficient
PHI
Surface potential
V
γ
ε0
KP
TOX
GAMMA Body effect coefficient
-
V1/2
dielectric constant = 8,85e-12 As/Vm
F
εSi
-
dielectric constant of As/Vm
silicon εSi= ε0 ·εr_Si *)
NSub
NSUB
Substrate doping
εox
-
diel. constant of gate As/Vm
ni
intrinsic carrier density
oxide εox= ε0 ·εr_ox *)
Table 1. Symbols and Spice Parameters
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
cm-3
cm-3
4 Elementary Structures of analog IC Building Blocks
*) εr_ox ≈ 3,9 for SiO2 ;
4–3
εr_Si ≈ 11,9 for Silicon.
UBS = 0
ID
UBS < 0
S
UGS
UBS
G
B
PMOS
UTH0
H0
UBS > 0
UDS
UTH0
H0
PMOS
ID
UGS
NMOS
(c)
UBS = 0
D
D
ID
Triode
Region
ID
NMOS
Saturation
B
G
UBS
UGS
UDS
UDSSat UDSSat
S
(a)
UGS
Region
(b)
(d)
UDS
Cut-off Region ( ID = 0 )
Fig. 2. MOS Symbols, conventions for voltage and current directions for NMOS and PMOS
( a ),alternative symbols ( b ), transfer characteristics in saturation region ( c ), output
characteristic curves and regions of operation of an NMOS transistor( d )
Convention: NMOS: UDS > 0 , ID > 0; otherwise interchange Drain and Source terminals!
PMOS: UDS < 0 , ID < 0; otherwise interchange Drain and Source terminals!
Cut-off Region:
NMOS: UGS ≤ UTH : ID = 0;
Triode Region:
(Linear Region)
NMOS: UGS > UTH
PMOS: UGS < UTH
ID = KP
PMOS: UGS ≥ UTH : ID = 0.
and | UDS | ≤ | UDSSat | ;
and | UDS | ≤ | UDSSat | ;
[
]
W
1
U GS −U TH U DS − U 2DS 1  ∣U DS ∣ .
L−2 L D
2
For PMOS transistors, the current has to be assumed negative!
Drain-Source Saturation Voltage: | UDSSat | = |UGS – UTH | .
Saturation Region: NMOS:
PMOS:
ID =
UGS > UTH
UGS < UTH
and
and
| UDS | > | UDSSat |;
| UDS | > | UDSSat |;
1
W
2
KP
U GS −U TH  1∣U DS ∣

2
L−2 L D
with
K P =  C ox ;
C ox =
 ox
.
t ox
For PMOS, the current has to be assumed negative!
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4–4
If the values of ID and UDS are known, the current equation can be resolved for UGS :
U GS = U TH ±

2ID
KP
; „+“ for NMOS; „ - „ for PMOS.
W
1∣U DS ∣
L−2 L D
Threshold Voltage UTH
U TH = U TH0     ∣ 2  F ∣  ∣U BS ∣ −  ∣ 2  F ∣  .
The SPICE-Parameter GAMMA is always given with a positive value; for PMOS however, it
has to be introduced into the equation with negative sign!
The Source-Bulk PN-junctions must always operate in reverse polarity.
Hence
NMOS: UBS ≤ 0 ;
PMOS: UBS ≥ 0 !
The SPICE-Parameter PHI equals the value 2ΦF (Surface Potential)!
Body effect coefficient γ
=
1
 2 q Si N Sub ;
C ox
F =
 
N Sub
kT
ln
q
ni
.
In the case of PMOS transistors, the body effect coefficient is negative. The SPICE parameter
GAMMA however is always given with a positive value.
| UTH | must increase with increasing absolute value of the substrate voltage | UBS | .
Principle: | UBS | ↑ ⇒ | UTH | ↑.
From the above equations, the small signal-model in Fig. 3 can be derived.
G
D
uGS
g mu GS
g mbu BS
rDS
S
uDS
S
uBS
B
Fig. 3. Small-signal MOSFET model without capacitances
For analog circuits, the saturation region is most important!
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4–5
In the saturation region, the equations for the transconductances gm and gmb as well as for the
differential output resistance rDS are.
gm =
∂ID
W
= KP
U GS −U TH 1∣U DS ∣  or
∂U GS
L−2 L D
gm =
2ID
W
= 2IDKP
⋅1∣U DS ∣  ;
U GS −U TH
L−2 L D
g mb =
r DS =

∂ID

= gm
=  gm ;
∂U BS
2  ∣2  F ∣  ∣U BS ∣
∂ U DS
1
1
1
=
=
≈
g DS
∂ID
1
W
ID
2
K
U −U TH  ⋅
2 P L−2 L D GS
The inclusion of all capacitances of the transistor yields the complete small-signal model in
Fig. 4
c GD
G
c GS
S
c GB
uGS
D
g mu GS
g mbu BS
rDS
uDS
S
uBS
c SB
c DB
B
Fig. 4. Complete small-signal MOSFET model
Most of the capacitances in Fig. 4 are voltage dependent; their value depends on the operating
point of the transistor.
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4–6
4.1.2 Elementary Circuit Structures
●
„Diode-connected“ MOSFET [Raz01, Ch. 3.2.2]
| ID |
D
S
S
D
| UGS |= | UDS |
|UTH |
NMOS
PMOS
Fig. 5. NMOS or PMOS „diode-connected“ (Drain + Gate connected) and I/U-curve.
The configuration is known from bipolar transistors, which in the case of a Collector-Base
short circuit form a bipolar diode. Short-circuiting drain and gate of a MOSFET creates a twoterminal device with a quasi-diode characteristic (Fig. 5). Enhancement Transistors in this
configurations always operate in the saturation region!
Large-signal behaviour: in the ideal case (Level 1 Model), the device has a quadratic
I-U-curve!
∂ U DS
1
1
=
∥ r DS ≈
Small-signal behaviour: differential resistance r =
.
∂ID
g m  g mb
gm
●
Parallel connection of MOSFETs
D
G
W
L
W
L
D
G
S
2W
L
S
Fig. 6. MOSFETs connected in parallel
Sometimes, MOSFETs are composed of several singular transistors having the same channel
length, which are connected in parallel (Fig. 6).
Benefit: reduced parasitics (capacitances, gate resistance), simplified layout, standardized
transistor sizes in RF-designs.
Effect: the channel widths can be added: the composed transistor behaves like a single
(equivalent) transistor with the channel width W = Σ Wi of the transistors connected in
parallel.
[Raz01, Ch. 2.4.2; 7.2.1; 18.2.1]
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
●
4–7
Series connection of MOSFETs
The configuration in Fig. 7 is sometimes used in order to overcome the voltage limitations of
circuits. The lower transistor M1 always operates in the triode region; the equivalent transistor
operates in saturation if M2 is in saturation.
For  = 0 and  = 0 the approximation in Fig. 7 is valid.
D
G
M2
M1
D
W
L
G
W
L
W
2L
S
S
Fig. 7. Series connection of two MOSFETs and their approximate equivalent circuit
4.2 Basic amplifier stages
Overview
The basic amplifier stages are distinguished by the name of the pin which is common to the
input and the output port: common-source stage (CS), common-drain stage (CD, also called
source follower SF) and common-gate stage (CG) – see Fig. 8. The common-source stage with
resistive feedback, also known as CS-stage with emitter degeneration, is a modification of the
common-source stage.
Common
Source (CS)
signal input
input pin
MOS
FET
signal output
→G
CS + R
feedback
→G
Common
Drain (SF)
→G
Common
Gate (CG)
→S
output pin
D→
D→
S→
D→
3 rd pin
S
S
D
G
rd
3 pin
?
AC-Ground
AC
ground
R!
Fig. 8. Basic amplifier stages - overview
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4–8
4.2.1 Common-Source Stage (CS Stage) with resistive Load
See Fig. 9 - [Raz01, Ch. 3.2.1].
Uout
UDD
RD
Transistor in
Cut-off region
UDD
rout
Saturation region
D
Uin
Uout
S
UDSSat
Triode region
Uin
UTH
Fig. 9. Common-source stage with resistive load – left: schematic; right: voltage transfer
curve
This circuit only works properly as an amplifier as long as the transistor operates in the
saturation region ( UDS > UDSSat ) ! This is a constraint, which has to be observed in nearly all
analog circuits.
Normally, an operating point in the middle of the voltage transfer curve is chosen in order to
achieve maximum distance to the cut-off and to the triode region, when applying an input signal
to the amplifier.
The small-signal behaviour of the circuit can be described with the following equations:
AU =
u out
= −g m⋅ R D ∥ r DS  ;
u in
r out = R D ∥ r DS .
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4–9
4.2.2 Common-Source Stage with active Load
See [Raz01, Ch. 3.2.3]
The resistive load in Fig. 9 is often replaced by a so-called active load; this is a transistor which
acts as load element. Active loads are preferred in integrated circuits because they have several
advantages: they need less area than resistors, they have less parasitic effects, and they offer a
higher (differential) resistance and hence yield a higher voltage gain of the stage.
UDD
Uout
S
Ub
const
M2
D
UDD
UDD
rout
D
Uin
M1
|UDSSat2 |
„linear region“
( Headroom )
Uout
Uout
UDSSat1
S
UDSSat1
0V
Uin
UTH
Fig. 10. Common-Source stage with active load – left: schematic;
center: voltage transfer curve; right: region of linear operation
Fig. 10 shows the circuit schematic with a PMOS load transistor M2 , the voltage transfer curve,
and the region of linear operation of the stage: this is the region where both transistors operate in
the saturation region! (Constraint for design)!
Small-signal behaviour:
AU =
u out
= −g m1⋅ r DS1 ∥ r DS2  ;
u in
r out = r DS1 ∥ r DS2 .
Theoretically, the gain can reach a maximum value AUmax in the case that r DS2  ∞ (ideal current source as load element):
g
∣AUmax ∣ = g m1 ⋅r DS1 = g m1 .
DS1
A voltage gain in the range 20 ... 50 is achievable with short-channel transistors; when using larger channel lengths ( L > 2 ... 5 Lmin ), values up to 200 are possible.
The reason for this is that the differential resistance rDS of integrated MOSFETs, taken at the
same quiescent current, depends on the channel length of the transistor in all IC technologies!
Trend: Large L => large rDS .
This is an important restriction to the design of analog integrated circuits! Transistors with
minimum channel length are only advantageous for digital circuits; analog circuits – amplifier stages in particular – normally require larger transistors.
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4 – 10
4.2.3 Common-Source Stage with Source Degeneration (CS + RS )
See [Raz01, Ch. 3.2.5].
Fig. 11 shows the circuit schematic and the voltage transfer curve. The resistor RS causes a negative (series-series) feedback which reduces the voltage gain and, at the same time, linearizes the
voltage transfer curve. The output voltage range is reduced due to the voltage drop over RS , and
the output resistance of the transistor is increased.
UDD
RD
rout
Uout
UDD
D
S
Uin
RS
Uout
UDSSat
Uin
UTH
Fig. 11. Common-Source stage with source degeneration (via RS ),
left: schematic; right: voltage transfer curve
Constraint: the transistor must work in the saturation region!
Small-signal behaviour:
AU =
u out
−g m R D
=
;
u in
1  g m RS
r out = r DS⋅[ 1 g m g mb  R S ] ∥R D .
Notes
1. In this circuit, a source-substrate voltage unequal to zero occurs, because the source voltage is no longer
constant. Due to the substrate effect, the threshold voltage increases with increasing input voltage.
2.
Due to the phase inversion between input and output voltages, all common-source stages have the drawback of
the MILLER effect: the parasitic Drain-Gate capacitance of the transistor causes an increase of the input
capacitance of the amplifier stage. Together with a source resistance, this increased input capacitance causes a
low-frequency pole of the transfer function. High gain common-source stages are therefore not suited for highfrequency applications [Raz01, Ch. 6.1.1].
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4 – 11
4.2.4 Common-Drain (CD) Stage (Source Follower) with resistive load
See [Raz01, Ch. 3.3].
Fig. 12 illustrates the circuit schematic and the voltage transfer curve. The voltage gain is in all
cases less than one! The circuit is used as a level shifter and as an impedance converter due to its
small output resistance.
UDD
Uout
D
UDD
S
UGS
rout
„linear region“
( Headroom )
Uout
Uin
RS
UDD
Uout
0V
UDD U
in
Fig. 12. Source Follower with resistive load – left: schematic; center: voltage transfer curve;
right: region of linear operation
UTH
Constraint: The transistor must work in the saturation region: U TH  U in ≤ U DD U TH 
Small-signal behaviour:
AU =
u out
g m RS
=
1 ;
u in
1 g m g mb  R S
r out =
1
1
∥ RS≈
.
g m g mb
gm
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4 – 12
4.2.5 Common-Drain Stage (Source Follower) with active Load
See [Raz01, Ch. 3.3].
The circuit and the linear region of operation are shown in Fig. 13. The resistor R2 is here
replaced by the MOSFET M2 which is biased by a constant gate voltage Ub . The output voltage
remains in the “linear region” if both transistors operate in the saturation region (2 Constraints)!
UDD
UDD
UGS1
D
M1
Uin
S
„linear region“
( Headroom )
rout
Uout
D
Ub
const
M2
Uout
RL
S
UDSSat2
0V
Fig. 13. Source follower with active load (M2 ) - left: schematic;
right: linear region of operation
Small-signal behaviour:
AU =
u out
gmra´
=
 1 with r a ´ = r DS1 ∥ r DS2 ∥ R L ;
u in
1g m g mb r a ´
r out ≈
1
1
∥ r DS2 ≈
.
g m1 g mb1
g m1
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4 – 13
4.2.6 Common-Gate (CG) Stage with resistive Load
See [Raz01, Ch. 3.4].
The common-gate stage, shown in Fig. 14, is advantageous for high-frequency applications
because it is not degraded by the MILLER effect. The CG stage has a low input resistance, a high
output resistance, and a high voltage gain, (in fact the same gain as the common-source stage),
but no phase inversion.
UDD
rout
RD
D
Ub
const
rQ
S
Uout
Uin
r in
Fig. 14. Common-Gate stage with resistive Load and
current source on the source side for biasing.
Constraint: The transistor must operate in saturation region.
Small-signal behaviour:
AU =
Voltage gain:
u out
≈  g m g mb  R D ≈ g m R D .
u in
Input and output resistance of the transistor in a CG stage.
Fig. 15 depicts the small-signal equivalent circuit of the transistor in CG configuration with
signal source and load.
r DS
rQ
g m u GS
S
D
S
i
uQ
u in
u GS
g mb u BS
ra
u out
r in T
i
rout T
r in T
G
D
x1
G
Transistor
rout T
rout
r in T
Transistor
Fig. 15. Small-signal equivalent circuit of a transistor in CG configuration with source and load (left),
and simplified equivalent circuit (right)
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
rout T
4 Elementary Structures of analog IC Building Blocks
4 – 14
In the first approximation, the transistor input resistance is proportional to the reciprocal of the
transconductance; the transistor output resistance rout_T is large, it depends however on the
impedance of the signal source rQ .
CG-stage:
r in T =
input resistance
approximation for gm* rDS >> 1:
r a  r DS
;
1  g *m⋅r DS
ra
1
1
1
r in T ≈

* ≈
≈
.
g m *⋅r DS
gm
g m*
gm
output resistance
r out T = [1  g *m⋅r Q ] r DS  r Q
approximation for gm rQ >> 1:
r out T = g *m⋅r Q ⋅r DS ≈ g m⋅r Q ⋅r DS .
;
At the output node of the stage (Fig. 13), the resistor RD lies in parallel with rin T ,
consequently, the output resistance of the whole stage is
r out = { [1   g m g mb ⋅r Q ]⋅r DS  r Q }∥ R D ≈  g m⋅r Q⋅r DS ∥ R D .
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4 – 15
4.2.7 Cascode Stage
See [Raz01, Ch. 3.5]
The cascode stage is a two-transistor stage with a transistor in CS configuration (M1 ) at the input
side, followed by a second transistor in CG configuration (M2 in Fig. 16). This stage combines
the high input resistance of the CS stage with the good RF properties of the CG stage. Specific to
the cascode stage is that the first (CS) stage has only a small voltage gain close to the value of
-1. Hence, the Miller effect is no longer dominant in this inverting partition of the amplifier. The
(high) voltage gain is then realized by transistor M2 in CG configuration.
The total voltage gain of the cascode is comparable to that of a single common-source stage or a
single common-gate stage.
UDD
RD
rout T2
D2
G2
M2
Ub = const
Uout
S2
G1
D1
Uin
M1
G1
S1
Ux
g m1 u IN
D1
S2
i
u in
r DS1
ux
S1
u GS2
D2
x1
1/g m2
i
rout T2
RD
u out
G2
M1
r in T2
M2
rout T2
Fig. 16. Cascode stage – circuit schematic (left) and
small-signal equivalent circuit (right)
Constraints: Both transistors must operate in saturation region.
Specific properties of the cascode stage
1. The input resistance of M2 is small. Because this resistance is the load for the first stage
(M1 ), the voltage gain AU1 = ux / uin is small as well.
As approximately rin T2 ≈ 1/gm2 , and rDS1 >> rin T2 , the voltage gain of the first stage is
AU1 ≈ −g m1⋅r in2 = −
g m1
.
g m2
2. If both transistors have the same transconductance, then AU1 ≈ -1.
In the first stage, the Miller effect has no longer a significant influence: the parasitic
capacitance cGD does not influence the transfer characteristic of this stage.
AU2 = uout / u x ≈ g m2 ⋅R D ∥ R L  . This is a large voltage gain!
3. Second stage:
(RL is a possible external load resistance). In CG stages, the Miller effect is not important.
If a very large voltage gain is required, RD (or RD || RL ) must have high values. Therefore,
an active load or even another cascode stage as load element is often used in practical
circuits.
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4 – 16
4. Total voltage gain of the cascode stage: AUCascode = AU1 · AU2 .
5. Transistor M2 exhibits has a high output resistance because it operates in CG configuration.
r out _ T2 ≈ r DS2⋅ 1  g m2 r DS1 ≈ g m2⋅r DS2⋅r DS1 ≫r DS1 , r DS2 .
The total output resistance of the cascode stage is RD || rout_T2 !
In the case of active loads, their small-signal resistance replaces RD in the formula for AU2
in number 3 above.
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4 – 17
4.3 Current Mirrors and Differential Amplifiers
4.3.1 Current Mirrors
[Raz01], Ch. 5
Current mirrors are frequently used in analog integrated circuits. As current sources and/or
current sinks, they are in use for biasing purposes and also for analog signal transmission.
The ideal current mirror is basically a current-controlled current source (Fig. 17). It is
composed of a controlling current path through which the current Iref flows, and a controlled
path, which delivers the current I2 . The transmission factor α often equals one. Only in the case
of ideal current mirrors, I2 is independent of the voltage U at the output.
Iref
I2 = αIref
αi
i
α
U
Fig. 17. Ideal current mirror
●
Basic Current Mirror with Enhancement MOSFETs
The most simple realization of a current mirror is shown in Fig. 17: two MOSFETs have the
same Gate-Source-voltage UGS1 = UGS2 . Transistor M1 is diode-connected.
Iref
r IN
I2
r OUT
D
S
M2
M1
UGS = f -1 (Iref )
D
UDS2
S
Fig. 18. Simple current mirror
Principle of operation (approximation: channel length modulation parameter λ = 0 )
controlling branch
I ref = I D1 =
controlled branch
I 2 = I D2
 
W1
2
1
 C ox
U GS1 − U TH1  → U GS1 = f −1  I ref 

2
L1
↓ (!)
UGS2 = UGS1
↓ (!)
W2
2
1
=
 C ox
U GS2 − U TH2 
← ID2 = f (UGS2 )

2
L2
 
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4 – 18
If M1 and M2 match (i.e. they have equal values of µ, Cox , UTH etc.) and if M2 stays in the
saturation region, then the current relation is
I2
W 2 / L 2 
W2
=
=
I ref
W 1 / L 1 
W1
,
assumed that L1 = L2 .
The current ratio can be determined by the channel width ratio (equal channel lengths
provided)!
Notes
1. Current mirrors can also be realized using PMOS enhancement transistors.
2. The transfer principle I2 = f ( f -1 (Iref ) ) is called translinear principle. It can be traced back to BARRIE GILBERT,
one of the pioneers of analog circuit design, who realized it at first with bipolar transistors. When using bipolar
transistors, the current ratio is determined by the ratio of the emitter areas.
Important: M2 must operate in saturation region: UDS2 > UDSSat2 !
This condition is the major difference to the behaviour of an ideal current-controlled current
source. There exists in any case a not usable voltage region at the output; see Fig. 19, where
the transistor operates in the triode region.
I2
not usable region !
UGS = const
UDSSat
UDS2
Fig. 19. Not usable output voltage region
From the relations discussed above, the constraints for current mirrors can be deduced:
both transistors must match and the controlled transistor must operate in saturation region.
Small-signal behaviour
M1 is „diode-connected“
M2 operates in common-source mode
rIN
= 1 / gm1 ;
rOUT = rDS2 .
In practice, the symmetry is often affected by the channel length modulation at transistor M2 .
A variation in UDS2 results in a change of the current I2 . The differential output resistance rOUT
is in some cases too small.
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4 – 19
Basic Current Mirror – a closer look (Assumption: matching parameters).
Taking channel length modulation into account ( λ ≠ 0 ); the I/U-equations are
 
 
I ref = I D1 =
W1
2
1
 C ox
 U GS − U TH  ⋅ 1U DS1  ;
2
L1
I2 =
W2
1
2
 C ox
U GS − U TH  ⋅ 1U DS2  ;
2
L2
I D2 =
I D2
W 2 / L2  1 U DS1
=
⋅
.
I D1
W 1 / L1  1U DS2
In practice, UDS1 = UGS1 ≈ const ; UDS2 however is variable! This influence disturbs the
symmetry of the current mirror. Consequently, improvements aim at an enlargement of the
output resistance rOUT .
●
Enlargement of the output resistance through negative feedback.
The two resistors R in Fig. 20 realize a negative feedback, already known as source
degeneration (see page 4-10).
Iref
r IN
I2
r OUT
D
S
R
M1
not usable region !
D
M2
R=0
R>0
UGS
Iref R
I2
S
U2
R
U2min
U2
UDSSat
Fig. 20. Current mirror with resistive feedback - circuit schematic (left);
output curves at different values of R (right)
Constraints: Matching of M1 /M2 ; Matching of the both resistances R ; M2 must operate in
saturation region.
Advantage
The negative feedback enlarges the output resistance to a value of
rOUT = rDS2 [ 1 + ( gm2 + gmb2) R ] + R ≈ rDS2 [ 1 + ( gm2 + gmb2 ) R ] .
Disadvantage
The minimum voltage U2min at the drain of M2 increases as well: U2min = UDSsat2 + I·R .
Because in integrated circuits, resistances are preferably replaced by transistors, the so-called
cascode current mirror is an alternative to the circuit above.
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
●
4 – 20
Cascode Current Mirror
[Raz01], Ch. 5.2
Fig. 21 shows the schematic of a cascode current mirror.
Iref
I2
r OUT
D
S
D
S
M2
M1
S
UGS1
M4
M3
D
UDS2 > UDSSat2
D
UDS4 > UDSSat4
S
UGS3
Fig. 21. Cascode current mirror with NMOS transistors
Constraints:
Matching of M1 /M2 and M3 /M4 ; in addition, M2 and M4 must operate in saturation region.
Specific to the cascode current mirror is its larger output resistance
r OUT = r DS2⋅[1
  g m2 g mb2  r DS4 ]  r DS4 ≈ r DS2⋅[1  g m2 r DS4 ]

Wirkung der GK
Note: The substrate effect influences the transistors M1 and M2 as their source-substrate voltages UBS1 and UBS2
are different from zero!
The minimum voltage at the drain of M2 is U2min = UDSSat2 + UDSSat4 ;
it is larger than for the basic current mirror ( Loss of headroom )!
This restriction is increasingly a problem because due to the downscaling of device sizes and
voltages by the progress of technologies, the supply voltage UDD is decreased as well.
Note: Further design tricks aim at a reduction of this minimum voltage. Many proposals were published to
overcome this problem. Fig. 22 shows one example.
Iref
I2
Fig. 22. Alternative cascode current mirror for low-voltage operation [Raz01,Ch. 5.2]
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4 – 21
4.3.2 Differential Amplifiers
Differential amplifiers are the most important analog circuits as they form the input stages of all
operational amplifiers. The use of symmetrical signals is a possibility to overcome the problem
of maintaining a sufficient signal-to-noise ratio at decreasing supply voltages.
●
Differential amplifier with resistive load - [Raz01], Ch. 4 and 6.6.
The basic schematic is given in Fig. 23
UDD
RD
U1A
M1
U1D = U1A – U1B ;
Common-mode
input voltage :
U1G = ( U1A + U1B )/2 ;
RD
U2
U2A
Definitions
Differential input voltage:
U2B
M2
U1B
r SQ
unsymmetric output: U2A, U2B with respect to ground;
symmetric output
2I0
Fig. 23. Differential amplifier with resistive
load
U2 = U2A - U2B
The current source 2I0 can be realized with a simple
transistor current source (e.g. a current mirror) with or
without feedback or with a cascode current source.
Constraints: Matching of M1 / M2 ; Matching of the both resistors RD ; both transistors must
operate in saturation region.
Small-signal gain for f → 0
Note: ux are the small-signal voltages, which superimpose the DC voltages UX .
Differential voltage gain
A DA =
u 2A
1
= − g m1 R D ∣∣ r DS1  ;
u 1D
2
A DB =
u 2B
= − A DA ;
u1D
Common-mode voltage gain
AGA = AGB =
u 2A
u
−g m1 R D
R
= 2B =
≈− D
u 1G u 1G 1 g m1⋅2 r SQ
2 r SQ
.
with rSQ being the differential resistance of the current source 2I0 .
Common-mode rejection ratio
ACMR A =
CMRR
A DA
g  R ∣∣r ⋅r
= m1 D DS SQ ~ r SQ
AGA
RD
CMRR(A) = 20 log | ACMR(A) | .
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4 – 22
Important aspects for dimensioning:
•
the channel lengths of M1 and M2 should not be chosen too small because of rDS ;
•
the W/L ratio of M1 and M2 should not be chosen too small to obtain a sufficient gm ;
•
the area W·L should not be chosen too small because of parameter matching and
1/ f -noise (which increases with decreasing area).
●
Differential amplifier with active load - [Raz01], Ch. 4.4, 9.2
Ub
UDD
M3
M4
U2A
U1A
U2B
M1
S
M2
U1B
This form of differential amplifier results from the
standard form by replacing the resistive load RD with
the PMOS load transistors M3 / M4 , as shown in Fig.
24. The gates of M3 and M4 are connected to a
constant bias voltage Ub . The differential output
resistances rDS of the load transistors allow for a
higher gain of this circuit.
r SQ
2I0
Fig. 24. Differential amplifier
with active load
Constraints: Matching of M1 / M2 ;
Matching of M3 / M4 ;
all transistors must operate in the saturation region.
Small-signal gain for f → 0
u 2A
1
= − g m1 r DS1 ∥ r DS3  ;
u1D
2
r
AGA = A GB ≈ − DS3 .
2 r SQ
A DA =
A DB =
u 2B
= − A DA ;
u 1D
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4 – 23
Common-mode input voltage range and output voltage range
Ub
UDD
M3
M4
U2A
U1A
| UDSSat3,4 | - UTH1,2
UDD
U1G
U2B
M1
S
M2
r SQ
2I0
UDD
| UDSSat3,4 |
U2
U1G
U1B
UGS1,2
φSmin
0V
Fig. 25. Common-mode
input voltage range
UGS1,2
φS > φSmin
φSmin
0V
Fig. 26. Output voltage range
The permissible range of common-mode input voltage is U1Gmin < U1G < U1Gmax .
When the common-mode input voltage U1G varies, the potential φS of the joint source node S
of the transistors M1 /M2 varies as well. In a differential amplifier using NMOS input
transistors, φS is always more negative than the common-mode input voltage:
φS = U1G - UGS1,2 .
To find the limits of the common-mode input voltage U1G , the limits of φS must be checked.
The upper limit of U1G is reached, when the drain-source voltages of the transistors M1 /M2
and M3 /M4 arrive at the margin of their saturation region. In this case
and hence
φSmax = UDD - |UDSsat3,4 | - UDSSat1,2
U1Gmax = φSmax + UGS1,2 = UDD - |UDSSat3,4 | + UTH1,2 .
The lower limit of U1G is determined by the minimum permissible potential φSmin that is
necessary to maintain the operability of the current source (mostly the UDSSat of the current
source transistors (see chapter 4.3.1).
Thus
U1Gmin = φSmin + UGS1,2 .
The upper limit of the output voltage range U2min < U2 < U2max is
U2max = UDD - |UDSSat3,4 | , as M3 /M4 must operate in saturation
the lower limit depends on the potential φS of the joint source node of M1 /M2 which must
satisfy the condition φS = U1G – UGS1,2 . But, because also M1 /M2 must operate in saturation
region, the minimum value of U2 is U2min = φS + UDSSat1,2 . With UDSSat = UGS – UTH we get
the lower limit
U2min = U1G – UGS1,2 + UGS1,2 – UTH1,2 = U1G - UTH1,2 .
Note - Possible improvements to this circuit
1. To achieve a higher differential voltage gain: enlarge the load resistance by introducing a cascode load
instead of M3 , M4 ;
2. to achieve a lower common-mode gain: enlarge rSQ , the internal resistance of the current source, by use of a
cascode current mirror.
Both measures have the drawback that common-mode voltage range and the output voltage range will be further
reduced.
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
●
4 – 24
Differential amplifier with current mirror load - “single-end” - [Raz01], Ch. 5.3, 6.6, 9.2.
Specific features:
- Frequently used circuit topology (Fig. 27);
- active current mirror M3 → M4 (PMOS);
- single end: only one output with respect to ground;
- the output has a high impedance (current source);
alternative designation: OTA
(Operational Transconductance Amplifier);
- AUD depends on the load resistance;
- output current i2 limited to | i2max | = 2I0 ;
Significance for Slew Rate in case of
capacitive load!
UDD
M3
M4
i2
X
U1A
M1
U2
U1B
M2
2I0
Fig. 27. Differential amplifier with
current mirror load (single-end).
Constraints: Matching of M1 /M2 ;
Matching of M3 /M4 ; all transistors must operate in
saturation region.
The small-signal behaviour can be explained using the equivalent circuit in Fig. 28.
Small-signal differential voltage gain for f → 0
AU0 =
u2
= g m1⋅r DS2 ∥ r DS4 ∥ R L  .
u1D
The output resistance of the stage is rDS2 ║rDS4 .
The frequency dependence of the gain is determined by the load capacitance CL (if existing).
The equivalent circuit yields the cut-off frequency fg and the gain-bandwidth-product
GBW = fT
g m1
1
fg =
;
GBW = f T =
.
2 r DS2 ∥ r DS4 ∥ R L C L
2 C L
aU
g m1 u 1D
(+)
a U0
i2
u 1D
u 1A
(-)
u 1B
u2
RL
CL
r DS2 ║r DS4
0 dB
fg
Fig. 28. Equivalent circuit for small-signal operation (left) and
frequency response of differential voltage gain (right)
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
fT
f
4 Elementary Structures of analog IC Building Blocks
4 – 25
Large-Signal Behaviour
In the case of a large positive or negative differential input voltage (exceeding several
100 mV), the output current i2 is limited to the value 2I0 given by the current source (Fig. 29).
Case 1 ( U1A >> U1B ): The current in M1 and M3 is limited to 2I0 while M2 is in the cut-off region: due to the
current transfer M3 → M4 , also M4 can deliver the current 2I0 . As M2 is cut off, this current is available at the
output node and i2 max = +2I0 .
Case 2 ( U1A << U1B ): M1 and M3 are cut off, while M2 has the current 2I0 . Due to M3 → M4 , also M4 is cut
off. The current source and the conducting transistor M2 determine the current i2 min = -2I0 .
i2
Slope: gm1 = gm2
2I0
U1D
-2I0
Fig. 29. Limitation of the output current i2 in the case of large differential voltages
When a capacitance is connected to the output node, the slew rate will be
SR =
d u2
dt
|
max
=
2I0
.
CL
Disadvantages of this circuit
1. The potential at the gate of M3 / M4 (node „X“ in Fig. 27) stays nearly constant
G3 ≈ const , even when a differential signal is applied. In contrast, U2 changes its
value. This introduces an unsymmetry into the circuit: UDS1 and UDS2 differ. The channel
length modulation effect (factor 1   U DS  in the ID = f(UGS, UDS ) equation) influences
only transistor M2 .
2. At high frequencies, a second pole occurs in the frequency response. This pole is caused
by the parasitic capacitance C* (with respect to ground) at the gate node of M3 / M4 and at
the drain of M1 and M3 in combination with the effective small-signal resistance at this
node (1/ gm3 ). (Way of signal: M1 , M3 , M4 ): fp2 = gm3 /(2 π C* ) . [Raz01], Ch. 6.6.
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4 – 26
4.4 Operational Amplifiers
Operational amplifiers (op amps) are basic elements in the world of analog circuits. Op amp
blocks as sub-structures in mixed-signal integrated circuits can be adapted to the respective
requirements [Raz01], ch. 9. We distinguish op amps with unsymmetric output (single end) from
those with symmetric output (double end) – see Fig. 30.
If the op amps have high output resistances, they are in fact current sources, which are controlled
by the differential input voltage; their transfer characteristic is a transconductance. Those op
amps are called OTAs (operational transconductance amplifiers).
U1A
U1A
U2
U1B
U2A
U2
U1B
U2B
Fig. 30. Op amps with single end (left) and with double end (right)
Essential circuit properties of op amps (design goals) are
•
•
•
•
•
•
High differential voltage gain (open-loop gain); low common-mode gain (= high common
mode rejection); high power supply rejection.
Frequency response of the differential gain; small-signal bandwidth / gain-bandwidth-product;
stability in feedback configurations; phase margin.
High common-mode input voltage range; high output voltage swing.
Slew Rate; power consumption.
Linearity; offset voltage, noise
Layout area.
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4 – 27
4.4.1 Simple two-stage op amps
●
Two-stage op amp with symmetric output (double end) - [Raz01], Ch. 9.3
The circuit in Fig. 31 is composed of a differential amplifier with active loads and two
subsequent amplifier stages in common-source configuration with the active loads M7 and
M8 . Ub1 and Ub2 are constant bias voltages. The capacitors CC serve for frequency
compensation.
UDD
X
M5
U2A
M3
M4
Y
M6
Ub1
CC
U1A
M1
M2
U2B
U1B
CC
2I0
Ub2
M8
M7
Fig. 31.Simple two-stage op amp with double end
Constraints
Matching M1 / M2 ; M3 / M4 , M5 / M6 ; M7 / M8 ; all transistors must operate in saturation.
Small-signal gain for f → 0
stage 1
AU1 =
uX
1
= − g m1 r DS1 ∥ r DS3  ;
u 1D
2
stage 2 (CS)
AU2 =
u 2A
= = −g m5 r DS5 ∥ r DS7  ;
uX
together
u 2A
1
= A U1⋅A U2 = g m1 r DS1 ∥ r DS3 ⋅g m5⋅r DS5 ∥ r DS7  .
u 1D
2
In the case of a load resistance RL at the output node(s), RL must be introduced in parallel with
rDS5 and rDS7 . A corresponding set of equations applies to the right side (M2 , M4 , M6 , M8 ).
Output voltage range of U2A :
U DSSat7 ≤ U 2A ≤ U DD − ∣ U DSSat5 ∣
Small-signal analysis / Frequency response of the differential gain.
Low-pass characteristic with 2 poles. Frequency compensation through capacitances CC
between drain and gate of M5 and M6 (Miller compensation, Pole-splitting compensation).
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
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4 – 28
Two-stage op amp with unsymmetric output (single end)
Possibility1: Differential amplifier with current mirror + subsequent CS-stage
The circuit is composed of a differential amplifier with current mirror load which already has
a single-ended output, and a subsequent gain stage in CS-configuration with M6 as active
load. Ub is a constant bias voltage. CC provides the frequency compensation.
UDD
M3
M4
M5
U1A
M1
M2
2I0
U2
U1B
CC
Ub
M6
Fig. 32. Two-stage op amp with unsymmetric output version 1
Constraints
Matching M1 / M2 ; M3 / M4 ; all transistors in saturation.
Small-signal gain for f → 0
u2
= −g m1 r DS2 ∥ r DS4 ⋅g m5⋅r DS5 ∥ r DS6 
u 1D
In the case of a load resistance RL at the output node, RL must be taken in parallel with rDS5
and rDS6 .
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4 – 29
Possibility 2: OTA with current summation at the output node - (Fig. 33).
This circuit avoids the drawbacks of the differential amplifier with current mirror load. The
differential input stage is here completely symmetric; thus, the amplifier exhibits an improved
common-mode behaviour. The small-signal voltage at the node X is transferred to the output
via the transistors M5 , M7 , and M8 ; the respective small-signal voltage at node Y via M6 . Both
small-signal currents are summed at the output node.
UDD
M5
X
M3
M4
Y
Ub1
U1A
M1
M2
M6
U1B
U2
2I0
M7
M8
Fig. 33. Two-stage op amp with current summation at the output node (version 2)
Constraints: Matching of M1 /M2 , M3 /M4 , M5 /M6 , M7 /M8 . All transistors must operate in
saturation.
Small-signal gain for f → 0
signal path 1: M1 /M3 → M5 /M7 /M8 ;
signal path 2: M2 /M4 → M6 .
Note:
Due to the constraints, it can be assumed that gm1 = gm2 , gm3 = gm4 , gm5 = gm6 and gm7 = gm8 !
uX
1
= − g m1⋅r DS1 ∥ r DS3 
u 1D
2
i D5
i
= g m5 = D8
uX
uX
uY
1
=  g m2⋅r DS2 ∥ r DS4 
u 1D
2
i D6
= g m6
uY
i 2 = −i D6 − i D8 = − g m5⋅g m1⋅r DS1 ∥ r DS3⋅u 1D
u 2 = −i 2⋅r DS6 ∥ r DS8  = − g m1 g m5⋅r DS1 ∥ r DS3 ⋅r DS6 ∥ r DS8 ⋅u 1D
In the case of a load resistance RL at the output node, RL must be taken in parallel with rDS6
and rDS8 .
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4 – 30
4.4.2 Folded-cascode op amps
The simple cascode stage was treated at the end of ch. 4. (page 4-). The benefit of cascode
circuits is the very high differential resistance that can be obtained with it and – as a consequence
of this – a higher voltage gain. The folded cascode is a modification which is used frequently in
today's analog circuits.
Basics of folded cascode stages - [Raz01], Ch. 3.5.2, 9.2.
UDD
UDD
I1
I1
U2
Ub = const
D
U2
S
U1
M2
M1
D
D
M2
S
S
Ub = const
D
U1
M1
S
I2
Fig. 34. Transition from the simple cascode stage to the folded cascode stage;
the partition in the frame remains unmodified
Reasons for the introduction of the folded cascode
•
•
The static voltage difference between the input and the output can be reduced. This is important for buffer applications, where the output is directly connected to the input!
The output voltage range can be enlarged.
How to fold the cascode - Fig. 34.
The type of the input transistor M1 (in CS config.) must be inverted (NMOS → PMOS); for this,
a second current source I2 is needed. The transistor M2 (in CG config.) and its (active) load element (here current source I1 ) remain unmodified.
Important: when dimensioned properly, the small-signal properties of both circuits remain the
same.
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4 – 31
Folded cascode op amps – selected circuit structures - [Raz01], Ch. 9.2.
A cascode differential stage can be folded according to the procedure described above.
Fig. 35 shows an example.
UDD
I0
UDD
I0
U2
M1
Ub =
const
M3
U1A
M1
I0
2I1
S
U2
M2
Ub
M2
U1A
M4
I0
D
M3
U1B
M4
S
D
U1B
I2
2I0
I2
Fig. 35. Transformation of a cascode differential stage into a folded cascode differential stage
●
Folded cascode op amp with symmetric output (double end)
The transistor circuit in Fig. 36 is a realization of the schematic in Fig. 35 . The current
sources 2I1 and I2 are realized through simple transistor current sources (M11 , M5 , M6 ).
The current sources I0 are realized as cascode current sources using the PMOS transistors
(M7 ... M10 ). The circuit needs four bias voltages Ub1 ... Ub4 which must be produced by a
bias circuit.
UDD
S
Ub1
M11
M1
U1A
S
D
Ub2
M2
M9
M10
M7
M8
U2
U1B
Ub3
D
S
D
D
M3
M4
S
D
Ub4
M5
M6
S
Fig. 36. Implementation of the folded cascode op amp with double-ended output
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
4 – 32
Folded cascode op amp –
version with extended common-mode input range and single-ended output.
(Complementary input CMOS folded cascode amplifier)
Architecture
This OTA has a single-ended output. Two complementary differential input stages operate in parallel; this modification extends the common-mode input range for full functionality from rail-torail. Complementary cascode stages with current mirror function add the current signals (coming
from the two input stages) at the output node.
The two differential input stages are biased externally via a system of current mirrors (P3, P4,
P5, N3, N4); the cascode stages are self-biased through the “diode-connected” transistor chain
P6, P8, N7, N5.
The example shown below is a tutorial circuit. In practice, the cascode stage should also be
biased externally for better power supply rejection and more stable operating conditions.
Fig. 37. Complementary input CMOS folded cascode amplifier - circuit from [Val94]
Constraints
Channel length L of all transistors equal.
All transistors must operate in saturation.
WP3 = WP4 = WP5;
WP6 = WP7;
WN1 = WN2; WP1 = WP2;
WP8 = WP9;
WN7 = WN8;
WN3 = WN4;
WN5 = WN6.
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
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Specifications
The circuit must meet a series of specifications (specs). This can be seen mathematically as a set
of constraints concerning the circuit properties. The table below gives an example.
Circuit Property
DC gain
Phase margin
Common Mode Rejection Ratio
Offset voltage
Transit frequency
Slew Rate (rise + fall)
Output voltage swing
Power consumption
Power supply rejection ratio
Symbol
AU
phase
CMRR
Uoff
fT
SR
U2
P
PSRR
Constraint
AU > AUmin
phase > phasemin
CMRR > CMRRmin
| Uoff | < Uoffmax
fT > fTmin
SR > SRmin
U2min ≤ U2 ≤ U2max
P ≤ Pmax
PSRR > PSRRmin .
Operating parameters
The above specifications must be guaranteed in the complete range of environmental conditions,
described by the operating parameters. Normally, these are at least
Temperature
Supply voltage
T
UDD
Tmin ≤ T ≤ Tmax
UDDmin ≤ UDD ≤ UDDmax .
Design Task
The design task comprehends
a) the selection of a circuit architecture that is in principle suited to meet the specs. (In the
above case already given);
b) the sizing (dimensioning), i.e. the determination of all design parameters (W and L of all
transistors) of the circuit such that the specs are met under all operating parameters;
c) the validation that the circuit will meet all specs under all operating parameters with simultaneous consideration of the inevitable statistical process variations.
Process variations
The specifications mentioned above must also be met in the complete range of expected production process variations. Neglecting this aspect leads to a loss of yield. The statistical variations
of process steps (lithography, doping, gate oxide formation, etc.) result in variations of the transistor parameter (also SPICE parameters), e.g. ΔW, ΔL, ΔUTH , ΔtOX , etc.
Design-Flow
In detail, the following steps have to be executed for the design of an analog circuit block.
1. Clarify and freeze the requirements. Write the specifications.
2. Select a suitable circuit architecture.
3. Determine test benches for the simulations in order to be able to simulate all specified circuit
properties. Check, how the circuit properties can be evaluated from the simulation results.
4. Make a first sizing of the circuit, e.g. based on simplified hand calculations.
Result: a start design parameter set.
5. Iterative process Nominal design: T = Tnom ; UDD = UDDnom ; model parameters: „typical“;
simulate → evaluate circuit properties → specs met?
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009
4 Elementary Structures of analog IC Building Blocks
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If specs not met: change design parameters → re-simulate → re-evaluate;
If OK: Nominal design complete.
6. Take the influences of the operating parameters and of the process variations into account.
(Design for Manufacturability / Design for Yield). Continue optimizing the design.
7. Draw the layout and regard the design rules. (Run DRC = design rule check)
8. Check layout versus schematic (LVS) and extract all parasitic elements from the layout
(EPC). Re-simulate the extracted netlist again and check, if specs are still met.
9. If necessary perform further optimization steps (points 5 to 8).
10. Document the results.
Exercise
concerning the complementary input CMOS folded cascode amplifier in Fig. 37.
Given
UDD = 1,5 V;
IBias = 10 µA;
RL = 10 MΩ;
CL = 5 pF.
•
•
•
•
•
Considerations concerning the first sizing (Widths of all transistors).
Currents in case of small-signal operation.
Small-signal equivalent circuit and small-signal voltage gain for f → 0.
Dominant pole of differential voltage gain; gain-bandwidth product
Slew rate.
Literature
[Raz01] B. Razavi: „Design of Analog CMOS Integrated Circuits“. Boston, New York, ...: McGraw-Hill, 2001;
ISBN 0-07-238032-2; 684 pages.
[Val94] R. E. Vallee, E. I. El-Masry: “A very high-frequency CMOS complementary folded cascode amplifier,”
IEEE J. of Solid-State Circuits, vol. 29, no. 2, pp. 130-133, Feb. 1994.
* * *
© University of Applied Sciences, Munich, Germany • FK04 • Prof. Dr. Hans L. Zapf • ams_kap_4_en_v5 • 05/2009