World Applied Sciences Journal 32 (9): 1962-1969, 2014 ISSN 1818-4952 © IDOSI Publications, 2014 DOI: 10.5829/idosi.wasj.2014.32.09.1143 Proposal of the Application-Specific Integrated Circuit and Radio Transceiver Choice for the Wireless Endoscopic Capsule Mikhaylov Dmitry, Zhukov Igor, Starikovskiy Andrey, Khabibullin Timur and Konev Vladimir Engineering Centre of the National Research Nuclear University “MEPhI”, Kashirskoye Highway, 31, Moscow, Russian Federation Abstract: This paper overviews advantages and disadvantages of CMOS and CCD matrixes used in endoscopic capsules, specifies requirements that should be met by the microcontroller of the device for the improvement of its effectiveness and concludes on the need of developing the application-specific integrated circuit (ASIC) for the wireless endoscopic capsule. The ASIC microcontroller designed especially for the wireless capsule endoscope will improve the specifications of the device in terms of the recorded images` size and the size of transmitted data as well as reduce the energy consumption. The article also deals with radio transceiver choice as it is essential in terms of energy consumption reduction and the data transmission speed increase. The main ISM protocols are compared, namely NRF, Chipcon, Wi-Fi and Bluetooth. The article also provides the power estimation of the proposed ASIC. Key words: ASIC Microcircuit Controller MICS standard ISM Power consumption INTRODUCTION The wireless capsule endoscopy is a non-invasive way to record images of the digestive tract for use in medical examination and diagnosis [1-3]. A typical capsule is the size and shape of a large pill and contains a miniature camera. After a patient swallows the capsule, the camera takes images as it traverses down the gastrointestinal tract of the patient and the capsule transmits them wirelessly to recorder. The primary use of capsule endoscopy is to examine areas of the small intestine that cannot be seen by other types of endoscopy, such as colonoscopy or esophagogastroduodenoscopy [4]. After the battery of the capsule is exhausted, or the capsule leaves the digestive tract in a natural way, recorder is connected to the gastroenterologist’s personal computer and all the images are transferred by special software on PC's hard drive to be further analyzed. The block-diagram of the capsule is shown in Figure 1 [5]. During the work on this project the first generation of wireless endoscopic capsules was developed. It was based on stock components – image sensor, FPGA Corresponding Author: Image compression Radio transceiver (field-programmable gate array), SDRAM (Synchronous Dynamic Random Access Memory) memory, MCU (Multipoint Control Unit) and radiofrequency transceiver. [6-8]. During the development of the capsule several global problems that cannot be solved without an ASIC (application-specific integrated circuit) were faced, namely: High power consumption (because of the size constraints, the CR1/3N batteries with capacitance at 2 mA and current of 160 mA were used); Very small endoscopic capsule`s size; CMOS (Complementary Metal Oxide Semiconductor) sensor does not have the scaler and internal memory, so the logic should act very fast to read the frame, scale it in FPGA and store it in external memory. Of course, no compression was applied because of the power and size constraints. All these problems resulted in low image resolution (120x160 pixels) and low speed of image taking (2 frames per second). Mikhaylov Dmitry, Kashirskoye Shosse 31, Moscow, 115409, Russian Federation. 1962 World Appl. Sci. J., 32 (9): 1962-1969, 2014 Fig. 1: Wireless endoscopic capsule`s scheme Since capsule endoscopy is a growing medical sphere it was decided to develop the second generation of wireless endoscopic capsule eliminating disadvantages by using ASIC providing among other things data compression. Moreover, it is important to choose the correct radio transceiver for data transmission from the capsule to portable reader to reduce energy consumption and increase the speed of data transfer. Comparison of Cmos and Ccd Matrixes: To visualize the mucosa of gastrointestinal tract of a patient the elemental base of the wireless endoscopic capsule should include photosensitive matrix such as CMOS or CCD (Charge Coupled Device) with an object lens comprising a single lens or a lens system providing the viewing angle of at least 120 degrees. To select the type of photosensitive matrix for the capsule endoscopy it is proposed to compare the specifications of CCD and CMOS matrixes from the point of effectiveness and appropriateness of their use in the endoscopic examination of the digestive tract. CMOS matrix is characterized by low power consumption (up to two orders of magnitude lower than CCD), reading circuits` compactness (simple external circuits or integrated with one circuit with matrix) and "inherited" light-striking resistance of adjacent pixels. CMOS sensor also has a high operating speed (up to 500 frames per second), but it is quite sufficient in CCD. Moreover, CMOS matrix is able to read the image part, but the use of this property (except, perhaps, lighting correction) has not been found yet [9]. CCDs are characterized by the best image quality (but CMOS has photographic quality up to several megapixels that is sufficient for use in the wireless endoscopic capsule), lesser noise, higher sensitivity and dynamic range. Despite the existing opinion there is no significant difference in price between the two types of matrixes with all other features being equal. With respect to the wireless endoscopic capsule the most important features are energy saving and the matrix size. In this case CMOS matrix is more efficient. The smaller sensitivity (in comparison to CCD) is balanced out by the LED assembly and small spaces inside the human body. Therefore, it is proposed to use CMOS image sensor in the wireless endoscopic capsule being developed. However, the CMOS sensor has a disadvantage in the form of a visual defect called rolling shutter (lines displacement during the frame freeze). It occurs when a line or a group of lines is read out while all other lines on the sensor continue to be exposed [10]. It means that the image should be read quickly. The radio channel for data transmission is quite narrow, so the quick reading is often either impossible or leads to a substantial increase in the chip cost. Therefore, the image should be buffered directly on the capsule. Micro Controllers: To improve the performance of the endoscopic capsule of first generation it is necessary to compress the images because the original image will have a heavy weight [11]. For example, a frame with a resolution of 100x100 pixels will weigh 20 kilobyte. It is difficult to perform the transmission through a narrow channel of even 20 kilobytes since the transfer of each byte is a time and energy-consuming process. For this end, the capsule of second generation should contain the path of fast buffering and simultaneous compression of image. Several works on image compressor of the endoscopic capsule have been reported [12-17]. They show good results and present original ideas; however, the possible disadvantages of these proposals may be large capsule power consumption limiting the examination time, limitations of matrixes specifications, etc. As distinct from them, the proposed ASIC is able to perform two types of compression: scale (proportional image shrinking) and compression (data amount reduction). 1963 World Appl. Sci. J., 32 (9): 1962-1969, 2014 Compression and buffering logic is fast-acting, so one of the most energy-consuming. In the shooting mode of two images per second the camera takes up to 5 mA and the transmitter – less than 10 mA (can be reduced to 2 mA). The rest power is consumed by the central path of buffering and compression. The implementation of this path is performed on runoff microcontrollers with memory of at least 32 kilobytes (big memory for microcontrollers), or with high eigen clock frequency of the core, around 100 MHz, or with built-in interfaces DCMI or DMA. DCMI (Digital Camera Interface) is the interface via which the CMOS sensor produces an image; DMA (Direct Memory Access) is the universal channel of direct memory access without the involvement of the central processing unit. The implementation of a single peripheral is useful because core clock frequency does not really matter. Only the rate at which interfaces DCMI or DMA work is important. This is a significant advantage, since the more clock frequency the core has (controller that executes commands) the greater power consumption of the controller (exponential dependence) is. However, if the microcircuit has a specific element responsible, for example, for frame buffering, then this area will consume less. This dependence has been tested on the controllers STM 32F205 and STM 32F207 [18]. The STM 32F20x family is based on the highperformance ARM® Cortex™-M3 32-bit RISC core operating at a frequency of up to 120 MHz. The STM 32F205xx and STM 32F207xx constitute the STM 32F20x family whose members are fully pin-to-pin, software and feature compatible, allowing the user to try different memory densities and peripherals for a greater degree of freedom during the development cycle. [18] STM 32F205 is a two-bit general purpose microcontroller in a small 3x4 mm package that is very convenient for the developed endoscopic capsule of second generation. However, the microcontroller has a significant disadvantage. Although STM 32F205 has the DMA interface that can be configured to accept the image via the DCMI interface and immediately send them to the microcontroller memory, the consumption of the microcontroller is about 40 mA. It means that the total consumption of the wireless endoscopic capsule is about 50 mA (in this case, the charge of the batteries will last for about one hour of capsule operation). STM 32F207 has a built-in DCMI interface and other specifications quite similar to those of STM 32F205. However, STM 32F207 is not available in a miniature package. Fig. 2: Block diagram of the proposed controller. Characteristics of the Proposed ASIC for the Wireless Endoscopic Capsule: Thus, the implementation of the wireless endoscopic capsule of the second generation on the runoff logic does not make sense. Therefore, it is necessary to develop the special ASIC. ASIC is an integrated circuit designed for a particular rather than for general-purpose use. The proposed ASIC chip will take the image via the DCMI interface, compress the data and send them to its own memory. The block diagram of the proposed microcontroller for the wireless endoscopic capsule being developed is presented in Figure 2. The developed ASIC for the wireless capsule endoscope should cover the most energy- and sizeconsuming elements, including data processing and meet the following requirements: 1964 Ihe ASIC should be very energy-efficient – it is possible to provide 10 mA in active mode, but the lower - the better; World Appl. Sci. J., 32 (9): 1962-1969, 2014 Receiving frames from CMOS sensor (in the developed endoscopic capsule OmniVision OV7675 and OV7690 sensors are used); Scaling frames; Compressing frames; Storing frames into ASIC buffer; Transmitting frames to the radiofrequency transceiver (in the developed endoscopic capsule Nordic NRF solution is used); Operate the LED flash (using PWM GPIO (GeneralPurpose Input/Output)); Control the sensor (via SCCB interface); Control the transceiver (via SPI interface); The DCMI and SCCB interface should be compatible with OV7675 and OV7690 sensors; The SPI should operate up to 4MHz. If the ASIC microcircuit will have the general-purpose programmable outputs this will expand its functionality (LED notification, camera and transceiver preset, etc.). To achieve the requirements mentioned above it is proposed to replace the most energy-intensive path of the wireless endoscopic capsule for the component of our own design. Matrix and the transceiver are not replaced intentionally due to the fact that the CMOS sensors are quickly updated (energy consumption is reduced, the sensitivity is increased and the image becomes clearer and sharp). In case the microcircuit implements DCMI interface that is standard for CMOS matrix the matrix may be replaced if necessary. If the controller supports the standard interfaces of communication between chips (UART, I2C or SPI) and has programmable general-purpose outputs the wireless endoscopic capsule will be able to work with any industrial radio transceiver. So, to increase the flexibility of the integrated circuit it is proposed to include UART and I2C interfaces. To add the programmable logic, it is worth adding 8051 core to operate the GPIO, control the sensor, transceiver and LEDs. Radio Transceiver Choice: According to the international law, implantable medical devices should comply with the standard for the Medical Implantable Communications Service, MICS [10]. MICS is the unlicensed standard with very low power that is used for data transmission to perform diagnostic or therapeutic functions associated with the implantable medical devices. MICS has limitations in the frequency range 402-405 MHz and a signal output 25 mW. However, capsule endoscopes do not have to meet the MICS standard because MICS as a standard was developed for devices which stay in human body for a long time (10-15 years) such as cardiac pacemakers, implantable defibrillators, hearing aids, automatic drug delivery systems [19]. In turn, the wireless endoscopic capsule stays in human body for not more than 48 hours and the capsule radiation is significantly smaller than the radiation received from external sources such as Wi-Fi, so it can be ignored. Moreover, 25 mW provide a very low data rate, so it is inappropriate to stick to MICS in the process of the endoscopic capsule development. In this regard, the standard device of ISM (Industrial, Scientific and Medical) band will be used. ISM that does not require licensing opens for use at certain powers frequencies 433 MHz, 868 MHz, 902 MHz and 2.4 GHz. [20] The most common wireless standards of ISM band are Bluetooth, Wi-Fi, 802.15.4 and Zigbee. Standards can have an open protocol such as Bluetooth and Wi-Fi, or be proprietary (closed-protocol). The only requirement for products development in ISM-band is compliance with standards set by regulatory authorities for a particular part of frequency spectrum. The rules are different in different countries. In the United States the rules are set by the Federal Communication Commission, FCC and in Europe – by the European Telecommunications Standards Institute, ETSI. [21] Consider the specifications of radio transceivers operating on proprietary protocols of Texas Instruments Company – Chipcon technology (Chip Connect, ÑÑ) and Nordic (NRF), as well as on open protocols Wi-Fi and Bluetooth (Table 1) [22-25]. As the Table 1 shows, the radio transceivers that exchange data via Bluetooth and Wi-Fi protocols have high energy consumption so are not considered for use in the wireless endoscopic capsule of second generation. The Chipcon and NRF devices have similar specifications but for the endoscopic capsule radio transceiver NRF has been selected, as it has a higher speed of data transfer with similar energy consumption as Chipcon. Power Estimation Calculation Method: Power estimation for ASIC has been performed using the power information of its components. The following memories have been considered: MCU8051: 256 Byte internal data memory (DATA_MEM, single port); 1965 World Appl. Sci. J., 32 (9): 1962-1969, 2014 Table 1: Comparison of the specifications of different ISM radio transceivers NRF CC Wi-Fi Bluetooth Speed Upto 1 Mbit/s Up to 76,8 kbit/s Up to 2 Mbit/s Up to 4 Mbit/s Current, mAReception Transmission Voltage, V Size, mm 10.518 1.9 - 3.6 33x16x11 9.18.6 2.7-3.6 - 38120 3.0 - 3.7 27x18x3.1 10.518 1.7 - 4.8 - Table 2: Different variants for PCLK and MCUCLK PCLK [MHz] MCUCLK [MHz] Peak power [mW] Pavg [mW] Average Idd [mA] Peak Idd [mA] 24 12 12 20 20 8 113.47 56.74 56.74 12.23 12.23 12.23 6.8 6.8 6.8 63.04 31.52 31.52 512 Byte data memory (DATA_MEMx, single port); 4 kByte program memory (PROG_MEMx, single port); 64kByte frame buffer (FRAME_BUFFER_MEM, dual port). correstion factor = 2kByte LUMI_MEM; 2kByte CHROM_MEM. Data Cycle and Average Power Consumption: The whole data cycle from data acquisition to read out of the frame buffer by the MCU can be divided into three phases (Figure 3): JPEG Encoder: 16kByte R2B_MEM; 320Byte R2B_OFIFO0_MEM+ R2B_OFIFO1_MEM; 272Byte DCT0_MEM + DCT1_MEM; 256Byte VLE_HUFFM_TAB0_MEM; 256Byte VLE_HUFFM_TAB1_MEM; 128Byte QUANT_TAB0_MEM; 128Byte QUANT_TAB1_MEM; 768Byte VLC_FIFO0_MEM+VLC_FIFO1_MEM. Phase 1: Transfer of image data from sensor to the scaler, scaling, compression and storing the compressed data into the frame buffer. The following components of the ASIC are active during this phase: scaler with memories, JPEG encoder with memories and frame buffer. The preferred pixel clock is 12 MHz. Phase 2: Read out of the frame buffer by MCU and transfer data to the RF-Chip by SPI. The following components of the ASIC are active during this phase: frame buffer, MCU with memories. The preferred MCU clock is 20 MHz. MCU8051 has 3.9mW@8MHz for a 0.18µm CMOS technology. The dynamic power consumption for a NAND2 (1 gate equivalent) is 0.02232 µW/MHz. The power consumption has been calculated using the following formula: (1) where PGE – power for one NAND2 equivalent; GC – gate count of IP; fclk – clock frequency. The leakage power is in the range of pW and has been neglected. At first the power consumption of the MCU8051 has been calculated using formula (1). Then a correction factor has been calculated using the calculated power consumption for the MCU and the power consumption specified in the documentation: (2) The correction factor is 0.72. It means that the calculated power using the gate-count-method is too high. So the power consumption for the scaler and the JPEG encoder has been calculated using the gate-countmethod and corrected by the factor 0.72. Scaler: PIP = PGE * GC * fclk Pdoc Pcalculated Phase 3: Scaler, encoder, frame buffer and MCU are in power-down state. Because of the small data transmission rate of the RFChip (only 2 Mbit/s) the maximum possible frame rate is 4 fps. Therefore, the shortest duration of one frame is 250ms. During data processing the digital part of the ASIC consumes power only in phase 1 and phase 2. Therefore, the average power consumption is less than the peak power consumption in the active phases. Nevertheless, the clock frequencies for both phases should be as low as possible to reduce the peak power in the active phases, because the integrated voltage regulator has to support this peak power. 1966 World Appl. Sci. J., 32 (9): 1962-1969, 2014 Fig. 3: Phases of the data cycle The power consumption has been calculated for each phase separately using the assigned clock frequency. The resulting power consumption of the digital part has been calculated by averaging the separate power values over the duration of one frame. where FB – byte count of frame buffer; PCLK – pixel clock; CR – compression ratio; MCUCLK – clock for the µC; tframe – duration of one frame. The compression ratio CR is calculated using the following formula: (6) The amount of input data is 614400 bytes for one image with resolution of 640 x 480 pixels, because one color pixel needs two byte (YCbCr). The necessary compression ratio is 9.375 in order to prevent frame buffer overflow. Using a pixel clock (PCLK) of 12 MHz, a MCU clock (MCUCLK) of 20 MHz this calculation results in a power consumption of the digital part of 12.23 mW. The average operating current of the digital core will be 6.8mA at a core voltage of 1.8V. The current consumption of the analogue part has been neglected. The peak power occurs at phase1 with 56.54 mW. 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