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Abstract ² This paper presents a novel architecture for
detecting the frequency of sinusoidal or square-wave signals
with a short settling time. The architecture is based on
detecting consecutive rising edges of the input signal and is
able to generate a dc voltage proportional to the signal
frequency in a time as short as only one input cycle.
Measurements show that it can detect signals with
frequencies up to 2.6 GHz. The chip is fabricated in a 90nm
CMOS process. The total die area is 0.132 mm2 and consumes
6.5 mW from a 1-V power supply.
Index Terms ² CMOS integrated circuits, cognitive
radio, frequency conversion, frequency-locked loops,
reconfigurable architectures.
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