IEEE CPMT Meeting, San Jose, CA
Wafer Level Packaging
L. Nguyen
National Semiconductor Corp.
Santa Clara, CA
Acknowledgments: N. Kelkar, V. Patwardhan,
C. Quentin, H. Nguyen, A. Negasi, E. Warner
Feb-02
1
What is a WLP?
• Significant confusion in the industry over the term
“wafer-level packaging”
• Simple definition: “All packaging and interconnection
must be fabricated on the wafer prior to dicing” →
Bumped chips are WLP?
• Differentiation: Are the devices packaged further prior
to assembly?
• High I/O µPs and ASICs: chips are mounted on chip
carriers before surface mount attachment → Not WLPs
• Small die and/or die with low I/O can be mounted
directly on the final substrate → WLPs
Feb-02
2
1
Outline
•
•
•
•
•
•
•
CSP packaging trends
CSP migration toward wafer level processing
WL-CSP barriers and challenges
micro SMD package construction
Process / assembly flows
Package selection criteria
Future developments
– Lead-free
– Wafer level underfill
• Conclusions
• References
Feb-02
3
Outline
•
•
•
•
•
•
•
CSP packaging trends
CSP migration toward wafer level processing
WL-CSP barriers and challenges
micro SMD package construction
Process / assembly flows
Package selection criteria
Future developments
– Lead-free
– Wafer level underfill
• Conclusions
• References
Feb-02
4
2
Package Forecast
308+
212-304
1998
2003
I/O RANGE
148-208
104-144
72-100
36-68
20-32
4-18
100
10 5
UNITS (M)
Source: Electronic Trend
Publications 1999
Feb-02
10 4
1000
5
Flip Chip Packages
Definitions
1000
UNITS (M)
800
FCOB
FCOO
BGA FC
CSP FC
MCM FC
Direct Attach
FCOB - Flip Chip on Board
FCOO - Flip Chip on Other
600
400
200
0
1997
1998
1999
2000
YEAR
Feb-02
2001
2002
In Package
BGA FC - FC in BGA
CSP FC - FC in CSP
(includes WL-CSP)
MCM FC - FC in MCM
Source: Electronic Trend
Publications 1999
6
3
WLP Growth Projections
8-in WAFER EQUIVALENT
6
2 10
High
Low
6
1.5 10 Source: Electronic
Trend Publications 1999
6
1 10
Total Packages
5
5 10
0
2001
2002
2003
2004
2005
YEAR
Feb-02
Source: TechSearch 2001
7
Form Factor Migration
STANDARD
< 208 lead
⇒
TO
PDIP
⇒
PLCC ⇒
> 208 lead
PGA
⇒
SOP
SOIC
⇒
MSOP
TSSOP
⇒
⇒
QFP
⇒
TQFP
⇒
CSP
BGA
⇒
BGA
⇒
FP-BGA
(1.27 mm)
(1.0 mm)
⇒
SOT
CSP
⇒
⇒
(Leaded/Laminate)
SC70
CSP
(Wafer)
(0.8 mm)
POWER
DPAK, D2PAK, TO263
TO220 ⇒
PACKAGE ENHANCEMENTS
THERMAL
ELECTRICAL
OPTICAL
Feb-02
Embedded heat slug ⇒ Drop-in HS
Shorted leads
MQFP
Aluminum nitride EMC
Shorter leads
Shorter wire bond
⇒ Exposed DAP
Multiple wires
LCC
⇒ Pre-molded
Custom
Custom
⇒
Exposed DAP
⇒ Solder bumps
⇒
CSP
Custom
8
4
Outline
•
•
•
•
•
•
•
CSP packaging trends
CSP migration toward wafer level processing
WL-CSP barriers and challenges
micro SMD package construction
Process / assembly flows
Package selection criteria
Future developments
– Lead-free
– Wafer level underfill
• Conclusions
• References
Feb-02
9
CSP Migration toward Wafer
Level Packaging
• CSP applications are rapidly expanding with drivers in …
– Flash memory
– RAMBUS DRAM
– Analog
• Evolution of CSP technology toward Wafer Level
Packaging due to the following factors:
– Batch fabrication of ICs in arrays
– Test and burn-in in strip and array format; strip format has
continuously increased in manufacturing for higher throughput
– Adaptability of some configurations to wafer level processing
more than others (e.g., possibility for die shrink)
– Emergence of 0.5 mm pitch as the standard for CSPs in memory,
µPs, DSPs, ASICs, and most consumer products
Feb-02
10
5
CSP for Portable Application
…1
Other applications:
Game Gear, Play
Station, Portable
Computers, etc..
Feb-02
11
CSP for Portable Application
…2
Casio Color Wristwatch/Camera
(CPU in RealCSP by IEP Technologies)
Handspring Visor
Edge
(Integrated passive
devices in Ultra CSP)
Feb-02
12
6
Benefits of WL-CSP
Wafer Level-CSP can provide the following benefits:
– Batch processing to lower costs
– Handling and shipping logistics can be streamlined
• Final test is done at the wafer level. Savings in test and logistics can be
equally, or more important, than the manufacturing cost of the package
• ICs can be packaged in the fab and shipped directly to customers for
surface mounting with conventional SMT; shortens TAT; lower
assembly capital costs
• Ability to minimize inventory
Feb-02
– No need for Known Good Die - tested like other ICs
– Functionality can be packed into a form factor as small
as the die
– Wider pitch allows for wider UBM, taller bumps, and
better joint reliability
13
Outline
•
•
•
•
•
•
•
CSP packaging trends
CSP migration toward wafer level processing
WL-CSP barriers and challenges
micro SMD package construction
Process / assembly flows
Package selection criteria
Future developments
– Lead-free
– Wafer level underfill
• Conclusions
• References
Feb-02
14
7
Barriers and Challenges
Like any other new technologies, WL-CSP still faces a
number of hurdles ...
•
•
•
•
•
Infrastructure is not quite established
Wafer bumping is still too costly
High cost for poor yield wafers
High cost for low wafer bumping yields
Who should manufacture the WL-CSP (IC or bumping
house)
• Die shrink strategy
• Solder joint reliability is more critical (since underfill may
not be used in the application)
Feb-02
15
Users of WL-CSPs
• USA
– FCD, Unitive, MCNC, Dallas Semi (1wire), Xicor (Shell BGA, Ultra CSP), National
Semi (micro SMD), Atmel, CMD (Ultra CSP), Alpine Micro Systems (WALEP), TI
(NanoStar)
• Europe
– TU Berlin, IMEC, CS2
• Taiwan
– Apack, Unitive Taiwan, ASE, SPIL, Chipbond, ShellCase (Xintec)
• Korea
– Amkor, Hyundai
• Japan
– IEP/Oki/Casio (Real CSP)
– Fujitsu/Shinko (Super CSP)
– Hitachi (WPP2)
Feb-02
16
8
Outline
•
•
•
•
•
•
•
CSP packaging trends
CSP migration toward wafer level processing
WL-CSP barriers and challenges
micro SMD package construction
Process / assembly flows
Package selection criteria
Future developments
– Lead-free
– Wafer level underfill
• Conclusions
• References
Feb-02
17
Micro SMD
• Micro SMD is a Wafer Level-Chip Scale Package
• No interposer - the die is the package
• Micro SMD has the following advantages:
– No need for underfill (although some OEMs use underfills for
certain applications such as portable consumer products)
– Smallest footprint per I/O - savings in PCB estate
– Leverage standard surface mount assembly technology
– Cost-effective manufacturing and assembly
– Matrix interconnect layout designed at 0.5 mm pitch
– 0.9 mm maximum package height
– Epoxy backcoating provides conventional black marking surfaces
Feb-02
18
9
Package Construction
8
5 mm
7
6
5 mm
1.5 mm
5
4
MSOP-8
1.5 mm
3
2
3 mm
1
0
TSSOP-14 MSOP-8 SOT23-5 SC70-5 microSMD-8
SMT PACKAGE TYPE
Micro SMD: 4, 5, 8, and 14 I/O
Comparison between various SMT
0.5 mm pitch; JEDEC Standard MO-211
packages and the micro SMD
Feb-02
19
Package Construction
Cross-section of an 8 I/O micro SMD
bonded to an organic substrate
Feb-02
Cross-section of a solder
ball
20
10
Outline
•
•
•
•
•
•
•
CSP packaging trends
CSP migration toward wafer level processing
WL-CSP barriers and challenges
micro SMD package construction
Process / assembly flows
Package selection criteria
Future developments
– Lead-free
– Wafer level underfill
• Conclusions
• References
Feb-02
21
Process Flow
Incoming wafer
2nd passivation
Laser mark
Bumping
Test (Wafer sort)
Back side coating
Saw
Tape and reel
Feb-02
22
11
Assembly Flows
micro SMD
Conventional
Package PQFP & TSSOP
CSP
Wafer Fab
Wafer Fab
Wafer Fab
Solder Bumping
Wafer Sort
Wafer Sort
Backside
Coating
Marking
Saw
Saw
Die Attach
Die Attach
Final Test
Wire Bond
Plasma Clean
Saw
Mold
Wire Bond
Tape & Reel
Lead Plating
Mold
Trim & Form
Laser Mark
Final Test
Mark
Tray / Tape &
Reel
Feb-02
5 process steps
1 test step
7 process steps
2 test steps
Saw
Final
Singulated
Test
Tape & Reel
7 process steps
2 test steps
23
Outline
•
•
•
•
•
•
•
CSP packaging trends
CSP migration toward wafer level processing
WL-CSP barriers and challenges
micro SMD package construction
Process / assembly flows
Package selection criteria
Future developments
– Lead-free
– Wafer level underfill
• Conclusions
• References
Feb-02
24
12
Package Selection
• WL-CSPs will replace traditional perimeter leaded packages:
– Initially targets low pin count memory and analog devices; growth
highest in wireless portable applications where small form factor
and weight are crucial factors
– Growth relies on the existing assembly infrastructure
• Criteria for choosing from the many CSP versions?
– From IC supplier: Reduced TAT, inventory size, cost reduction
from transportation and logistics simplification, manufacturability,
and scaleability
– From user: Cost, electrical performance, thermal performance,
manufacturability (assembly), and reliability
Feb-02
25
Package Selection
120
Laminate
CSP
Pin Count
100
80
60
TSSOPs
L/F based
CSP (.5/.65 mm)
40
20
0
MSOPs
SOTs
98
Feb-02
micro SMD
99
Year
00
01
26
13
(Thermal)
300
200
50
MSOP
SOT
LLP
2-layer board
@ 0.7 W
100
2-layer board
@ 0.5 W
150
1-layer board @ 1.0 W
with 50x50 mm Cu
enhancement
250
2-layer board
@ 0.5 W
Junction Temperature (oC/W)
Package Selection
micro SMD
Thermal performance comparison of 8-lead MSOP,
Feb-02
SOT, LLP, and micro-SMD
27
Micro SMD 8 bump package footprint
Package Selection
350
160
(Manufacturability - PCB
Layout)
Feb-02
500
• Both non-solder mask defined (NSMD) and
solder mask defined (SMD) layouts
possible
• Prefer NSMD for (1) tighter control on
copper etch process, (2) minimal stress
concentration, and (3) ease of trace routing
• Recommend 0.5 oz (12 to 15 µm) top layer
copper thickness
• Internal reliability data collected with NSMD
design, 0.5 oz copper and OSP lead finish
• For Au finish recommend to limit Au flash
thickness < 0.5 µm
Copper pad
500
All dimensions are in microns
PCB
Solder mask
Solder Mask
Copper Pad
NSMD
Substrate
SMD
28
14
Package Selection
Micro SMD 8 bump stencil layout
525
525
(Manufacturability - Solder
Paste Printing)
Stencil aperture
R 50
• Recommend laser cut process
followed by electro-polish to ensure
tapering aperture walls to facilitate
paste release.
• Recommend aperture 0.300 mm X
0.300 mm square on a 0.125 mm thick
laser cut + electro-polished stencil
• Type 3 or finer solder paste is
recommended
• With recommended stencil parameters
a vertical standoff of ≥ 0.140 mm in the
final assembly can be achieved
300
225
300
All dimensions are in microns
225
Stencil
Feb-02
29
Package Selection
(Manufacturability - Pick & Place)
• Micro SMD can be placed using
standard SMT placement m/c
Offset
• Part silhouette or bump recognition
can be used to position micro SMD
• Micro SMD aligns with land pattern by
self-aligning of flip chip solder joints
• Component placement height for the
micro SMD should be compensated
for its thickness such that minimal
force (< 50 gm/bump) is exerted on it
when comes in contact with the PCB
Platforms used:
• Micro SMD can be assembled without
Fuji
CP60, CP3; Amistar
solder paste (flux only) in case of
PlacePro 5800; ESEC Micron 2;
rework procedure
Feb-02
Siemens; Universal GSM 30
250
O - Self Aligned
X - Not Aligned
SMT Process Envelope
Flip-Chip Process Envelope
Y-Offset (um)
200
150
100
50
0
0
50
100
150
200
250
300
X-Offset (um)
15
Package Selection
(Manufacturability - Solder Reflow)
• Micro SMD is assembled using
standard reflow process
• Thermal profile at specific board
locations is determined
• Recommend Nitrogen purge
during solder reflow operation
• The micro SMD is qualified for
up to three reflow operations (JSTD-020)
• Rated max peak temperature =
260°C for < 30 sec
• Depending on the type of flux
used assembly may be cleaned
Reflow Furnace: Heller 1700
N2 Capable
Feb-02
31
Package Selection
(Manufacturability - Rework)
• Rework process similar to a
standard BGA or CSP part
• Rework process duplicates the
original reflow profile
• Automated re-work developed
using OK International’s BGA3000 Rework System (includes
localized convection heating with
profiling capability, bottom-side
pre-heater, and part placer with
image overlay alignment)
• Manual rework is possible using
soft tip high temperature pick-up
tool (e.g. tweezers, vacuum wand)
Feb-02
and hot vacuum / air gun
“A Successful Rework Process
for Chip-Scale Pack-ages”, Paul
Wood, OK International, Chip
Scale Review, Vol. 2, No. 4, 1998.
32
16
WL-CSP Failure Modes
Al Pad
Passivation
PI
UBM
High Lead
Eutetic
Solder Mask
Die
NPEU
PIHL
NPHL
Failure Locations
PIEU
Cu Pad
PCB
• Eutectic bump w/o PI showed Al pad peeled off from
die and cratering
• PI showed no significant effect on high lead
• PIEU with 3 mil stand-off showed 50% cumulative
failure rate at 550X
• High lead deformed much greater than eutectic solder
Feb-02
33
Failure Locations
No PI + Eutectic (Al Pad Peel Off)
No PI + High Lead (Failed at Intermetallic)
Feb-02
PI + Eutectic (Joint Failed at PCB)
PI + High Lead (Failed at High Lead)
34
17
Failure Mechanisms
Material
Device
Substrate
CTE
Effect of Manufacturing Variables
Process
Bumping
Solder mask
Passivation
High Pb Solder
CTE/E
Encapsulation
Voids
Underfill
Eutectic
Adhesion
Time Dependent
Creep Deformation
Temperature Cycle
Wetting
Time Independent
Plastic Deformation
Height
Cap Dia
Size
Thermal Shock
Loading
Solder Joint
Fatigue Life
Underfill DNP
Substrate
Feb-02
Voids
Solder Joint
Silicon
Thickness
Geometry
Cause and Effect for Solder Joint Fatigue
35
Outline
•
•
•
•
•
•
•
CSP packaging trends
CSP migration toward wafer level processing
WL-CSP barriers and challenges
micro SMD package construction
Process / assembly flows
Package selection criteria
Future developments
– Lead-free
– Wafer level underfill
• Conclusions
• References
Feb-02
36
18
Development of Pb-Free Solders
(Ternary Systems)
SYSTEM
KNOWN COMPOSITIONS
Tm (o C)
Sn-Ag-Bi
91.8Sn/3.4Ag/4.8Bi (E)
92Sn/3.3Ag/4.7Bi
43Sn1Ag/56Bi (E)
83.5Sn/2.5Ag/14Bi
94Sn/2Ag/4Bi
92.5Sn/1.5Ag/6Bi
211
213-215
136.5
142-218
223-231
188-229
88.0Sn/3.2Ag/8.8In
83.9Sn/4.1Ag/12In
77.2Sn/2.8Ag/20In
200-207
190-200
178-189
93.6Sn/4.7Ag/1.7Cu (E)
96.75Sn/1.25Ag/2Cu
96.5Sn/0.5Ag/3Cu
95.65Sn/0.35Ag/4Cu
94.75Sn/1.25 Ag/4Cu
216
224-260
225-296
227-332
224-260
Sn-Ag-In
Sn-Ag-Cu
SYSTEM
KNOWN COMPOSITIONS
Tm (o C)
Sn-Ag-Zn
95.5Sn/3.5Ag/1Zn
217
Sn-Bi-In
70Sn/20Bi/10In
80Sn/10Bi/10In
143-193
163-209
Sn-Bi-Sb
75Sn/19Bi/6Sb
140-220
Sn-Bi-Zn
78Sn/16Bi/6Zn
41.7Sn/57Bi/1.3In
134-196
127
Sn-Cu-In 75Sn/0.01-9.5Cu/0.01-6In/addition 209-214
Feb-02
37
Consortia Recommendations
• NCMS: 96.5Sn/3.5Ag; 91.7Sn/3.5Ag/4.8Bi; 42Sn/58Bi
• NEMI: Sn/Ag/Cu without Bi is best in reliability (217-221oC)
• Brite Euram: 95.5Sn/3.8Ag/0.7Cu (for general purpose soldering);
99.3Sn/0.7Cu; 96.5Sn/3.5Ag; Sn/Ag/Bi
• Germany: 96.5Sn/3.5Ag; 99Sn/1Cu
• UK (Department of Trade & Industry): options depend on the
applications:
– automotive/military
– industrial/telecoms
– consumer
Sn/Ag/Cu(Sb)
Sn/Ag/Cu, Sn/Ag
Sn/Ag/Cu(Sb), Sn/Ag, Sn/Cu, Sn/Ag/Bi
• Japan Electronics Industry Development Association:
– Sn/Ag/Cu (before Pb-free components available)
– Sn/Ag/Bi (after Pb-free components available)
Feb-02
38
19
Micro SMD Adoption Path
Sn/Ag/Cu
Sn/Pb
• Best solder joint
performance results with
homogeneous combination
of lead-free solder.
B: Sn/Ag/Cu • Standard Sn/Pb
P: Sn/Pb
packages can be mounted
with lead-free paste.
B: Sn/Pb
• Worst solder joint
P: Sn/Ag/Cu performance results with
lead-free packages with
B: Sn/Pb
Sn/Pb paste and Sn/Pb
P: Sn/Pb
reflow.
Bump Paste Sn/Pb Sn/Ag/Cu
B: Sn/Ag/Cu
P: Sn/Pb
B: Sn/Ag/Cu
P: Sn/Ag/Cu
B: Sn/Pb
P: Sn/Ag/Cu
220oC
260oC
260oC
220oC
260oC
220oC
Feb-02
39
Outline
•
•
•
•
•
•
•
CSP packaging trends
CSP migration toward wafer level processing
WL-CSP barriers and challenges
micro SMD package construction
Process / assembly flows
Package selection criteria
Future developments
– Lead-free
– Wafer level underfill
• Conclusions
• References
Feb-02
40
20
Wafer Level Underfill
Bottom View - Micro SMD 8
I/O with Wafer Level Underfill
Side View - Micro SMD 8 I/O
with Wafer Level Underfill
Top View - Micro SMD 8 I/O with Wafer
Level Underfill is assembled on PCB
Over View - Micro SMD 8 I/O with
Wafer Level Underfill
Feb-02
41
Wafer Level Underfill
State of the Art - Conventional Underfill
Process
DEVICE
Align and Place
SUBSTRATE
Solder Bump
Reflow
Underfill Dispense
Underfill Cure
Process Flow
1. Align bumped device with substrate pads
2. Reflow assembly to create solder joint
3. Dispense underfill and flow under device
4. Cure underfill
Feb-02
42
21
Wafer Level Underfill
State of the Art - Conventional Underfill Process
Process Disadvantages
1. Slow - 4-5 minutes (for 6 mm die w/ 3mil gap)
2. Performed at device level - can be bottleneck
3. Lengthy cure (1-4 hours) - separate process
4. Sensitive to air entrapment (voids)
Material Disadvantages
Feb-02
1. Thermoset materials - not reworkable
2. Material properties - often at odds w/ process requirements
a. High filler loading - slows flow under die
b. Low filler loading - susceptible to popcorning
3. Cure sensitive properties - short floor life
4. Solvent use can cause voiding or bubbling
43
Wafer Level Underfill
State of the Art - Fast Flow Underfill Process
Process Disadvantages
Sensitive to material/device wetting characteristics
Feb-02
Underfill of Test Chip Q Underfill of Test Chip Q with mixed array
with full array (13 mm die, (13 mm die, 25 µm gap, 200 µm & 400 µm
25 µm gap, 250 µm pitch)
pitches)
44
Material - Dexter FP4511
Material - Dexter FP4511
22
Wafer Level Underfill
State of the Art - Fast Flow Underfill Process
Process Disadvantages
Sensitive to air entrapment
Feb-02
Small void formed during
underfill of Test Chip Q
(perimeter array) with
Namics U8433
Large void formed
during underfill of Test
Chip Q (full array) with
Dexter FP4511
45
Wafer Level Underfill
State of the Art - No Flow Underfill Process
Process
1. Dispense underfill over entire bond area
2. Align and place die
3. Cure underfill
DEVICE
SUBSTRATE
Underfill Dispense
Feb-02
SUBSTRATE
Align and Place
Underfill Cure
46
23
Wafer Level Underfill
State of the Art - No Flow Underfill Process
Process Disadvantages
1. Alignment difficult - bond pads covered
2. Underfill can be retained between solder ball and pad
causing mechanical or electrical joint failure
3. Process still performed at package level
4. Susceptible to voiding
5. Potential to “float” die w/o accurate dispensing
Material Disadvantages
1.
2.
3.
4.
Feb-02
High reliability materials still in R&D
Extremely high CTE (up to 80 ppm/K)
Potential for moisture absorption
Non-reworkable
47
Processing Issues
Current Process Flow Proposed Process Flow
a) Bumped and Coated wafer
a) Saw Wafer into Die
Underfill
Wafer
Wafer
b) Assemble Die
and Substrate
b) Gel Underfill
Apply heat
Die
Wafer
Substrate
c) Reflow Solder
c) Saw Wafer into Die
Apply heat
Die
Substrate
d) Apply Underfill
Wafer
Dispensing
Needle
e) Cure Underfill
Apply heat
Feb-02
d) Assemble Die
and Substrate
Die
Die
flow
Substrate
Screen Printing
Underfill
Substrate
e) Simultaneously Reflow
Solder and Cure Underfill
• High viscosity - material does not
flow through the screen ahead of
the squeegee and ruin the print
resolution
• Pseudoplastic - material flows
through the screen under high
pressures exerted by the squeegee
• High solids - more efficient
material transfer; thicker films;
reduced waste
Apply heat
Die
Die
Substrate
Substrate
48
24
Processing Issues
a)No stress at gel temperature
Coating - Large CTE
Wafer - Small CTE
Stress-Induced Warpage
b)Shrinkage at ambient temperature
Coating
Large
Shrinkage
Wafer
• Wafer curvature - planarity is
critical to the dicing process.
Small Shrinkage
c)Stress at ambient temperature
Coating
Wafer
Stress on Wafer
No contact between
solder ball and pad
Die
– Caused by CTE mismatch
between “soft cured” underfill
and the silicon wafer.
– Primary factors: wafer
thickness, film thickness,
modulus of wafer, modulus of
film, type of coating (e.g., blanket
vs. patterned).
Substrate
Feb-02
49
Processing Issues
3
- Wafer: 200 mm (8”)
- Nominal thickness: 0.77
mm
- Underfill coating: 0.11
mm (4 mils)
- Two underfills: 1 and 10
GPa
Curvature can reach 0.2x
(E=1 GPa) to 2.6X
(E=10 GPa) of a 200
mm wafer nominal
thickness
NORMALIZED CURVATURE
Wafer Warpage
2
1
0
0
1
2
3
4
5
6
COATING PATTERN
Feb-02
50
25
Processing Issues
Underfill
Hub
Blade
Wafer
Kerf
Tape
Dicing-Induced Damage
Negligible impact
• Potential problems
encountered during dicing @
Chipping @ die edges 30-40 kRPM
– Chipping: minimal on coated
side; potentially high on back
side.
Irregular kerf width/blade – Blade loading: accelerated blade
loading
wear / life; irregular cut widths;
heat generated caused melting of
Reflow of material into kerf the material into the kerf.
– Film delamination: poor
adhesion accentuated by the
shearing of the wafer.
Film delamination
Feb-02
51
Processing Issues
Silicon die
Underfill
Solder Wetting Under
Constrained Conditions
Substrate
Initial State
At Temperature T
Final State
Feb-02
• Wetting of solder pad potentially poor / incomplete pad
wetting due to the presence of
the underfill surrounding the
solder balls.
• Primary factors: surface tension
of underfill / solder, weight of
die, external force, coating
thickness.
52
26
Outline
•
•
•
•
•
•
•
CSP packaging trends
CSP migration toward wafer level processing
WL-CSP barriers and challenges
micro SMD package construction
Process / assembly flows
Package selection criteria
Future developments
– Lead-free
– Wafer level underfill
• Conclusions
• References
Feb-02
53
Conclusions
• WL-CSP is driven by imperatives such as:
–
–
–
–
Packaging cost
Production, handling, and testing logistics
Functionality, performance, size, and weight
Integration and interconnect density
• WL-CSP such as the micro SMD is highly suitable for
low pin count analog applications (cellular phones,
cameras, flash minicards, portable products, etc.)
• Criteria for selection of a particular form factor and pin
count will depend on both IC suppliers and end
customers readiness
• Next advances in lead-free and wafer level underfill
Feb-02
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Outline
•
•
•
•
•
•
•
CSP packaging trends
CSP migration toward wafer level processing
WL-CSP barriers and challenges
micro SMD package construction
Process / assembly flows
Package selection criteria
Future developments
– Lead-free
– Wafer level underfill
• Conclusions
• References
Feb-02
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References
• General WLP books/articles:
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–
–
–
–
–
–
–
TechSearch CSP/BGA Update Service
Prismark (market research, trends)
Electronic Trend Publications (market research, trends)
IEEE Transactions on Advanced Packaging, Vol. 23, No. 2, May 2000
issue.
“Wafer Level Packaging Has Arrived,” P. Garrou, Semiconductor
International, pp. 119-128, October 2000.
Chip Scale Packaging, J. Lau and S. W. R. Lee, Eds., McGraw Hill (1999).
“Wafer Pre-Applied Encapsulant Materials and Processes,” Q. Tong, S-H
Hong, L. Nguyen, H. Nguyen, and A. Negasi, 52nd Electron. Comp. & Tech.
Conf., May 28-31, San Diego, CA (2002).
“Lead-free WL-CSP: Assembly and Reliability,” V. Patwardhan, N. Kelkar,
and L. Nguyen, 52nd Electron. Comp. & Tech. Conf., May 28-31, San Diego,
CA (2002).
• TC-18: Wafer Level Packaging
Feb-02
– http://cpmt.org/tc/tc18.html
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