A 0.07µm CMOS Flash Analog-to-Digital Converter
for High Speed and Low Voltage Applications
Jincheol Yoo
Kyusun Choi
Jahan Ghaznavi
Department of Computer Science and Engineering
Pennsylvania State University
University Park, PA 16802
{jyoo,kyusun,ghaznavi}@cse.psu.edu
ABSTRACT
A CMOS flash analog-to-digital converter (ADC) designed
for high speed and low voltage is presented. Using the
Threshold Inverter Quantization (TIQ) comparator technique, a flash ADC can be applied to low supply voltage. A
fat tree encoder that has signal delay of O(log2 N) is used for
performance. A 6-bit and an 8-bit flash ADC were designed
with 0.07 µm CMOS technology and 0.7 V power supply
voltage. The 6-bit ADC operates up to 4.76 giga samples
per second (GSPS) with 11.35 mW power consumption. In
case of the 8-bit ADC, it consumes 48.90 mW at its high
speed 3.57 GSPS.
Categories and Subject Descriptors
B.7.1 [Integrated Circuits]: Types and Design Styles—
VLSI
General Terms
Design
Keywords
Analog-to-Digital Converter, Flash ADC, TIQ Comparator,
Low Voltage, High Speed, Fat Tree Encoder
1.
INTRODUCTION
Currently, the minimum channel length of the transistors
is 0.13 µm. This will be scaling down to 0.065 µm in 2007
according to the roadmap of semiconductors [1]. This shortening of the minimum channel length of the transistors results in reduction of the power supply voltage to 0.7 V . Also
system-on-chip (SoC) trend forces analog circuits to be integrated with digital circuits. To follow both the scaling down
of the minimum channel length of the transistors and SoC
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trend, analog-to-digital converters (ADCs) should be operated at low voltages, especially below 1.0 V for portable
devices. However, the minimum supply voltage for the analog circuits predicted in the roadmap [1] does not follow the
digital supply voltage reduction. Analog supply voltages between 2.5 V and 1.8 V will still be used by 2007. Therefore,
it is a great challenge to design an ADC that operates at a
low supply voltage because of relatively high threshold voltage of transistors with short channel length transistors. As
a result, an ADC should operate in a small full scale range
voltage (VF SR )
Many techniques have been devised to overcome this design challenge of low voltage operation, such as low threshold
devices [2], the bootstrap technique [3], switched-opamps [4],
and special biasing schemes [5]. In addition to these techniques, several design strategies for low voltage ADCs are
introduced [6, 7, 8, 9]. All of these low voltage techniques
have been implemented with additional or modified circuits
to all known ADC architectures like the successive approximation, pipeline, flash, and Σ∆ modulator.
This paper describes a CMOS flash ADC with an alternative technique for high speed and low voltage applications. The technique is called Threshold Inverter Quantization (TIQ) since two cascading inverters are used as a voltage comparator. The TIQ comparator architecture has been
shown in the authors’ previous work [10, 11] with 0.25 µm
standard CMOS technology. All circuit blocks have been
redesigned with 0.07 µm technology for low voltage applications. Also, the encoder circuit has been changed from
ROM type to fat tree encoder [12] for high speed.
2. ADC ARCHITECTURE
The proposed ADC is a full flash type with 2n − 1 TIQ
comparators for n-bit resolution. The block diagram of the
ADC is shown in Figure 1. An analog input voltage (Vin )
goes through each TIQ comparator, and then digital output
goes to a gain booster to provide full voltage swing. The gain
boosters are all identical, and each consists of two cascading minimum size inverters. The first encoding step occurs
at ‘01’ generator. The gain booster outputs (thermometer
code) are changed to 1-out-of-n code. Next, the 1-out-of‘n’ code is converted to an appropriate binary code through
the fat tree encoder. In the following subsections, two main
components of the TIQ flash ADC will be discussed in detail.
Analog Input
Voltage
Thermometer
Code
1-out-of-n
Code
Binary
Code
Fat Tree
Encoder
‘01’ Generator
max Vm
MSB
Vin
TIQ
Comparator
Gain
Booster
‘01’
Generator
Fat Tree
Encoder
LSB
min Vm
Figure 1: Block diagram of the ADC
TIQ Comparator
Gain Booster
2.1 TIQ Comparator
The TIQ comparator has been designed for high speed
ADCs in SoC applications. As shown in Figure 1, its architecture is very simple and fast compared to the differential input voltage (DIV) comparator. The inverter, which
is known for the fastest digital circuit, has been used to
compare the Vin to the built-in reference voltage, Vref .
The key difference between the DIV comparator and the
TIQ comparator is how to provide the Vref . Most DIV comparators utilize the external Vref source such as a resistor
ladder circuit. In the TIQ comparator, all 2n − 1 reference voltages for n-bit ADC are internally determined by
the size of each inverter. All DIV comparators are identical, duplicated for 2n − 1 times. On the other hand, each
TIQ comparator is different from all the others. Each comparator has unique reference voltage (Vm ). The 2n − 1 comparators’ reference voltages equally divide full scale range
voltage, VF SR . Achieving an optimal layout of such TIQ
comparator is very time consuming. Automatic generation
of the TIQ comparator has been developed by the authors
to reduce the linearity errors [13]. Figure 2 shows an 8-bit
TIQ flash ADC layout from the automatic generation. One
can notice systematic descending and ascending size of the
TIQ comparator.
The main advantage of the TIQ comparator is highly
adaptable for the high speed and low voltage. Especially, it
does not need any external Vref source. These advantages
enable the TIQ comparator to operate at a low voltage with
ultra-fast speed. On the other hand, the process parameter variation causes offset and gain errors due to internally
fixed reference voltages. Also the noise problem is one of the
challenges of the single-ended input TIQ comparator. According to the previous fabrication and measurement of the
TIQ flash ADC chip, this noise problem affects the sampling
rates of the ADC. Now, the authors are planning to design
an alternative comparator that reduces the noise problem.
Figure 2: 8-bit TIQ flash ADC layout
The 1-out-of-8 code, which is the output of the ‘01’ generator, is represented at the leaf nodes (from a7 to a0 ) of the
tree. The 3-bit binary output (d2 , d1 , and d0 ) is located at
the root of the tree. The output is obtained by a logical
ORing of the leaf nodes depending on the truth table shown
on the right in Figure 3. As shown in the tree, the number
of edges increases from leaf to root. So, this new encoder
type is named the fat tree encoder.
The fat tree encoder’s signal delay is O(log2 N), much
faster than the ROM type encoder. Also, all multiple OR
gates can be changed to NOR and NAND gates for more efficient implementation. Moreover, the fat tree encoder can
be easily pipelined at each height in the tree. However, the
fat tree is a 3-dimensional circuit topology, the design automation of the fat tree encoder is very challenging.
3. SIMULATION RESULTS
The proposed TIQ flash ADC has been simulated with
HSPICE 0.07 µm predictive model from the University of
California at Berkeley. Table 1 shows the summary of simulation results. The 6-bit and the 8-bit ADC can respectively operate at the speed of 4.76 GSPS and 3.57 GSPS
without any missing codes. The SPICE simulation result
of the 8-bit ADC is shown in Figure 4. Both the differential non-linearity error (DNL) and the integral non-linearity
a7
a6
a5
a4
2.2 Fat Tree Encoder
The previous encoder for the TIQ flash ADCs [10, 11]
was a ROM type, which has signal delay of O(N). The
encoder was the bottleneck of the TIQ flash ADC. A new
tree type encoder architecture has been developed by the
authors [12]. This new architecture is necessary for high
speed applications.
Figure 3 shows an example of the 3-bit fat tree encoder.
a3
d2
d1
d0
a7
a6
a5
a4
a3
a2
a1
a0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
d(2:0) 000 001 010 011 100 101 110 111
a2
a1
a0
d2 = (a4 + a5) + (a6 + a7)
d1 = (a2 + a3) + (a6 + a7)
d0 = (a1 + a3) + (a5 + a7)
Figure 3: Example of the 3-bit fat tree encoder
Table 1: Simulation results
Vin
* hspice file created from 8b007adc_flat.ext - technology: mmi07
400m
300m
bit7
600m
bit6
0.05
0.05
INL(LSB)
0.1
0
−0.05
0
−0.05
−0.1
0
20
40
output code
60
−0.1
0
20
40
output code
60
(b) INL of the 6-bit
(a) DNL of the 6-bit
0.2
0.2
0.1
0.1
0
−0.1
0
−0.1
0
600m
−0.2
0
0
600m
bit5
0.1
INL(LSB)
8-bit
0.07 µm
0.7 V
3.57 GSPS
48.88 mW
0.24 V - 0.46 V
0.81 mV
185.1µA
0.1684 LSB
0.1234 LSB
0.0625 mm2
DNL(LSB)
6-bit
0.07 µm
0.7 V
4.76 GSPS
11.32 mW
0.24 V - 0.46 V
3.43 mV
78.5µA
0.0075 LSB
0.0062 LSB
0.0170 mm2
DNL(LSB)
resolution
CMOS tech.
power supply
max. speed
power consumption
VF SR
VLSB
leakage current
DNL
INL
ADC Area
50
100
150
output code
200
(c) DNL of the 8-bit
0
250
−0.2
0
50
100
150
output code
200
250
(d) INL of the 8-bit
bit4
600m
0
Figure 5: Linearity errors of the ADC
bit3
600m
0
bit2
600m
3.2 Voltage and Temperature Variations
0
bit1
0
bit0
600m
600m
0
0
20n
40n
Time (lin) (TIME)
60n
Figure 4: SPICE simulation result
error (INL) shown in Figure 5 are less than 0.01 LSB for
the 6-bit and 0.20 LSB for the 8-bit ADC. Table 2 compares these results with other ADCs. The TIQ flash ADCs
show the highest speed but they also show the largest power
dissipation compared to the other low voltage ADCs.
3.1 Component power consumption
The other ADCs in Table 2 consume small amounts of
power. The TIQ flash ADC architecture is a pure flash
type and all 2n − 1 comparators turn on at the same time.
The TIQ flash ADC dissipates more power than the others.
Table 3 shows the component power consumption of the TIQ
flash ADC at the maximum sampling rate.
Most power consumption of the ADC occurs in the comparator as expected. Especially, the comparator’s power dissipation becomes very large as it changes to the higher resolution. Therefore, comparator section is the critical component for low power consumption. It is hard to reduce power
consumption in the flash architecture when the comparators are operating. However, the power consumption can be
managed in the TIQ comparator since the TIQ comparator
can be easily turned off. The authors are now working this
power management method in the TIQ flash ADC to save
power consumption.
In the TIQ flash ADC implementation, there are two problems that affect changes in the offset, gain, and linearity:
static variation and dynamic variation. The static variation is the process variation. The dynamic variations are
power supply voltage and temperature variation. The internal reference voltages, which are fixed by the size of the
transistors, are the cause of these variations. To correct
them, one can use digital signal processing (DSP) on the
ADC output. Unfortunately, there is no representative process parameters available for 0.07 µm technology. So, only
dynamic variations have been simulated.
Table 4 shows the variation parameters from the 8-bit
ADC simulation results as a result of the power supply voltage and temperature variations. The “default” condition is
a 0.7 V power supply voltage at 25o C. There are changes in
both the offset and gain variations. The temperature variations show an especially large amounts of expansion (at
85o C) or contraction (at −40o C) of full scale range of the
reference voltages. As a result of these changes, all characteristics of the ADC including the sampling rates are degraded. However, by using the optimal design method [13],
the DNL of the ADC shows less sensitive over the variations
than the INL. A new design method for INL optimization is
currently investigated to prevent the degrading performance
of the ADC as the temperature or power supply varies.
4. CONCLUSIONS
The TIQ flash ADC has been simulated with the 0.07 µm
CMOS technology to verify the functionality at low power
supply voltage. Both the 6-bit and the 8-bit ADC worked
correctly at a 0.7 V with high speed sampling rate and small
values of DNL and INL. The static and dynamic variations
affect the gain and offset errors. The overall simulation
shows that the TIQ technique can be adapted to the future
CMOS technology.
Table 2: Comparison with other ADCs
ADCs
TIQ
TIQ
[2]
[3]
[4]
[5]
[6]
[7]
architecture
flash
flash
Σ∆
successive approximation
pipeline
successive approximation
flash-interpolation
Σ∆
resolution
6-bit
8-bit
10-bit
10-bit
9-bit
8-bit
6-bit
14-bit
power supply
0.7 V
0.7 V
1.0 V
1.0 V
1.0 V
1.0 V
0.8 V
1.1 V
Table 3: Component power consumption
TIQ flash ADC
total
comparator
gain booster
‘01’ generator
fat tree encoder
6-bit (mW )
11.314 (100 %)
10.618 (93.8 %)
0.043 (0.4 %)
0.088 (0.8 %)
0.565 (5.0 %)
8-bit (mW )
48.882 (100 %)
47.983 (98.1 %)
0.083 (0.2 %)
0.085 (0.2 %)
0.731 (1.5 %)
Table 4: Power supply voltage and temperature
variations from the 8-bit ADC
0.665 V
0.735 V
−40o C
85o C
default
5.
min. Vm
0.239831
0.264819
0.276854
0.226461
0.251036
max. Vm
0.431048
0.491096
0.423492
0.490242
0.456555
DNL(LSB)
0.1874
0.1446
0.2345
0.1745
0.1684
INL(LSB)
0.7083
1.3165
2.1280
2.9707
0.1234
ACKNOWLEDGMENT
The authors wish to thank the Device Group at UC Berkeley which provided the 0.07 µm Berkeley Predictive Technology Model (BPTM)SPICE model.
6.
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