THE ANALOGUE PLATFORM OF DIGITAL DEFINED RADAR
SLOBODAN SIMIĆ
Military Academy, Belgrade, Serbia, simasimic01@gmail.com
ZORAN GOLUBIČIĆ
Peripolis – elektronika, Belgrade, Serbia, golubicic.zoran@gmail.com
ALEKSA J. ZEJAK
RT-RK Computer based systems, Novi Sad, Serbia, aleksa.zejak@rt-rk.com
Abstract: Main component in software defined radar, responsible for radar signal processing and signal generation is
FPGA circuits. Internal clocks generators inside the FPGAs are capable to operate at the speeds of few tens of
gigahertz. Unfortunately, these signals are not available at the FPGA pins. High speed data streams available at the
I/O pins are automatically coded by FPGA transceivers and transceiver bit streams are not suitable for the application
in form of radar signals. Additional problem could be the price and availability of FPGA components with gigabit
transceiver. Digitally generated analog signals are limited in spectrum and could be directly applied in VHF and UHF
radars. In order to apply digitally generated analog signals in X, Ku or Ka radars, analogue platforms fully transparent
to low frequency radar signal (generated digitally by FPGA) is described. Proposed architecture performs required
functionality by minimizing the number of the analogue components. There are no requirements for analog hardware
programming i.e. all flexibility is achieved by digital components. Proposed analogue platform enables independent
development, testing and production of analogue hardware and digital hardware and software components.
Key words: Up converter, Down converter, FPGA, Frequency reference
and convert Rx spectrum to IF level. Rx signal should be
undersampled by high bandwidth AD converter.
Simplified architecture is presented at the figure 1.
Further text will analyze how we can simplify analog
components and improve their characteristics exploiting
flexibility of digital platforms.
1. INTRODUCTION
Fast development of FPGA circuit has moved the radar
signal processing problems from analog to digital world
[1, 2]. Signal generation and signal filtering are performed
inside the FPGA processor and analog electronics are
minimized. Flexibility obtained by digital signal
processing should be supported by flexible analogue
platform intended for efficient UP and DOWN signal
conversion. In this paper one solution based on wideband
analogue components is described.
2. RADAR ARCHITECTURE
Already available and standard FPGA circuits operating
at high clock rate are capable to generate spectrum up to
200MHz. Output data rate of 500MSample/s is
compatible with available DA converters. New integrated
circuits containing DA converters with output data rate of
1GSample/s, interpolation filters and numeric IQ
modulator enable generation of digitally generated IF
spectrum up to 400MHz [3]. Spectrum of few hundred of
megahertz enables radar operation in frequency agile
mode or spread spectrum mode. It means that all radar
function could be generated and tested at digital level.
Analogue platform only has to convert Tx spectrum to
carrier frequency, amplify Tx signal, amplify Rx signal
Figure 1. Radar block scheme
3. LOCAL OSCILLATOR
Thanks to the capability of digital platform to generate
radar signals at different carrier frequency local oscillator
applied in frequency converter could be single frequency
microwave oscillator. Suitable choice of oscillator
407
Table 1. LO frequency generation for diferent band
components enables optimum phase noise. These phase
noise is not degraded by PLL component influence
(especially when small frequency resolution is required).
Phase noise depends on reference oscillator phase noise
and number frequency multiplication. At the larger
frequency offset from carrier phase noise depends on
VCO phase noise and PLL filter components. Simplified
block scheme of local oscillator is presented at the Fig. 2.
In order to optimize phase noise, reference frequency has
to be as high as possible. Higher frequency XCO has
worse phase noise than low frequency XCO, but
degradation of phase noise with higher number of
multiplication is higher. Values of reference frequency
about 100MHz are optimal. Limitation in reference
frequency originates from maximum operating frequency
of phase/frequency comparator in PLL circuit. Values
slightly higher than 100MHz are usual.
Band
L
(1.2-1.4GHz)
S
(2.7-3.1GHz)
C
(5.4-5.9GHz)
X
(8.6-9.5GHz)
Ku 13.8GHz
Ku
(15.5-17.5GHz)
Ku
(15.5-17.5GHz)
Ka
(33-36GHz)
VCO freq.
Multipl.
factor
LO freq.
1.6GHz
1
1.6GHz
3.2GHz
1
3.2GHz
6.4GHz
1
6.4GHz
3.2GHz
3
9.6GHz
6.4GHz
2
12.8GHz
3.2GHz
X3 X2
19.2GHz
1.6GHz
X3 X3
14.4GHz
3.2GHz
X3 X2 X2
38.4GHz
4. UP CONVERSION PROCESS
Figure 2. The local oscillator block scheme
FPGA circuits and appropriate DA converter (including
converters with interpolation filters) could generate signal
spectrum in the range up to 400MHz. In case that FPGA
generates BB signal, UP conversion process could be
applied at the output frequency. Commercially available
components enable direct modulation up to 20GHz [5]. In
case that wider frequency agility is necessary, output
carrier will be generated by the LO frequency and IF
frequency carriers. Fig.3. presents scheme of two possible
modulation methods.
Optimum value for frequency dividers should be 2n
because binary counter introduces minimum noise in
PLL. It means that values of 8, 16, 32, 64, 128 etc
should be applied. Commercially available PLL with
binary divider operating up to 7GHz are usual. It means
that maximum number of dividing is 64.
As a VCO, solutions with higher Q resonators will
minimize the overall phase noise. In that sense microwave
or millimeter wave oscillators based on coaxial or
waveguide high Q resonators should be the best solution.
Binary divider is also available in components for high
frequency. But the prices and dimension of these
components are not suitable for synthesizer design.
Optimum solution should be application of CRO that is
operable up to 6.4GHz. Dimensions and prices are
relatively low and acceptable for synthesizer realization.
Frequency multipliers at higher frequencies are realized
as X2 and X3 multipliers. Output frequency of X3
commercially available multipliers is limited to 16 GHz.
There are passive and active frequency multipliers.
Combination of VCO frequency and multiplication
number can generate optimum frequency for different
band LO. Examples are presented at the Table 1.
According to Table 1 it is clear that maximum IF
frequency should be below 6GHz what is the acceptable
frequency for commercially available frequency
converter. Application of IQ up converters compatible
with Tx DAC operable up to 6GHz [4] could be applied
for IF frequency generation. It can relax requirements for
microwave filters especially at millimeter band radars. In
order to manipulate with different IF frequencies good
solution for synthesizer should be the application of
unique 6.4GHz VCO and divided frequency as references
for frequency multiplication. PCB with these sources
could be assumed as universal source for all bands.
Figure 3. Two possible modulation ways
Examples for different band radar up converter are
presented at the Table 2.
408
conversion. IF frequencies between 100MHz and
300MHz are under sampled. Bandwidth of the AD
converter has to be over 300MHz. Sampling rate depends
of instantaneous signal bandwidth. The instantaneous
signal bandwidth is limited by minimum IF frequency.
Instantaneous bandwidth is of 100MHz (1.5m range
resolution is minimum) when signal spectrum is
positioned between 200 and 300MHz. In that case
sampling rate is 200MSample/sec. I and Q input are not
necessary. The schematic is presented at the Fig.5.
Table 2. Examples for different band radar up converter
IF frequency from 200 to 400 MHz is selected,
1600MHz carrier is IQ modulated. L and S band
L
radars are not massive radar and powerful FPGA
could be applied
IF frequency from 100 to 400 MHz is selected,
3200MHz carrier is IQ modulated. L and S band
S
radars are not massive radar and powerful FPGA
could be applied
BB frequency from 0 to 250 is selected. 5.65GHz
carrier is IQ modulated by 250MHz BB spectrum
C
from FPGA. XCO frequency of (5.65/64) 88.3MHz
will be applied.
BB frequency up to 200MHz and IF frequency up
to 400MHz could be applied. LO signal of 9 GHz
X
(XCO 93.75MHz) will be modulated for spectrum
between 8.6 to 9.4 GHz.
BB frequency up to 200MHz and IF frequency up
to 400MHz could be applied. LO signal of 16.8
Ku
GHz (XCO 87.5) will be modulated for spectrum
between 16.4 to 17.2 GHz.
5. DOWN CONVERSION
Figure 5. Block scheme of realized test model
Down conversion process should be performed with the
same LO signals as UP conversion process. It permits
applications of common microwave LO for Tx and Rx
chain. Because image frequency can be close to LO
frequency image rejection mixer should be used. In case
that BB frequencies (below 200MHz) are outputs from
the IRM it doesn’t mean yet that the receiver is direct
receiver without IF stage. IF signal could be the part of
the BB output spectrum. In that case sampling rate has to
be adjusted to fulfill under sampling criteria. Block
scheme of the down converters are presented at the Fig.4.
Tx DAC accept XCO signal as reference signal and
multiplies (by internal PLL) up to DA sampling frequency of
750MHz (X8). NCO is operable at frequency of 200MHz.
Input data rate of 375MS/s is interpolated X2 and
modulation is performed at NCO sampling frequency of
750MHz. Highest frequency in spectrum is 2.5 times below
sampling frequency. Tx DAC is presented at the Fig.6.
Figure 4. Block scheme of analogue part of down
converter
LNA, PA, circulator and antenna part are not affected by
FPGA processing flexibility.
Figure 6. Tx DAC for numerical up conversion
6. EXAMPLE OF ANALOGUE PLATFORM
SUPPORTED FPGA SIGNAL CONVERSION
As AD converter, 310MS/s 14 bit DDR converter could
be applied. AD converter bandwidth is 650MHz. LVDS
inputs in FPGA circuits can be programmed to receive
DDR bit stream and no additional interface is needed.
Two channel high speed DDR AD converter is presented
at the Fig.7.
Reference frequency oscillator of 93.75MHz is applied.
FPGA processor generate signal in the band between 100
and 300 MHz. IQ signals are generated by Tx DAC with
1200MSample/s. LO frequency of 9GHz is obtained
multiplying 3 GHz VCO by 3. Final frequency of 9.1 to
9.3 GHz is obtained by last conversion. The same
microwave local oscillator is applied for down
Test model of synthesizer is presented at the Fig.8.
Multiplier by 3 could be realized as a passive or active
circuit. Active multiplier with waveguide filter should be
409
the best solution. Applying low power GaAs HEMT
output power of 0dBm could be obtained. Two amplifiers
with the equal transistors could be applied as a driver to
IQ modulator and demodulator. Multipliers as off the
shelf components could be found in market, but
availability and price are in the favor custom design
active multiplier. Similar comments could be associate to
oscillator and power dividers.
Figure 9. UP/DOWN converter model
Figure 7. High speed low power DDR AD converter
Figure 10. Front-end components
7. CONCLUSION
Previous analysis and example proved that simple and
reliable analogue platform can support all advantages that
could be exploited from FPGA circuit application in radar
architecture. Application of flexible digital platform
relaxes the requirements for analogue component
performances. Required performances could be obtained
not only with the state of the art analogue components but
also with the mature technology.
Figure 8. Synthesizer model
IQ modulator and IQ demodulator (including wideband
90degree (hybrid) IF combiner are realized with discrete
components. 90 degree phase shifter at 9 GHz could be
realized with simple microstrip delay line because LO
frequency is fixed frequency. This is benefits of FPGA
flexibility too. Two mixers are simple balance mixer
applicable in satellite receiver LNB. Main drawbacks of
this solution are losses introduced by passive mixer.
There are of the shelf IQ modulators with significant gain
(instead losses) but availability and price of these
components could be problematic. Model of UP converter
is presented at the Fig.9.
References
[1] R. Andraka and A. Berkun: FPGAs Make a Radar
Signal Processor on a Chip a Reality, Proceedings of
the 33rd Asilomar Conference on Signals, Systems
and Computers, October 24-27, 1999, Monterey, CA.
[2] Tyler J. Moeller: Field Programmable Gate Arrays
for Radar Front-End Digital Signal Processing, MSc
thesis, Massachusetts Institute of Technology, May
22, 1999
[3] http://www.analog.com/en/digital-to-analogconverters/high-speed-daconverters/products/index.html
[4] http://www.analog.com/static/importedfiles/data_sheets/ADL5380.pdf
[5] http://www.rfmd.com/products/wirelessinfrastructure
/frequencyconversion.aspx
Power amplifier, low noise amplifier, RF filters, diplexer
and IF amplifiers are standard components that should be
incorporate in radar architecture. Unique control function
that could be added to FPGA is power amplifier supply
switching off and on. There are no requirements for
frequency adjustment and carrier modulation what are the
typical functions in classic radar architecture. These frontend components are shown in Fig.10.
410