.
First-order
frequency ∆-Σ modulation
Dr. Scient thesis
Mats E. Høvin
January
2000
.
.
I will greatfully thank my superviser Tor Sverre Lande
and the following persons for
making this thesis possible
(in alphabetical order)
Yngvar Berg
Ole Herman Bjor
Monica Finrsud
Saife Kiaei
Jan Tore Mairenborg
Nice guys at NFR
Sigbjørn Næss
Alf Olsen
Tanja Paetow
Trond Sæther
Chris Toumazou
Dag Trygve Wisland
.
Contents
Introduction
6
1 Conventional ∆-Σ noise-shaping
10
1.1 ∆-Σ analog-to-digital conversion . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2 The first-order ∆-Σ modulator . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3 Errors and noise sources in the first-order ∆-Σ modulator . . . . . . . . . . . 13
2 Basic FDSM techniques
2.1 The non-feedback ∆-Σ modulator . . . . . .
2.2 The first-order FDSM principle . . . . . . .
2.3 The basic modulo-2n FDSM . . . . . . . . .
2.4 The D flip-flop FDSM . . . . . . . . . . . .
2.5 The pointer-FDSM . . . . . . . . . . . . . .
2.6 Feature and performance characterization of
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the first-order FDSM
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18
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3 Extended FDSM techniques
3.1 FM signal undersampling . . . . . . . . . .
3.1.1 Time-domain analysis . . . . . . . .
3.1.2 Frequency-domain analysis . . . . .
3.2 The sampled-clock FDSM . . . . . . . . . .
3.2.1 Virtual frequencies . . . . . . . . . .
3.2.2 The SC D flip-flop FDSM . . . . . .
3.2.3 Resolution comparison for SS vs SC
3.3 Synchrounization . . . . . . . . . . . . . . .
3.4 Triangularly weighted zero-cross detection .
3.5 The single-bit pointer FDSM . . . . . . . .
3.6 Paralell conversion . . . . . . . . . . . . . .
3.6.1 Parallelisation . . . . . . . . . . . . .
3.6.2 Open-ended delay-line parallelisation
3.6.3 A 7-bit parallel audio FDSM . . . .
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36
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4 Excess noise
4.1 Phase Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 Equivalent frequency noise . . . . . . . . . . . . . . . .
4.1.2 Output noise power . . . . . . . . . . . . . . . . . . . .
4.1.3 Simulation . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.4 Comments on phase noise in the sampled-signal FDSM
4.2 Pattern noise . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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4.3
4.2.1 Background . . . . . . . . . . . . . . . .
4.2.2 A theoretical model for pattern-noise . .
4.2.3 Verification of the FDSM equivalence by
4.2.4 Valley utilization . . . . . . . . . . . . .
Time-domain dithering . . . . . . . . . . . . .
4.3.1 Measurements . . . . . . . . . . . . . .
5 Conclusion and
5.1 Summary .
5.2 Conclusion
5.3 Future work
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simulation
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83
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future work
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6 Publications
6.1 IEE Electronics Letters no. 1 . . . .
6.2 ISCAS no. 1 . . . . . . . . . . . . .
6.3 IEEE Journal of Solid State Circuits
6.4 ISCAS no. 2 . . . . . . . . . . . . .
6.5 IEE Electronics Letters no. 2 . . . .
6.6 Low Power . . . . . . . . . . . . . .
6.7 NorChip . . . . . . . . . . . . . . .
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98
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136
A PSD definitions
148
B C simulators
150
5
Introduction
For 20-30 years ago, the word digital was used by only a small group of specialized
engineers and scientists. Nowadays this word is heard almost everywhere and is used with
the greatest self-confidence by everyone from the little boy in the street (nowadays more
likely found in front of a play-station), to old aunt Mary. I will not suggest that the
understanding of what the word digital means, is more widespread today, but who cares
as long as it usually is synonymous with cheaper products with stunning new features. It
is not difficult to see why digital technologies are so popular today. For those of us who
are into digital design, we know that digital signal processing means high resolution, almost
no problems with noise and interference, the signal can easily be stored electronically in
memory, opening up for a new world of filtering techniques, and so on. In a marked driven
by low-cost, short time-to-marked and high flexibility, we do not achieve much by referring
to the beauty of analog solutions, unfortunately. So, the digital way of thinking is definitely
here to stay, at least for a while.
In many cases digital systems needs to communicate with the natural world, which we
normally refer to as analog, and in this case a signal converter is needed. For several reasons,
it normally pays off to let the digital domain expand in all directions, reducing the use of
analog electronics to a minimum. As an example, for analog-to-digital conversion, traditional
Nyquist-rate converters are now often replaced by ∆-Σ converters [1, 2, 3] reducing the
problems with analog matching and high order analog anti-aliasing filtering in VLSI. The
result is high quality, low-cost converters providing up to 24-bit resolution. Another example
can be found in some RF demodulators where bandpass ∆-Σ converters [4, 5] have moved
the digital domain closer to the antenna allowing for digital demodulation. In this way
the flexibility of the RF receiver is significantly increased opening up for multi-standard
communication.
The main reason for the success of the ∆-Σ converter is, that most of the conversion
challenge is shifted from the analog into the digital domain where it is easily taken care of by
high speed digital filters. It seems however, to be a trend nowadays to focus on higher-order
∆-Σ modulators [3, 6] to further increase the resolution, or alternatively, increase the signal
bandwidth. The reason for this is usually found from a limitation in the maximum sampling
speed. In traditional switch-capacitor ∆-Σ modulators the sampling speed is strongly limited
by slew-rate effects and finite op-amp gain. However, by increasing the order of the ∆-Σ
modulator, the challenge is actually shifted back towards the analog domain again, where
problems due to matching and/or stability occurs [3]. On the other hand, there have been a
reason to avoid low-order modulators, particularly first-order modulators due to an inherent
problem called pattern noise.
In 1994, the work on the FDSM (Frequency Delta-Sigma Modulator) concept was started.
This is based on a ∆-Σ modulator where the input signal is an ordinary FM signal. In this
way, a frequency-to-digital converter with ∆-Σ noise-shaping was made. The first-order
6
FDSM was a purely digital circuit, and by adding a frequency modulator to it we had an
alternative ∆-Σ analog-to-digital converter.
A frequency modulator can be implemented in many ways. In reference [7], we have
showed an example where the frequency modulator was made by a standard CMOS ringoscillator where the frequency was modulated by varying the inverter power supply voltage.
In other words, the analog input signal to the ring-oscillator was the inverter power supply
voltage. In this way a ∆-Σ analog-to-digital converter was implemented only by standard
digital gates, and the border of the digital domain was pushed even further. The ringoscillator FDSM is particularly interesting for integrated sensor applications as the inverter
delays can be directly modulated by a physical signal, with a suitable arrangement. Due to
high inverter gain and noise-shaping, there are no need for an analog pre-amplifier. In this
way, the digital domain is about to meet the natural world directly with almost no analog
circuitry in between.
A major advantage of a “digital” ∆-Σ modulator is that it will directly benefit from
improvements in digital processes and thus scales with technology. When the supply voltage
is reduced to 1 volt or probably less, we believe that the right way to go is low modulator
order, high sampling speed, time-domain quantization as we will discuss later, and the use
of standard digital gates.
There are, of course, also problems with such simple solutions. By using a first-order
∆-Σ modulator, a very high oversampling ratio is normally needed to achieve a high digital
resolution. But by implementing the ∆-Σ modulator only by digital gates, the sampling
speed can be much higher than in a traditional switched-capacitor modulator which means
increased digital resolution. As we have shown in this thesis, the resolution of a first-order
FDSM may be almost 24-bit in the audio range when a high sampling speed is used combined
with multi-bit conversion.
Another problem usually seen in first-order ∆-Σ modulators is pattern noise. In this
thesis, we have analyzed this effect extensively and proposed three different techniques that
can be used to reduce or eliminate this problem.
By using a very simple frequency modulation technique, the nonlinearly of the ringoscillator transfer function may be a problem. However, for low relative frequency deviations
the total harmonic distortion (THD) may be quite low. As an example, in reference [7] the
THD is measured to -80dB for a specific Vdd modulated ring-oscillator FDSM implemented
in 1.2µm CMOS VLSI. On the other hand, by comparing this non-linearity problem to the
problem with a non-linear DAC in a traditional feedback ∆-Σ modulator, the more deterministic non-linear transfer function of a ring-oscillator will be easier to linearize digitally
than the more randomly given function caused by DAC level mismatch.
A fundamental difference between a switched-capacitor ∆-Σ modulator and the FDSM
is that quantization in the FDSM is done in time or phase and not in amplitude. In this
way, we have a new axis to follow when seeking for high resolution which is more suitable
for low supply voltage applications. In this thesis, we have proposed a new concept of
analog/frequency to digital conversion based on parallelism. This idea utilizes both time
domain quantization and the small size and simplicity of the D flip-flop FDSM. The new
idea is to make a large number of very small parallel converters where the outputs are
added together to make a multi-bit ∆-Σ modulator. Each converter operates on different
phase or time information from the intermediate FM signal. The phase information can, for
frequency-to-digital conversion applications be obtained from a delay-line, and for analogto-digital conversion applications by a modulated ring-oscillator.
To summarize this overview, the overall aim of this thesis can be stated in the following
way:
7
The main aim of this thesis have been to develop techniques that make it possible to reduce the analog complexity of ∆-Σ converters and in this way reduce
the amount of necessary analog circuitry separating the digital domain and the
natural world.
Finally, two other research groups currently working with ∆-Σ frequency-to-digital conversion shold be mentioned. The first group is supervised by Professor Ian Galton at the
University of Califiornia, San Diego and includes William Huff, Paolo Carbone and Eric Siragusa. The other group consists of Walt T. Bax, Thomas A. D. Riley, Miles A. Copeland,
Tom A. D. Riley, Norman M. Filiol and Calvin Plett working at Carleton University, Ottawa in Canada. Both gropus have developed their own ∆-Σ FDC solutions based mainly
on digital circuits. The main focus for both groups are higher order modulators [8, 9], and
their results seem promising. However, for first-order ∆-Σ frequency-to-digital conversion
there are no simpler solution than the D flop-flop FDSM, as this circuit directly utilize the
close relationship between a hard-limited FM signal and the first-order ∆-Σ bitstream.
Organization of this thesis
The thesis starts by introducing the basic ideas of traditional ∆-Σ noise-shaping. Then
we have chosen to include some of the work from my Cand.Scient thesis in the introduction, to make it easier for readers that are unfamiliar with the FDSM concept. Chapter 2
“Basic FDSM techniques” is therefore a summary of first-order techniques selected from my
Cand.Scient thesis. In Chapter 3 “Extended FDSM techniques”, we start by introducing
the undersampled FDSM. It is described how to extend the useable range of the D flip-flop
FDSM which is the most simple and compact implementation of a frequency-to-digital converter with ∆-Σ noise-shaping. Then we introduce the sampled-clock FDSM, which will
increase the digital resolution for certain application. In Section 3.5 we present the triangularly weighted zero-cross detector which is a mathematical model of the FDSM. In Section
3.6 we present a simplification of the pointer FDSM which is the basis for parallel conversion. Then we continue with the parallel FDSM converter, both based on a ring-oscillator
solution targeted at ADC applications, and also based on an open-ended delay-line suited
for FDC applications.
From several technical discussions with representatives from the industry it have become
clear that FM signal phase noise is a major problem in many FM demodulation applications.
It have been quite difficult to convince them that phase-noise really is noise-shaped in the
FDSM, as it is only intuitively argued for in my Cand.Scient thesis. Section 4.1 is therefore
devoted to the analysis of phase noise in a practical FDSM system. The effect of phase noise,
both on the FM signal, and also on the clock signal have been analyzed, both analytically,
by simulations and by measurements. It is confirmed that phase noise, both on the FM
signal and on the clock signal, is first-order shaped by the FDSM. In Section 4.3 the effect of
pattern noise is analyzed. And finally, in Section 4.3 we present the method of time-domain
dithering.
Seven publications are attached to this thesis, but to make it more comprehensive we
have chosen to include two publications published during my Cand.Scient work. The first
two publications “Novel second-order ∆-Σ modulator/frequency-to-digital converter” and
“Delta-Sigma Converters using Frequency-Modulated Intermediate Values” are therefore not
considered to be a part of this Dr.Scient work. The next paper “Delta-Sigma Converters
using Frequency-Modulated Intermediate Values”, published in the Journal of Solid State
Circuits, are also mostly based on results from my Cand.Scient period but the paper is
created and written as a part of this Dr.Scient work.
8
9
Chapter 1
Conventional ∆-Σ noise-shaping
1.1
∆-Σ analog-to-digital conversion
∆-Σ AD conversion techniques have become very popular as they avoid many of the
difficulties encountered with conventional methods for AD conversion. Nyquist rate converters, as illustrated in Fig. 1.1 top, have attributes that make them difficult to implement
in VLSI technology. Chief among these is the use of analog anti-aliasing filters, the need
for high precision analog circuits, and their vulnerability to noise and interference. The
∆-Σ converter, illustrated in Fig. 1.1 bottom, is amenable for VLSI implementation because
circuit precision requirements can be significantly relaxed by a high oversampling (fs /fN )
ratio, noise shaping, and feedback. High oversampling eliminated the need for abrupt cutoffs
in the anti-aliasing filter, and due to the noise-shaping, a low resolution ADC may be used
without precluding a high overall signal-to-quantization noise-ratio (SQNR). In that sense,
the ∆-Σ converter can trade resolution in time for resolution in amplitude.
Figure 1.1: Top - Nyquist rate analog-to-digital converter. Bottom - ∆-Σ oversampled analog-todigital converter
The first part of the ∆-Σ converter is the ∆-Σ modulator. This circuit modulates the
10
analog input into a high frequency digital code shifting the noise from the coarse ADC
(usually one-bit), out of the frequency band of the signal. The output of the ∆-Σ modulator
is a high frequency bit- or words-stream followed by a digital decimation filter. This filter
will, dependent on the oversampling ratio, and the modulator order, be able to provide
a high resolution digital output at a low sampling rate. High frequency components and
out of band quantization noise will be removed by this filter before it could fold down to
the signal band. From Fig. 1.1 one may say that the ∆-Σ technique splits the Nyquist
rate conversion challenge in to parts, the decimation filter, and the smaller and simpler
implemented analog ∆-Σ modulator. In this way most of the conversion challenge is shifted
into the digital domain. Because the sampling rate in a ∆-Σ modulator usually needs to be
much higher than in a Nyquist rate converter, conventional ∆-Σ methods are best suited
for low signal bandwidth applications. They have found use in applications such as digital
audio, communication and instrumentation.
1.2
The first-order ∆-Σ modulator
Quantization of amplitude and sampling in time are at the heart of all ADCs. The
transfer function of an ADC or quantizer is nonlinear (Fig. 1.2), and in order to achieve a
simple mathematical description of the modulator, we may treat the quantization error as
a random variable.
output
quantization levels
quantization error
thresholds
∆
input
Figure 1.2: The input-output relationship of a quantizer
For most busy input signals, we may consider this random variable to be uncorrelated
with the input signal and to have a constant probability density function (pdf) over the
interval ±∆/2 where ∆ is the quantization level spacing. In many cases, reported experiments have confirmed these properties, but there are two important instances where they
may not apply; when the input is constant, and when it changes regularly by a multiple or
sub-multiple of ∆, as can happen in feedback circuits. As a constant pdf random variable,
the mean square value of the quantization error en ∈ [−∆/2, ∆/2 will be given by
e2rms
1
=
∆
∆/2
e2 de =
−∆/2
∆2
12
(1.1)
and we will assume that the spectral density is constant for all frequencies. In Fig. 1.3a,
the first-order ∆-Σ modulator principle is illustrated. The input to the circuit is fed to the
quantizer via an integrator, and the quantized output is then fed back and subtracted from
the input.
11
fs
in
+
∫( )dt
_
a)
ADC
out
DAC
en
xn
b)
+
+
_
z-1
+
yn
+
quantizer
Figure 1.3: a) The first-order ∆-Σ modulator principle. b) Linearized mathematical model
The feedback forces the average value of the quantized output to track the average
input. Any differences between them accumulates in the integrator and corrects itself.
Unless otherwise specified, the quantizer gain, defined as the level spacing divided by the
threshold spacing, will be unity for all quantizers described in this thesis. In Fig. 1.3b a
commonly used simplified model of the ∆-Σ modulator is shown. The circuit is linearized by
representing the quantizer by the additive noise source en , and the integrator is represented
as an analog discrete-time accumulator. By considering the ideal behavior, the DAC may
be disregarded. From the figure, we see that the modulator output may be expressed by
yn = xn−1 + en − en−1
(1.2)
in other words, the signal passes unchanged except from a unit delay while the quantization
error is differentiated. Due to the differentiation, low frequency quantization noise components will be attenuated. The spectral density of the output quantization noise is given
by
eon = en − en−1
(1.3)
and may be expressed as
N (f ) = 2erms
f
2/fs sin(π )
fs
(1.4)
In Fig. 1.4a the theoretical output noise power spectral density (psd) is shown for an example
where ∆=1 and the sampling frequency is 2MHz. As we see, the quantization noise is shifted
up in frequency.
For the maximum signal frequency fmax , the total in-band noise power is given by
integrating Eq. 1.4 over the frequency range 0 − fmax. For fs fmax , the resulting in-band
noise power will, by using Eq. 1.1, be
n20
∆2 π 2
=
36
2fmax
fs
3
(1.5)
In Fig. 1.4b n0 is plotted as a function of fmax for ∆=1 and fs =2MHz. As we see, the
in-band noise power is significantly reduced for low signal bandwidths. The improvement in
12
50
0
0
50
0
Inband power (W) (dB)
Output spectral density (W/Hz) (dB)
100
1
150
200
2
100
1
150
200
2
250
250
300
0
10
1
10
2
10
3
4
10
10
Frequency (Hz)
5
10
300
6
10
0
10
a)
1
10
2
10
3
4
10
10
Max signal frequency (Hz)
5
10
6
10
b)
Figure 1.4: a) Qantization noise psd plot. b) In-band quantization noise power as a function of
fmax . Both figures - fs =2MHz, ∆=1. 0: Unshaped noise, 1: first-order shaped noise, 2: secondorder shaped noise
resolution over ordinary oversampling do however require that the ∆-Σ modulator output
is decimated by a sharp digital low-pass filter. From Eq. 1.5, the SQNR of the modulator
will be
3 SRo
∆2 π 2 2fmax
√
SQN R = 20 log
− 10 log
(1.6)
36
fs
2 2
where SRo is the output signal range which by the use of a unity gain quantizer will be equal
to the input signal range. From Eq. 1.6 we have that each doubling of the oversampling
ratio (OSR) increases the SQNR by ≈9dB. An alternative way to increase the SQNR is by
decreasing the quantization spacing ∆, or increasing the input signal range. By doing so,
we have to increase the number of quantization thresholds, and the result is a SQNR gain
of ≈6dB for each doubling of the number of effective quantization thresholds which in turn
doubles the output word-length of the modulator.
In Fig. 1.5 the output psd from a single-bit ∆-Σ modulator simulation is shown. The
input signal is a sinusoidal with maximum amplitude and a frequency of 100Hz. The plot is
normalized to let 0dB correspond to the maximum signal amplitude, where the input signal
range is limited to [−∆/2, ∆/2]. The sampling frequency was set to 2MHz, and we notize
that the noise power is shifted up in frequency. There is also some pattern noise at lower
frequencies. The power spectral density is estimated by a modified periodogram estimator,
see Appendix A.
1.3
Errors and noise sources in the first-order ∆-Σ modulator
So far, we have treated the quantization error as uncorrelated with the input signal. In
a practical modulator, this assumption will not always be sufficient. In addition, the ∆-Σ
modulator is an analog device where the effect of inaccurate components must be considered.
In the following sections, the main limiting error and noise sources will be presented.
13
Figure 1.5: a) FFT analysis of simulated ∆-Σ modulator output sequence, fs =2MHz, ∆=1
Pattern noise
For DC or slowly varying inputs, the output will bounce between two levels, keeping its
mean equal to the input. The output sequence may be repetitive and the frequency of this
sequence will be determined by the input DC level. When the repetition frequency lies in
the signal band, the modulation is noisy, but when it does not, the modulation is quiet.
Fig. 1.6 top [3] shows how the in-band noise power depends on the value of the DC input
for a ∆-Σ modulator with quantization levels at ±1 and a low OSR. Fig. 1.6 bottom (scanned
from reference [10]) shows the corresponding noise for a high OSR, and quantization levels
at 0 and 1. There are peaks of noise adjacent to integer divisions of the space between
levels, elsewhere the noise is small. This structure of the quantization error is called pattern
noise, and it will appear as spurious tones/peaks in the modulator output spectrum. The
larger peaks in Fig. 1.6 can far exceed the expected noise level calculated from Eq. 1.5,
and the following properties of pattern noise are noteworthy: I) The height and width of
each peak are inversely proportional to the OSR. The height and width are also inversely
proportional to the denominator of the fraction that describe the position of the peak within
the quantization interval relative to the level spacing. II) About half the total power is in
the end peaks, one-sixteenth in the center peak.
Pattern noise may however be randomized by injecting a signal with frequency well above
the signal band at the input. This signal, also called a dither signal ”smears out” the output
power spectrum, and as a consequence, it reduces the energy of the noise peaks/tones. For
one-bit, first-order ∆-Σ conversion, the pattern noise problem may be significant as the inband pattern noise power may be large compared to the signal power. If not the full output
signal range is used, the output signal range may however be biased and located well away
from the main noise peaks to reduce this problem.
DAC output levels
The main problem for multi-bit ∆-Σ modulator operation is inaccurate DAC output
levels. From Fig. 1.3 we notice that all errors introduced in the feedback path will add
directly to the signal. In addition, since yn is close to xn in a multi-bit ∆-Σ modulator,
14
In-band noise power (dB)
DC input level
DC input level
Figure 1.6: Measured in-band noise v.s input signal DC value. Arrows indicate theoretical in-band
noise from Eq. 1.5. Top - low OSR. Bottom - High OSR
the correlation between the input and the DAC error will be large. Thus the DAC error
will usually have a large baseband energy content and will generate harmonic distortion.
The DAC output levels must therefore be positioned with an accuracy better than the
overall SQNR which for high resolution conversion normally will require, either external
components and/or trimming, or the use of more or less complex correction techniques
[11, 12, 13, 14, 15]. The use of external components or trimming will, however, raise the
cost of the system considerably. The fact that the DAC output settling time must be very
low (less than 1/fs ), eliminates the use of most ordinary high resolution DAC architectures.
For single-bit ∆-Σ modulator operation only two DAC output levels are required, and any
misplacement is equivalent to a bias in the modulator input signal. The only requirement
will therefore be properly placed DAC output levels to accommodate the input signal range.
ADC thresholds
The quantizer in the multi-bit ∆-Σ modulator usually takes the form of a flash ADC.
Misplaced ADC thresholds may be regarded as a non-linearity of its gain, but due to the high
gain feedback, such errors have little effect on the baseband properties of the modulator.
Misplacing the thresholds by as much as a quarter of their spacing is usually tolerable. For
single-bit ∆-Σ modulator operation, the only requirement on the single threshold placement
is to prevent overloading in the integrator.
15
ADC overloading
The internal signal swing in the integrator uses up some of the dynamic range of the
circuit, and if the ADC is not to overload, the input signal range (SRi ) must not exceed the
maximum and minimum ADC output levels. If a large input causes the ADC to overload,
the modulator noise will increase rapidly. Simulations show that excess noise introduced by
larger signals appears as odd-order harmonic distortion of sine waves. The excess noise will
decrease with increased OSR but increases with the frequency of the applied sine wave.
Integrator errors
In the integrator, there are several noise sources, but small errors introduced by the
integrator will generally due to the high gain feedback have little impact on the overall
modulator performance. For most applications a 10% change of integrator gain will be
tolerable. Integrator leakage decreasing the integrator DC gain to at least the OSR will
not be a problem. The integrator slew rate will however be a limiting factor for high
sampling frequency operation. Most ∆-Σ modulator integrators are implemented by the use
of switched capacitor (SC) techniques, and linear capacitors and a non-overlapping two-phase
clock is normally required. To reduce the effect of power supply noise, charge injection and
clock feedtrough, a fully differential architecture is normally used. The SC technique is very
little sensitive to clock jitter, but to achieve a low kT /C level, there will be a minimum limit
on the capacitor values. For high SNR operation, the minimum value may typically be in the
10pF range. Due to this constraint, there will be a trade-off between high speed operation
combined with a low kT/C level, and low power consumption. It should be mentioned that
in a ∆-Σ modulator, the main power consumer will normally be the integrator, but in a
complete ∆-Σ converter, the decimator power consumption may dominate.
Implementation constraints
As previously stated, by using SC techniques in the ∆-Σ modulator, linear capacitances
are required, and the SC-∆-Σ modulator can generally not be implemented in the least
expensive standard digital CMOS processes, since an extra poly-layer will be required. In
addition, as a voltage-mode device, the SC-∆-Σ modulator is not well-suited for low power
supply voltage operation. With power supply voltages close to 1V likely to become a future industrial standard, process parameters such as threshold voltage will be chosen to
optimize digital performance so voltage domain behavior will suffer as a consequence. To
overcome these limitations, switched current (SI) techniques have been proposed [16], but so
far no high-resolution SI-∆-Σ modulators have been reported due to several implementation
difficulties associated with this new technique.
16
17
Chapter 2
Basic FDSM techniques
The frequency delta-sigma modulator is a feed-forward device with no feedback. Usually
∆-Σ modulation is synonymous with feedback, but in the next section we will prove that
the traditional first-order ∆-Σ modulator is equivalent to a cascade of an integrator and a
differentiator where the quantizer is located in between. This is shown without linearizing
the quantizer function.
2.1
The non-feedback ∆-Σ modulator
For now, it will be convenient to have a mathematical definition of the quantizing function. For a practical ∆-Σ modulator, where the number of quantizer output levels is restricted, the level placements must be properly chosen to accommodate the input signal
range due to the feedback. In this discussion, the number of levels is assumed to be large,
and therefore, the level placements will not be critical. The unity-gain quantizing function
q(x) with quantizing thresholds integer multiplies of l will therefore simply be defined as
q(x) = x − modl (x)
(2.1)
where modl (x) is the remainder of x after division with l. Compared to the quantizing
function illustrated in Fig. 1.2, q(x) is shifted down by ∆/2 as illustrated in Fig. 2.1. The
quantization error en will now be restricted to the interval −1, 0], but by considering its
new mean value as a bias in the input signal, the root mean square (rms) value will be the
same as for the former used quantization function, and the theoretical results from Chaper
1 will therefore still be valid for q(x).
The Z-transformed representation of a conventional discrete-time first-order ∆-Σ modulator is shown in Fig. 2.2. In this circuit, the ADC or quantizer is represented by the
complex quantization function Q, defined by Q[U (z)] = Z{q(un )}. The output may then
be expressed as
−1
z
z −1
Y (z) = Q
X(z)
−
Y
(z)
(2.2)
1 − z −1
1 − z −1
In [7] it is proven that in general, for two real sequences fn and gn , the quantization function
Q posses the property
Q[F (z) + P · G(z)] = Q[F (z)] + P · G(z),
18
if
q(gn ) = gn
(2.3)
q(x)
output levels
quantization error
thresholds
x
∆
Figure 2.1: The q(x) quantizer function
X(z)
+
_
z−1
+
U(z)
Y(z)
Q( )
Figure 2.2: Z-transformed representation of the traditional first-order ∆-Σ modulator
if the sequence gn is already quantized. In this statement, P is a general complex polynomial
of the form z −a /(1 − z −1 )b where a and b are positive integers. By using this property,
referred to as the resolving property, the Y(z) terms of Eq. 2.2 may be resolved from the
quantizer function, and the equation may be expressed as
−1
z
−1
Y (z) = (1 − z )Q
X(Z)
(2.4)
1 − z −1
X(z)
z-1
+
+
Q( )
+
z-1
z-1
Y(z)
-
Figure 2.3: Equivalent first-order ∆-Σ modulator
But Eq. 2.4 is an expression describing a different circuit with the same mathematical
behavior, and it may be sketched by Fig. 2.3. The corresponding time domain representation
is
n
n−1
yn = q
xi−1 − q
xi−1
(2.5)
i=−∞
i=−∞
This new circuit reveals the simple principle of the first-order ∆-Σ modulator. Except from
the unit delay, the modulator operates by first integrating the signal, then quantizing it,
and finally differentiating the signal and the quantization error to restore the signal. Since
the quantization error is not integrated, it will be differentiated, and the quantization noise
19
will be shifted up in frequency and out of the signal band. By considering the quantization
error as uncorrelated with the input signal, the signal will pass unchanged except for the
unit delay. To achieve a better understanding of the first-order ∆-Σ noise shaping principle
we may think of the modulator as a cascade of a continuous-time integrator and a derivator.
Their equivalent gains will be 1/Ts and Ts respectively, where Ts = 1/fs is the sampling
interval. In between, the quantization noise is entering the circuit as illustrated in Fig. 2.4.
e
x
∫
( )dτ
+
+
1/Ts
Ts
d ()
dt
y
Figure 2.4: Another look at the first-order ∆-Σ noise-shaping principle
In this circuit, we have two different mechanism both reducing the in-band noise in the
output signal. First, by letting the error enter in between the integrator and the derivator,
the output noise will be given by the derivative of the error. This mechanism shapes the
noise by suppressing low frequency in-band error components. The next noise suppressing
effect follows from the fact that the error enters in between the two complementary gain
factors 1/Ts and Ts which scales up the signal compared to the error by a factor 1/Ts for all
frequencies. By doubling the sampling frequency 1/Ts , we actually double the magnitude
of the input signal compared to the magnitude of the error, and this gives a ≈6dB increase
in SQNR. It is further a well known result that by sampling a signal mixed with white
noise, the in-band SNR increases with ≈3dB for each doubling of the sampling frequency.
Together these two factors explains the increase in SQNR by 6+3=9dB for each doubling
the sampling frequency in the traditionally ∆-Σ modulator.
2.2
The first-order FDSM principle
By considering the theoretical circuit in Fig. 2.3, there are no feedback and thus no DAC,
and this eliminates all problems due to misplaced DAC output levels. As the output of the
quantizer is digitally differentiated, all baseband noise introduced by misplaced quantizer
thresholds will be heavily suppressed. These two features open up for straightforward multibit quantization. The drawback is however that due to the lack of feedback, inaccuracies in
the integrator adds directly to the signal. The modulator SNR will therefore be restricted
to the SNR of the integrator, which for high SQNR operation must be very accurate. In
addition, without feedback, a conventional accumulator will at some point normally saturate,
and this is why the FM representation of signals become interesting. A FM signal be
expressed as [17]
f m(t) = sin[θ(t)]
where the instantaneous angle is given by
θ(t) = 2π
(2.6)
t
−∞
(fc + kx(τ ))dτ
(2.7)
In this expression fc represents the carrier frequency, and k the frequency sensitivity to the
modulating signal x(t). From Eq. 2.7 we notice that the FM signal or more exactly the
20
frequency modulator source by its angle θ(t) is an integrator with respect to the modulating
signal x(t). This property do also follow from the fact that the FM carrier may be considered
as a phase modulated carrier where the modulating signal is pre-integrated. The frequency
modulator may be very useful as an ∆-Σ modulator integrator in applications where the
feedback is removed. It will never saturate as it may be considered as a modulo integrator
where θ(t) represents a rotating pointer where the angular speed is modulated by the input
x(t). The modulo operation on the angle is carried out by the sin() function. The integrator
SNR will correspond to the SNR of the FM signal which may be high, depending on the
architecture of the frequency modulator. The frequency modulator is however a continuoustime integrator, and by exchanging the discrete-time integrator in Fig. 2.3 with a frequency
modulator as illustrated in Fig. 2.5, the resulting FDSM will be mathematically equivalent
to a conventional ∆-Σ modulator with a continuous-time loop integrator and input Ts (fc +
kx(t)) [7].
fs
θ(t)
fm(t)
θn/2π
detector
x(t)
θn/2π
+
q( )
_
yn
z-1
frequency
modulator
Figure 2.5: The general first-order FDSM
But for a high OSR we may from Eq. 2.7 approximate θn as
θn ≈ 2πTs
n
(fc + kxi )
(2.8)
i=−∞
and the FDSM overall operation may, in principle, be described by applying this sampled
FM variable directly to the quantizer. Since there is no unit delay, the output will from
Eq. 2.5 be
n
n−1
yn = q T s
(fc + kxi ) − q Ts
(fc + kxi )
(2.9)
i=−∞
i=−∞
By representing the quantizer by the additive noise en , we have
yn = T s
n
i=−∞
(fc + kxi ) + en − Ts
n−1
(fc + kxi ) − en−1 = Ts (fc + kxn ) + en − en−1 (2.10)
i=−∞
As we see, the modulating input signal xi is just scaled and biased, while the quantization
error is differentiated. The overall circuit will therefore, except from the scaling and biasing
factors, provide equivalent ∆-Σ noise-shaping with respect to x(t). We may also consider
it as delta modulation [18] with respect to θn since the sub-circuit handling the FM signal
actually is a delta modulator. Buried in the output bit or word stream, the effective output
signal range will be
SRo = 2∆f /fs = Ts kSRi
21
(2.11)
where ∆f is the maximum frequency deviation caused by the input signal range SRi . By
doubling the sampling frequency in the first-order FDSM, the in-band quantization noise is
reduced by ≈9dB. However, from Eq. 2.11 we see that the signal range is also reduced by a
factor of two. The net gain in SQNR will, therefore only be ≈3dB.
In FD applications, the input signal will already be given as a FM carrier i.e. the
frequency modulator is implemented in the signal source. For these applications, the FDSM
system must be considered to include the signal source integrator even if it is implemented
as an oscillating sensor or as a traditional frequency modulator several miles away in a radio
transmitter. In these applications, the integrator SNR is already given by the SNR of the
received FM signal. Any noise introduced to the FM signal, including noise generated by
the θn detector, will be first-order shaped as the FM signal is the integral of x(t). Due to
the high noise immunity of the FM signal, the accuracy requirement of the θn detector will
be very low.
2.3
The basic modulo-2n FDSM
As in the traditional ∆-Σ modulator, the ADC thresholds placement and spacing may
be varied, but in the FDSM system, we will see that the implementation will be particularly
simple by locating the quantization thresholds to integer values by letting the module l of
q(x) equal 1.
θn detection
By looking at the sampled FM variable θn /2π, the quantizer input may be expressed as
θn
= pn + ϕn
(2.12)
2π
where pn is an integer representing the number of received FM periods or rising FM edges
at time nTs , and ϕn ∈ [0, 1 represent the phase difference between the previous rising FM
edge and the sampling edge scaled by 1/2π as illustrated in Fig. 2.6.
sample
pn-1
fm(t)
pn
2πϕn
θn=pn2π+2πϕn
pn+1
ϕn
2πpn
Figure 2.6: The splitted angle representation
The modulator output may now be expressed by
θn
θn−1
yn = q
−q
= q[pn + ϕn ] − q[pn−1 + ϕn−1 ]
2π
2π
(2.13)
By the use of integer quantization thresholds, pn and pn−1 will be already quantized, and
according to the resolving lemma [7], the output will be equivalent to
yn = pn − pn−1 + q[ϕn ] − q[ϕn−1 ]
22
(2.14)
But since ϕn is restricted to the interval [0, 1 and we are using integer quantization thresholds, the quantization error will be −ϕn , and the output from the quantizer function will
always be zero which let us reduce Eq. 2.14 to
yn = pn − pn−1
(2.15)
This is simply the received number of rising FM edges during the sampling interval Ts .
From this discussion we realize that the most straightforward first-order FDSM may be
implemented simply as a frequency modulator followed by a count and dump FD converter
as shown in Fig. 2.7.
fs
fm(t)
x(t)
reset
period
counter
reg
θ(t)
yn
count
frequency
modulator
Figure 2.7: The most straightforward FDSM implementation
To put it in another way, we have shown that by introducing oversampling and proper
decimating in a traditional count and dump FDC system, we achieve multi-bit ∆-Σ noise
shaping with respect to the modulating signal. Since the quantization error is −ϕn , the
output from this FDSM may from Eq. 2.10 also be expressed as
yn = Ts (fc + kxn ) − ϕn + ϕn−1
(2.16)
As a ∆-Σ analog-to-digital-to-frequency converter, the SQNR will from Eq. 2.11 and Eq. 1.6
be
3 kSRi
π 2 2fmax
√
SQN R = 20 log
− 10 log
(2.17)
36
fs
2 2fs
As we see, this expression is identical to the traditional ∆-Σ modulator expression, except
from the scaling of the input signal by k/fs . Since multi-bit quantization is inherent in the
FDSM concept, a significantly higher SQNR may be achieved in the FDSM by the use of a
high k value. A high k value can be obtained by the use of a high frequency deviation. Since
the non-linearity of the frequency modulator normally will increase with the ∆f /fc ratio,
the use of a high carrier frequency may be the best way to go. If the frequency modulator
is already implemented in the signal source, we may from Eq. 2.11, more easily express the
SQNR of the FD subcircuit by
3 ∆f
π2 2fmax
SQN R = 20 log √
− 10 log
(2.18)
36
fs
2fs
It will, of course, be possible to increase the dynamic range by counting both rising and
falling FM edges. This will directly correspond to letting θn in Eq. 2.12 represent the received
number of halve periods at time nTs , and ϕn ∈ [0, 1 be the phase difference between the last
23
FM edge and the current sampling edge scaled by π. Since the quantization error rms value
will be unchanged while the signal range is doubled, an increase in SQNR of ≈6dB will result.
Probably, the most practical implementation may then by the use of a separate positive and
negative edge triggered counter and simply add their outputs. The first objection may be
that an accurate FM signal duty-cycle of 50/50 may be required, but simulations show minor
SNR degradations for minor FM duty-cycle deviations. This is reasonable since the dynamic
range is independent of the duty cycle while the quantization error range will increase from
[0, 1 to [0, 2 when the duty cycle approach 0/100 or 100/0. By reducing the duty-cycle to
0/100 or 100/0, the 6dB increase in SQNR will therefore gradually be lost.
The modulo-2n counting principle
The counter resetting operation will be a limiting factor for high-speed operation. According to Eq. 2.15 and by considering the count and dump circuit as an ideal counter with
no upper limit followed by a digital differentiator, the ideal counter may be realized as a
modulo-2n counter as shown in Fig. 2.8.
fs
fm(t)
modulo-2n
counter
n-bit
reg
θ(t)
x(t)
+
_
reg
frequency
modulator
n-bit
output
word-stream
Figure 2.8: The basic modulo-2n FDSM with a positive edge triggered modulo-2n counter
By disregarding the borrow bit from the differentiator, the modulator output will be
equivalent to the output from the modulator in Fig. 2.7 assuming that the maximum number of received rising FM edges during Ts is smaller than the module of the counter. In
most applications, non-varying bias components in the measured signal have no information
content. In the FDSM, the carrier will normally be of no interest, and by using modulo-2n
arithmetic, the only restriction on the size of the module is that it have to be larger than
the maximum variation of the number of received rising FM edges during Ts to avoid signal
aliasing. The counter may therefore pass through several cycles during the sampling interval
as long as the maximum difference in its outcome is less than 2n . This property let us reduce
the internal word-length in the modulator without loosing any information about the signal
itself. By using a smaller module than the maximum number of received rising FM edges
during Ts , the modulator output will be represented in modulo-2n arithmetic. In reference
[3] it is shown that an efficient way to implement the first stages of the decimator may
also be done in modulo-2n arithmetic. Therefore, if a decimator where the first stages are
based on modulo-2n arithmetic is chosen, no interfacing is required. The modulo-2n output
word-stream may also easily be converted to a standard representation by adding a proper
bias and disregarding the carry bit. The minimum number of received rising edges during
Ts = 1/fs will be the integer part of (fc − ∆f )/fs . If (fc + ∆f )/fs is not an integer, which
is only of mathematically interest, the maximum number of received rising edges will, as
illustrated in Fig. 2.9, be the integer part of (fc + ∆f )/fs + 1 as the sampling period may
be shifted in time.
If 1/fs is close to an integer multiple of 1/fc, the minimum variation in the counter
outcome, may therefore, even for very small signal ranges be 3. For the basic modulo-2n
24
1/(fc-∆f)
a)
fm(t)
0
1
2
3
1/fs
1/(fc+∆f)
fm(t)
0
b)
1
2
3
4
4
5
1/fs
1
2
3
Figure 2.9: a) Minimum number of received positive FM edges during 1/fs . b) Maximum number
of edges during 1/fs
FDSM, the module may in general, be chosen to be the smallest integer larger than
int
fc + ∆f
fs
+ 1 − int
fc − ∆f
fs
≤ int
2∆f
fs
+ 2 = int(SRo ) + 2
(2.19)
where int(x) is the integer part of x. The minimum internal word-length will then be
log2 [int(SRo ) + 2]
(2.20)
and the output bias component due to fc will be clipped down to mod2n (fc /fs ). For low
output signal ranges the shortest internal word length will therefore generally be two bit.
No counter resetting is needed, and the sampling speed may be considerably higher than by
using the traditional count, dump and reset converter.
Counter readout
The counter reading operation may be considered as a data transfer between two independently clocked systems as the counter is asynchronous to the rest of the system. When
a multi-bit word is to be transferred between two such systems, great care must be taken to
avoid situations when the receiving system tries to read the data at the same time as more
than one bit changes. In that sense, the binary data representation is not well suited, and if
a binary counter is to be used, a separate synchronizing circuit must be applied. There are
however other ways to overcome this problem, and one way is the use of Gray code, either
by a modulo-2n Gray code counter or a binary counter followed by a binary to Gray code
converter. Both solutions will require some more logic, and a Gray to binary converter must
also be applied. Another solution may be using a ring-counter followed by a binary encoder.
If the counter length is large, this solution will however require a large encoder and a lot of
wiring.
System-level simulations
To verify the theory, and simulate the ideal behavior, several system level simulations
have been carried out. Details of the simulator are given in [7]. There are several more or
less sophisticated ways to estimate the output power spectral density from the simulated
word-streams. Throughout this thesis, the most straight-forward and commonly used FFT
25
technique where the psd is estimated by the periodogram estimator [19] (Appendix A), is
used. To better illustrate the modulator dynamic range, the estimated psd is scaled to
let 0dB represent the maximum input signal amplitude for all plots throughout this thesis.
When working with high SNR ∆-Σ output spectrums, a high window sidelobe suppression
factor will be desirable, and a 6-term Blackman-Harris-Hodie window (see Appendix A),
which is specially suited for high SNR analysis is therefore used in all computations.
Figure 2.10: A 218 point FFT analysis of a ideal modulo-22 FDSM output. Max signal amplitude,
signal frequency 100Hz, fc =10MHz
In Fig. 2.10 the estimated output psd for a basic modulo-22 FDSM where fs = 2MHz,
fc =10MHz and the input is a single sinusoid with maximum amplitude and frequency of
100Hz is shown. The maximum input signal amplitude is defined as the amplitude that
produces a maximum intermediate frequency deviation of ±10%. By this choise of circuit
parameters, the modulator SRo will from Eq. 2.11 be 2 · 1 · 106 /2 · 106 = 1, which is the
same as for the traditional first-order ∆-Σ modulator simulation presented in Chapter 1.
The result in Fig. 2.10 may therefore directly be compared to the result in Fig. 1.5. As
we see, the two spectrums are quite similar with the same ≈20dB/decade slope, and the
∆-Σ noise-shaping behavior of the FDSM is confirmed. Compared to Fig. 1.5, the FDSM
spectrum is smoother with less pattern noise. This is only a consequence of the different
quantization level location. For the traditional ∆-Σ modulator simulation, the sinusoidal
input signal have its peak values equal to the quantization levels. The signal will then, for
a longer period be in the large pattern noise end-peak sections, illustrated by Fig. 1.6, than
the FDSM output signal, which have its integer quantization level in the middle of its output
signal range of [4.5,5.5]. For the FDSM, a higher SQNR may be obtained by increasing the
sensitivity k of the frequency modulator.
2.4
The D flip-flop FDSM
From the previous discussion, by using a module less than the maximum received number
of FM edges during Ts , the minimum FDSM internal word-length will, in general, be two
26
bit. But if the maximum received number of FM edges during Ts is less than two, we may,
without risking signal aliasing use modulo-21 arithmetic. This follows from the fact that
the maximum difference in the counter outcome will be two, which will be accommodated
by modulo-21 arithmetic. By using modulo-21 arithmetic and disregarding the borrow bit
from the subtractor, the subtractor may be implemented simply as a XOR gate. A onebit modulo counter will, easiest be implemented as a double edge counter, since a one-bit
modulo counter triggered by both rising and falling edges is equivalent to a D flip-flop. The
entire FDSM may therefore be implemented as a frequency modulator connected to a D
flip-flop followed by a one-bit register and a XOR gate as illustrated in Fig. 2.11
θ(t)
x(t)
fm(t)
fs
CK
D
Q
reg
reg
output
bit-stream
fs
frequency
modulator
Figure 2.11: The D flip-flop FDSM
FM
a)
out
FM
b)
out
Figure 2.12: The D flip-flop FDSM intermeadiate/output signals. a) Modest fs /fc ratio. b) High
fs /fc ratio
The operation of the D flip-flop FDSM may also be considered as a frequency modulator
connected to a synchronizer or direct bit-stream converter as illustrated in Fig. 2.12. From
this discussion, we notice the close relationship between the FM representation of signals
and the first-order ∆-Σ noise-shaped bit-stream. By rising the fs /fc ratio as illustrated in
Fig. 2.12b, the bit-stream will approach an exact representation of the analog information
which in the FM signal is given by the zero crossings or edge positions. In that sense, the
first-order ∆-Σ noise-shaped bit-stream may also be considered as a quantized FM signal.
Since the D flip-flop FDSM is counting both rising and falling edges, its SQNR will be given
by
3 k · SRi
π 2 2fmax
SQN R = 20 log √
− 10 log
(2.21)
36
fs
2fs
If the frequency modulator is already implemented in the signal source, we may for FD
applications, express it as
3 √ ∆f
π2 2fmax
SQN R = 20 log
2
− 10 log
(2.22)
fs
36
fs
Compared to the traditional ∆-Σ modulator, the output signal range in the D flip-flop
FDSM will for a high fs /fc ratio be very small, and by locating the output signal range well
27
away from the main pattern noise peaks illustrated in Fig. 1.6, we may achieve a slightly
higher SQNR than the theoretical value since the pattern noise problem in this way may be
eliminated.
System-level simulations
A high-level D flip-flop FDSM simulator have been made (see Appendix B), and by
following the same procedure as in the previous section, the psd is estimated by FFT analysis
of the ideal output bit-stream. Several simulations have been carried out, and in Fig. 2.13b,
the estimated output psd is shown for a D flip-flop FDSM with fs =100MHz, fc =40MHz
and a maximum frequency deviation of ±10%.
a)
b)
Figure 2.13: A 218 point FFT analysis of the D flip-flop FDSM output for max input amplitude.
Input signal frequency 3439Hz, fs =100MHz, fc =40MHz. a) 35/65 FM duty cycle. b) 50/50 FM
duty cycle
As we see, the noise spectrum is shaped according to the theory with a slope of ≈20dB/decade.
There are some high-frequency pattern noise, but for low and medium frequencies, the spectrum is quite smooth. Compared to the basic modulo-22 spectrum shown in Fig. 2.10, the
SQNR will from Eq. 2.18 and Eq. 2.22 be increased by ≈35dB, and we should expect the
noise floor to be lowered by 35-10·log(100MHz/2MHz)≈18dB. As we see, the noise floor is
further lowered by almost 10dB, which is a consequence of the signal range location in the
quantization level interval and the low signal range. To illustrate the effect of duty-cycle
deviations, the same simulation was done with a FM duty cycle of 35/65, and as we see
from Fig. 2.13a, the noise floor is just slightly raised.
2.5
The pointer-FDSM
In some applications the frequency modulator can be implemented as a ring oscillator,
where the propagation delay of each inverter is modulated by the input signal. Dependent
on the architecture, the modulating signal may be given either as a current or as a voltage or
even as a directly measured physical parameter. Examples are: Current controlled bipolar
ring oscillators [20], acceleration modulated ring oscillators, and pressure modulated ring
oscillators where the inverters are located on a silicon membrane. A particularly simple
28
voltage controlled oscillator (VCO) may also be implemented by standard CMOS inverters
connected in ring where the frequency is modulated by the inverter power supply voltage.
Although the exact relationship between the power supply voltage and the loop frequency
is quite complex, Spice simulations indicates that the loop frequency is a surprisingly linear
function of the power supply voltage over a large range as shown in Fig. 2.14.
6
14
x 10
12
Frequency (Hz)
10
8
6
4
2
0
1
1.5
2
2.5
3
3.5
Input (Volt)
4
4.5
5
5.5
Figure 2.14: The frequency of a 15-inverter CMOS ring-oscillator as a function of the inverter
power supply voltage simulated by Spice. The straight line is fitted to the simulated data by linear
regression
In such a VCO, there will be no power supply noise in the traditional sense. By considering the ring oscillator itself as a modulo-m counter, we may both simplify the FDSM,
and increase the resolution. The ring oscillator node values may be considered as a cycling
binary state vector with 2m different states where m is the number of nodes or inverters as
illustrated in Fig. 2.15.
0
1
0
1
0
0
1
0
3
2
1
1
1
1
0
0
0
1
1
1
0
Figure 2.15: The different states of a 3-inverter ring-oscillator
The operation of the ring oscillator may be described by a transition edge running
through all inverters in sequence, and by looking at the state diagram, we realize that
at a given time instant, all neighboring nodes will, apart from the two at each side of the
edge, have their complementary values. The logical XNOR or equivalence function between
each neighboring nodes will therefore provide a active high ”pointer” output which will
run through all nodes in sequence with a loop frequency twice the overall ring oscillator
frequency. By sampling the node values by D flip-flops, and generating the logical XNOR
between each neighboring nodes, the m bit pointer vector consisting of one ”1” and m − 1
29
binary encoder
’0”s may be fed to a binary encoder, providing a sampled modulo-m representation of the
state of the oscillator Fig. 2.16.
4-bit
reg
borrow
_
+
_
+
4-bit
modulo-15 output
word-stream
4-bit
Figure 2.16: A 15-inverter pointer-FDSM. The outer ring symbolize the individual D flip-flop and
XNOR units
The output may then be differentiated to form a modulo-m representation of the number
of pointer shifts during Ts . Compared to counting each rising FM edge, the pointer-FDSM
will therefore, in addition, provide quantized phase information by counting 2m times for
each overall FM period and thereby increase the resolution.
The maximum number of pointer shifts during Ts will be Ts /(τ0 − τ0 δτ ) where δτ is the
maximum deviation in propagation delay relative to the unmodulated propagation delay of
one inverter τ0 . Together with the minimum number of pointer shifts Ts /(τ0 + τ0 δτ ) the
effective output signal range will be
SRo =
Ts
Ts
2δτ
−
=
τ0 (1 − δτ ) τ0 (1 + δτ )
fs τ0 (1 − δτ 2 )
(2.23)
and for δτ 1 it may be simplified to
SRo =
2δτ
fs τ0
(2.24)
As we see, the SRo is proportional to the maximum relative propagation delay deviation, and
inversely proportional to the sampling frequency and the unmodulated inverter propagation
delay. From Eq. 2.24 we also notice that for a given inverter propagation delay, the resolution
of the pointer-FDSM is independent of the number of inverters. The minimum number of
inverters or module must however still be larger than int(SRo + 2) to avoid signal aliasing.
The ring-oscillator carrier frequency may be expressed as
fc =
1
2τ0 m
(2.25)
Since the maximum relative frequency deviation ∆f /fc will be equal to δτ , we may also
express the output signal range as
SRo =
2m∆f
fs
(2.26)
which is 2m times larger than for the basic modulo-2n FDSM.
However, since the number of inverters m, in a ring oscillator must be odd, the output of
the binary encoder can not be represented in modulo-2n arithmetic, and a standard binary
30
subtractor can not be applied. To overcome this obstacle, some extra logic is required. By
using 2n − 1 inverters, and two binary subtractors as illustrated in Fig. 2.16, we achieve a
modulo-m represented output difference, and by finally adding a proper bias modulo-2n to
the result, we arrive with a standard represented output. The modulo-m subtraction may
probably be implemented in a simpler way, but this proposal just illustrates the principle. In
a practical implementation, there will be process dependent deviations amongst the different
inverter delays and within the D flip-flop thresholds. Such errors may be considered as phase
offsets and will as duty-cycle deviations be systematic errors. Simulations indicates that the
effect of phase offsets will, in the overall SNR, correspond to the effect seen by duty cycle
diversions in the D flip-flop FDSM, and will thus be of less significance. If the unmodulated
and maximum inverter delay is given, the SQNR of the pointer-FDSM will be
3 δτ
π2 2fmax
√
SQN R = 20 log
(2.27)
− 10 log
36
fs
fs τ0 2
If the ring oscillator carrier frequency and max frequency deviation is given, we have
3 √ ∆f
π 2 2fmax
SQN R = 20 log m 2
− 10 log
(2.28)
fs
36
fs
For the same fc and ∆f , we notice that the dynamic range is increased by m compared to
the D flip-flop FDSM.
System-level simulations
Several system-level simulations have been carried out to verify the theory and the ideal
behavior of the pointer-FDSM. In Fig. 2.17a, the estimated psd for a 15-inverter pointerFDSM output is shown. A 3.33ns inverter propagation delay is chosen which will provide
a carrier frequency of ≈10MHz. The input is a single sinusoidal signal with maximum
amplitude and a frequency of 100Hz. The maximum frequency deviation is set to 5%. As
we see, the spectrum is shaped according to the theory. Compared to the basic modulo-2n
FDSM spectrum in Fig. 2.10, the noise floor should from Eq. 2.18 and Eq. 2.28 be lowered by
≈24dB which is close to the simulated result. In Fig. 2.17b, the same simulation is carried
out for randomly chosen phase offsets in the range [0, 1 rad. As we see from the figure, the
noise floor is not significantly raised, and due to the dithering effect it is slightly smoother
than for the ideal simulation.
An application example
For the specific pressure sensor (hydrophone) developed by Schlumberger-Geco-Prackla,
the sensor was implemented as a ring-oscillator mounted on a silicon membrane. The membrane is then exposed to a differential pressure causing stress in the silicon substrate. This
stress modulates the transistor β parameter, causing a modulation in the ring-oscillator frequency. Sensor output specifications are: digital resolution 20bit, signal bandwidth 400Hz,
maximum sampling frequency 2MHz and relative frequency deviation ∆f /fc . For a pointerFDSM with ∆f /fc=0.1, the SQNR will from Eq. 2.28 be 128dB, and from the simulated
result in Fig. 2.17a we may conclude that this ring oscillator will provide the necessary
resolution.
31
a)
b)
Figure 2.17: A 218 -point FFT analysis of a 15-inverter pointer-FDSM output. Input signal frequency 100Hz, fc =10MHz, fs =2MHz and ∆f =500KHz. a) Ideal modulator. b) Modualtor with
random phase offsets
Differential operation
To reduce the impact from common mode noise, differential architectures are widely used.
In the FDSM system, a differential realization seems to require two independent frequency
modulators, and the single FDSM output may then be implemented by subtracting the
output from the original counter from the reference counter output. The new quantization
error will then be the difference between the original quantization error and the reference
signal quantization error. Since there are no correlation between the two quantization errors,
the new quantization error pdf will have a√triangular shape spanning from -1 to +1, and
its mean square value will be a factor of 2 times the original mean square value. For
differential operation, the output signal amplitude will be doubled and the result is a net
SQNR gain of ≈3dB. On the other hand, if the reference oscillator is not modulated, a loss
of ≈3dB will result.
2.6
Feature and performance characterization of the firstorder FDSM
In the following sections, the different features of the first-order FDSM system will be
compared to the traditional ∆-Σ modulator.
Pattern noise
As we have seen, the FDSM is mathematically equivalent to a traditional ∆-Σ modulator
where the input signal is scaled and biased. Therefore, the pattern noise properties are
expected to be the same as in the traditional ∆-Σ modulator. For the basic modulo-2n and
the pointer-FDSM, the output signal rms value may however, due to multi-bit quantization,
be large compared to the pattern noise. For the D flip-flop FDSM, the output center value
will be fc /fs , and by locating this value well away from the main DC pattern noise peaks,
the pattern noise problem is expected to be eliminated for small signal ranges.
32
DAC output levels
Due to the absence of a DAC, problems due to misplaced DAC output levels will be
eliminated, and multi-bit quantization is straightforward.
ADC thresholds
In the FDSM, the counter value must be considered as a quantized analog value as the
counter is asynchronous. By sampling the counter value, both quantization and sampling
have been executed, and an equivalent AD conversion have been carried out. In the basic
modulo-2n FDSM, the single counter threshold which is used to decide if the FM signal is
high or low, may be placed anywhere it will be convenient from a digital consideration. In
the D flip-flop and the pointer-FDSM, there will in a practical implementation, be some
duty-cycle and phase deviations from the ideal. These deviations may be considered as misplaced ADC thresholds, but due to the differentiation, the baseband noise will be heavily
suppressed. As opposed to the traditional ∆-Σ modulator, these errors will be very little
correlated with the input signal, and as the simulations indicates, have less practical significance. Such errors should however be minimized as large offsets may slightly degrade the
overall SNR.
ADC overloading
Since the ADC is implemented by a counter and the number of output levels may easily
be chosen larger than the output signal range requires by increasing the internal word length,
problems due to ADC overloading is eliminated.
Integrator errors
In a frequency modulator, there will be no leakage, charge injection and slew-rate limitations, and for the FDSM, the only limiting factor for high sampling speed, will be metastability effects in the synhrounizing circuits [21, 22]. The main problem is however the fact
that frequency modulating noise in the frequency modulator will add directly to the signal.
Dependent on the architecture of the frequency modulator and the application, harmonic
distortion may be a problem. By reducing ∆f /fc, the maximum non-linearity of a frequency
modulator will normally decrease, and due to the high resolution of the ∆-Σ modulator, a
low ∆f /fc may be utilized to reduce harmonic distortion. If the frequency modulator is
already implemented in the signal source, the FDSM concept may therefore be used to
improve harmonic distortion in a FD system by enabling the use of a lower ∆f /fc ratio.
External noise
In the FDSM system as in the traditional ∆-Σ modulator, several external noise factors
will be present. As we have both the signal and its integral represented in the circuit, we may
differ between noise that affects the signal (frequency modulating noise) and noise that affect
the integral of the signal (phase modulating noise). In general, phase modulating noise will
due to the differentiation be first-order noise shaped, and will normally be of no significance
compared to the quantization error. In this category we have sampling clock jitter, power
supply noise in the θn detector/quantizer and digital/transmission noise deteriorating the
intermediate FM signal. Frequency modulating noise will however directly add to the signal,
and must be carefully considered. In this category, we may, depended on the architecture,
have power supply noise in the frequency modulator, and low frequency noise caused by
33
the frequency modulator sensitivity to temperature drift. By using a reference frequency
modulator, the impact from such factors may be significantly decreased. Another noise
source that should not be overlooked, is frequency modulating noise in the sampling clock
oscillator. By using an intermediate FM signal, the sampling clock frequency must be
considered as a reference signal, and a frequency stable clock oscillator must be used. By
using a reference modulator we convey the stability requirement from the clock oscillator
over to the reference input signal.
The integrator-differentiator combination
As in a conventional ∆-Σ modulator, by using an analog loop filter, the frequency response of the continuous-time integrator - discrete-time differentiator combination is not
constant. The impulse response of a continuous-time integrator is given by H i (jω) = 1/jω,
and in the frequency interval |ω| < 2πfs /2, the Fourier transform of the sampled impulse response sequence is Y (ejωTs ) = fs H i (jω). Together with the accumulator frequency response
H a (ejωTs ) = (1 − e−jωTs ), the overall frequency response will be
H(ejωTs ) = fs H i (jω)H a (ejωTs ) =
fs (1 − e−jωTs )
,
jω
|ω| ≤ πfs
(2.29)
and the magnitude will be
sin(ω/(2fs ))
,
|ω| ≤ πfs
(2.30)
ω
Due to the single pole at zero, the maximum in band signal suppression will be seen for
the maximum signal frequency, and the low pass filtering effect will be most noticeable
for systems with a low OSR. But as an example, for fs = 1M Hz and fmax = 20KHz
which corresponds to an OSR as low as 25, the maximum signal amplitude deviation in the
passband will be
|H(ejωTs )| = 2fs
|H(ej2π0·Ts )| − |H(ej2πfmax Ts )| = −145dB
(2.31)
As we see, the continuous-time integrator - discrete-time differentiator combination causes
no practical problems.
Implementation
The implementation of a FDSM system is very different from the implementation of a
traditional ∆-Σ modulator, and the frequency modulator may, dependent on the application,
be implemented in several ways. If the input signal is already given as a FM carrier, the
necessary extra circuitry will be purely digital. The CMOS pointer-FDSM where the carrier
frequency is modulated by the inverter power supply voltage, is an example which illustrates
an AD converter build exclusively by digital components, and a standard digital CMOS
process may be used. By, in this way, using only a few digital components, a low power
supply voltage operation and a reduced power consumption is possible.
34
35
Chapter 3
Extended FDSM techniques
In this Chapter four novel FDSM techniques will be presented and analyzed. We will start
by looking at the undersampled FDSM.
3.1
FM signal undersampling
In some frequency demodulation applications it may be desirable to move the frequency
demodulator and the ADC as close as possible to the antenna. In a FDSM based system this
means that the incoming frequency to the FDSM may be very high. If the digital resolution
requirement is low, the chosen sampling clock frequency may be much lower than the FM
carrier frequency. For systems where the sampling frequency is lower than 2(fc + ∆f ), a
multi-bit FDSM should be used according to the discussion in Section 2.4. In a multi-bit
FDSM running at very high frequencies, the maximum operation frequency will be limited
by synchronizer metastability effects [21, 22]. If a very high frequency operation is required,
the synchronizing elements of the FDSM should therefore be kept as simple as possible, and
the D flip-flop FDSM will normally be the best candidate. From Eq. 2.18 and Eq. 2.22
we also notice that the D flip-flop FDSM provides ≈6dB higher SQNR than the standard
counter-based FDSM since both FM edges are counted. On the other hand, by using a
D flip-flop FDSM and increasing the sampling frequency to 2(fc + ∆f ), this frequency is
now more than twice the FM frequency and if we try to push the limit of the processing
technology, the sampling frequency may now be the limiting factor. In this way, the power
consumption, particularly in the decimator, will also be much higher than necessary.
In the following, we will propose a solution to this problem by proving that the simple
D flip-flop FDSM may also be used in applications where the sampling frequency is lower
than 2(fc + ∆f ) by using the alias of the FM signal. To illustrate this idea we will start by
looking at the undersampling FDSM from a time-domain view, and continue by analyzing
the converter in the frequency-domain.
3.1.1
Time-domain analysis
The D flip-flop FDSM is based on both modulo-2 edge counting and modulo-2 differentiation. The modulo-2 edge counter output is represented by the “logical” value of the limited
FM signal, and the modulo-2 differentiator is implemented by a XOR gate as illustrated in
Fig. 3.1.
36
fclk
fm
fclk
clk
clk
DQ
DQ
out
Figure 3.1: The standard D flip-flop FDSM
This modulo-2 wrap-around error cancellation scheme works well as long as the counted
number of FM edges during the sampling interval is 0 or 1, which is true for sampling clock
frequencies higher than 2(fc + ∆f ). However, by using a multi-bit FDSM running at a
sampling frequency lower than 2(fc + ∆f ), the output will, for low FM deviations, be m or
m + 1 where m is an integer given by the sampling clock frequency to the FM carrier ratio.
In other words, for low FM deviations, the number of counted edges during 1/fclk will be
limited to two adjacent integers. But in this case, if we do not need the bias component
m, modulo-2 arithmetic will accommodate the FDSM output signal and we may use a D
flip-flop FDSM. From this intuitive discussion we realize that for certain fclk /fc and ∆f
combinations we may use a D flip-flop FDSM even if the sampling frequency is less than
2(fc + ∆f ).
To put it in another way, what we should do is to make sure that the sampling clock
frequency is chosen so that we omit certain (fc ± ∆f )/fclk ratios. To find these ratios we
notice that the highest possible variation in FM edge counts will occur when the previous
sampling edge is close to an FM edge (Fig. 3.2). This is because a small phase variation on
the sampling signal will either include or exclude the first FM edge.
fm(t)
clk(t)
Figure 3.2: FM signal relative to sampling clock. Shaded areas indicate ambiguous regions.
In Fig. 3.2 the shaded regions illustrate the maximum phase deviation of the FM signal.
So, depending on the modulating signal, the FM zero-crossings will be restricted to these
intervals. To restrict the FDSM outcome to m or m + 1 we therefore must ensure that the
next sampling edge do not occur in one of these shaded regions. Otherwise the number of
FM edges during 1/ff clk may be m, m + 1 or m + 2 as the previous sampling edge may
be located both on the left and on the right side of the corresponding FM edge. Since we
have lined the previous sampling edge up to a FM edge, this frequency constraint can be
formulated in the following way; the number of FM edges per second must not be divisible
by the sampling frequency or
2(fc + δf )
−∆f < δf < ∆f
= m,
(3.1)
m∈N
fclk
This statement may be formulated as
fclk ∈ [2(fc − ∆f )/m, 2(fc + ∆f )/m], m ∈ N .
37
(3.2)
For a given m, the allowed sampling frequencies will then be all frequencies in between the
shaded intervals in Fig. 3.2 which from Eq. 3.2 is
fclk ∈ 2(fc + ∆f )/(m + 1), 2(fc − ∆f )/m, m ∈ N .
(3.3)
By reducing the sampling frequency for a fixed fc , m increases and the intervals in between
the shaded regions decreases. For a certain m, the lower limit and the higher limit in Eq. 3.3
will be switched, and there will no longer be room to locate the sampling edge. To find this
maximum m or ‘squeezing’ limit the following statement must be true
2(fc + ∆f )/(m + 1) < 2(fc − ∆f )/m, m ∈ N
(3.4)
and we have the following limitation on m
m<
fc −∆f
2∆f ,
m ∈ N.
(3.5)
For a D flip-flop FDSM, the minimum sampling frequency will then from Eq. 3.3 be
2(fc + ∆f )
.
(3.6)
mmax + 1
By approximating mmax by (fc − ∆f )/2∆f , and assuming fc ∆f , the minimum
sampling clock frequency may be approximated by
min
fclk
=
min
fclk
≈ 4∆f
(3.7)
It should be emphasized that this is a theoretical limit. In a practical implementation,
one should also make room for phase noise.
In Fig. 3.3 the D flip-flop clock usable range is illustrated for two different ∆f . Upper
graph - fc =400MHz, ∆f =10MHz. Lower graph - fc =400MHz, ∆f =5MHz. The inclining
line segments illustrate the usable clock range given by Eq. 3.3. Above 2(fc + ∆f ) the range
is comprehensive as the converter operates in FM oversampling mode. For the case where
∆f =10MHz the “squeezing” limit frequency, illustrated by point g, is twice as high as for
∆f =5MHz.
3.1.2
Frequency-domain analysis
The undersampling operation may also be analyzed in the frequency domain by looking
at the frequency content of the FM signal. The most intuitive point of view will be to look
at a very low frequency modulated carrier and model it as a single tone varying in frequency
with the amplitude of the modulating signal (Fig. 3.4).
By this approach the maximum and minimum frequency will be given by fc + ∆f and
fc − ∆f respectively. Since the FM signal is immediately digitized by the first D flip-flop,
we may equivalently model this operation by assuming a square wave FM signal and the
D flip-flop to be an analog-to-digital converter with infinite amplitude resolution. In this
case the continuous-time, square wave FM signal spectrum will consist of odd harmonic
components as illustated in Fig. 3.4. The maximum deviation from the center frequency in
each harmonic group will be proportional to the harmonic center frequency as illustrated in
the figure.
For modulating signals at medium or high frequencies we should rather look at the FM
spectrum as a carrier frequency with two symmetrical sidebands given by the modulating
signal amplitude and frequency. For sinusoidal modulation, the modulating index [17] is
defined as
38
130
125
a
120
cb
d
f
SQNR (dB)
115
e
110
g
105
100
90
4∆f1
4∆f2
fc
100MHz
Sampling frequency fclk (Hz)
2fc+∆f1
2fc+∆f2
95
1GHz
Figure 3.3: Usable sampling clock ranges for the D flip-flop FDSM. Upper graph - fc =400MHz,
∆f =10MHz. Lower graph - fc =400MHz, ∆f =5MHz. a,b,c) - FM oversampling mode, d,e,f ) undersampling mode, g) “squeezing” limit
β=
∆f
fm
(3.8)
where fm is the frequency of the modulating sinusoidal. For β > 1 the FM signal is described
as wide-band and the required bandwidth is 2∆f according to Carlsons rule [17]. For β < 1
the FM signal is described as narrow-band and the required bandwidth is 2fm . For nonsinusoidal modulation we normally refer to the deviation ratio given by
D=
∆f
fmax
(3.9)
where fmax is the highest frequency component in the modulating signal. By using the
deviation ratio we implicitly assume that the FM signal may be wide-band modulated as
the modulating signal may contain all frequencies from 0 − fmax .
In Fig. 3.5 top, the spectrum of a wide-band modulated square-wave FM signal is illustrated. To simplify the picture, both sidebands are symbolized as a square box also containing the carrier frequency. For higher harmonics the bandwidth increases proportional to
the harmonics number, while the power density is proportional to −20 log(k) where k is the
harmonic number. By sampling the square-wave FM signal, all harmonics above half the
sampling frequency will fold down to the sampling interval as illustrated in Fig. 3.5 bottom.
If the sampling frequency is lowered, the position of these harmonic bands will change, and
39
PSD
∆f
3∆f
fc
0
5∆f
3fc
7∆f
5fc
9∆f
7fc
9fc
f
Figure 3.4: The continuos-time square-wave FM signal spectrum represented as a single tone varying in frequency with the amplitude of the modulating signal
0
PSD (dB)
-10
-20
fc
3fc
5fc
7fc
9fc
0
-10
-20
fc
fclk-fc
fclk
Figure 3.5: Top - the continuous-time square-wave FM signal spectrum represented by a carrier
component with two symmetrical sidebands (all in one box) and its higher-order harmonic components. Bottom - the sampled FM signal
at certain fclk /fc ratios the high-power lower harmonics bands, will interfere with the original FM band. By looking closely at the situation for different fclk /fc ratios, it seems like
this effect corresponds very closely to the effect of pattern noise. In this way pattern noise
is described as interference between the original FM band and its higher harmonic bands. It
should be mentioned that this relationship have not been proven analytically, but threre are
indications that this can be an alternative model for pattern noise. In Fig. 3.6 the sampled
FM signal power spectrum is illustrated for different sampling frequencies corresponding to
point a-g in Fig. 3.3. In the following, each point will be commented.
• Point a: The sampling frequency is 1.3GHz corresponding to point a in Fig. 3.3. In
this case the FM signal is well oversampled and we notice some low power harmonic
interference.
• Point b: The clock frequency is lowered to 860MHz. The FM signal is still oversampled, and the upper mirror signal band is approaching the original main signal
band at fc − ∆f, fc + ∆f . There is no noticeable harmonic interference although the
high-power second harmonic signal bands are quite close.
• Point c: The sampling frequency is lowered to 2(fc + ∆f )=820MH which is the
minimum FM oversampling frequency. In Fig. 3.6 c we notice that the main signal
band is touching its mirror band at fc + ∆f, fc + 3∆f and there is heavy interference
with all harmonic signal bands.
40
• Point d: The FM signal is undersampled at 668MHz and the main signal band has
exchanged position with its mirror band. In this case, the FDSM will demodulate the
FM mirror band. By further lowering the clock frequency the FM mirror band will
move towards zero frequency while the original FM band will be closer to the sampling
frequency.
• Point e: The clock frequency is 410MHz corresponding to the lower end of the line
segment if Fig. 3.3. From the time-domain analysis given by Eq. 3.3 this is the lowest
clock frequency where the FDSM output is restricted to m=1 and m=1+1. From
Fig. 3.6e we notice that this is the point were the original FM signal band at fc −
∆f, fc + ∆f starts to interfere with the mirror band at fclk + (fclk − [fc + ∆f ]), fclk +
(fclk − (fc − ∆f )). There is heavy harmonic interference.
• Point f: The clock frequency is 362MHz and the FDSM output is restricted to m=2
and m=2+1. From the frequency spectrum we see that in the clock frequency band,
there are two mirrors of the original FM signal band, and the FDSM will now demodulate these two images instead of the original FM band at fc − ∆f, fc + ∆f . We also
notice that the two FM mirror bands and the harmonic signal bands occupy a larger
fraction ot the sampling clock band.
In Fig. 3.7 the sampling clock frequency is lowered to 41MHz which is close to the
squeezing limit shown as point g in Fig. 3.3. From the frequency spectrum we see that the
squeezing limit in the time-domain corresponds in the frequency-domain to the situation
where there is no longer room for narrowing the sampling interval as the two FM mirror
bands occupies the complete interval. A further decrease in fclk will now make the two signal
band interfere with each other causing signal distortion. To decribe the resulting distortion
in the demodulated signal caused by FM mirror band interference is a complex affair, as the
demodulation process is non-linear. We may however now look at the time-domain behavior
by inspecting the demodulated signal.
In Fig. 3.8 the demodulated signal is plotted both against time and frequency for
fclk =82.3MHz. In this case the FM signal is moderately undersampled. There are no
visible distortion as the FDSM output is restricted to m=9 and m=10. The SQNR was estimated to 107dB which is very close to its theoretical value of 108dB (Eq. 2.22). In Fig. 3.9
right, the sampling frequency was set to 400MHz which is in center of the ambiguous interval fc − ∆f, fc + ∆f from Eq. 3.2. The demodulated signal is now maximally distorted,
which we see corresponds to a rectifying operation. In Fig. 3.9 left the sampling frequency
is slightly biased away from 400MHz but is still in the ambiguous region. In this case, we
see the distortion as biased rectifying.
Finally, in Fig. 3.10 a 1·106 point FFT analysis of a sampled square-wave FM signal is
shown. In this example the carrier frequency was set to 400MHz, the maximum frequency
deviation - 10MHz and a 2KHz modulating sinusoidal was used. The sampling frequency
was set to 668MH which make the parameters identical to point d in Fig. 3.6. The plot is
shown for the 0-fclk /2 range, and we notice that both the FM mirror band and its major
harmonics bands are present at the same places and with the same power densities that in
Fig. 3.6 d.
Comment on FM bandwidth
In this frequency analysis we have assumed a wideband modulated FM signal, as the
modulating signal generally may contain low frequency components. For narrowband FM
signals the FM bandwidth will be given by fc − fm , fc + fm where fm is the lowest
41
frequency component of the modulating signal. In this case the FM signal band and its
mirror bands will occupy a smaller fraction of the sampling interval and the squeezing limit
will be somewhat lower. This will also slightly increase the usable frequency intervals of
Eq. 3.3.
42
0
a) -10
-20
fclk
2fclk
3fclk
0
b) -10
-20
fclk
2fclk
3fclk
4fclk
0
PSD (dB)
c) -10
-20
fclk
2fclk
3fclk
4fclk
5fclk
0
d) -10
-20
fclk
2fclk
3fclk
4fclk
5fclk
0
e) -10
-20
fclk
2fclk
3fclk
4fclk
5fclk
6fclk
7fclk
8fclk
9fclk
0
f) -10
-20
fclk
2fclk
3fclk
4fclk
5fclk
6fclk
7fclk
8fclk
9fclk
10fclk
11fclk
PSD (dB)
Figure 3.6: The sampled FM signal spectrum for different sampling frequenies
0
-10
-20
fclk
2fclk
Figure 3.7: The sampled FM signal spectrum for fclk =41MHz illustrating the squeezing limit
43
500
450
Amplitude
400
350
300
250
200
150
100
50
2.6
2.65
2.7
2.75
Sample no.
2.8
2.85
4
x 10
Figure 3.8: Left - demodulated signal, fclk =82.3MHz. Right - estimated spectrum
350
250
300
200
Amplitude
Amplitude
250
200
150
150
100
100
50
50
0
3.34 3.36 3.38 3.4 3.42 3.44 3.46 3.48 3.5 3.52 3.54
4
Sample no.
x 10
0
2.54
2.56
2.58
2.6 2.62 2.64
Sample no.
2.66
2.68
4
x 10
Figure 3.9: Right - demodulated signal, fclk =400MHz. Left - fclk slightly increased
Figure 3.10: A 1·106 point FFT analysis of a sampled square-wave FM signal. fc =400MHz,
∆f =10MHz, fm =2KHz and fclk =668MHz
44
3.2
The sampled-clock FDSM
Although the first-order FDSM provides first-order ∆-Σ noise-shaping, the SQNR is only
increased by ≈3dB for each doubling of the sampling frequency (Eq. 2.18). This is because,
a doubling of the sampling frequency decreases the noise power by ≈9dB, but in addition,
the FDSM signal range is decreased by ≈6dB resulting in a net SQNR gain of ≈3dB. In
a FDSM, a more effective way to increase the resolution is to increase the FM deviation.
By doubling the deviation, the SQNR will increase by ≈6dB. If the FM signal source has a
constant ∆f /fc ratio, as it may be in a modulated ring-oscillator, a doubling of fc will now
double the SQNR. However, in many applications both the FM carrier frequency and its
deviation is already given and the only thing to play with is the sampling clock frequency.
In Fig. 3.11 a typical FDSM frequency-to-digital system is shown. The front-end is the
FDSM followed by a decimator. In the other end of the system, we have the user of the
demodulated digital signal. In many cases, the user is a non-human digital system running
at the same system clock as the FDSM. In other cases the user is a human listening to or
looking at the data provided via an ADC or visualized on the computer screen. From now
on we will denote this kind of system as a “sampled signal” system as we are sampling the
FM signal with the system clock.
mod-2n
counter
fm
reg
fclk
mod-2n
diff
cnt
decimator
user
reg
FDSM
Figure 3.11: A standard modulo-2n “sampled signal” FDSM system
In a FDSM system as illustrated by Fig. 3.11, the information given to the user is high
quality information about the ratio of the instantaneous FM frequency to the system clock
frequency, as this ratio is proportional to the modulating signal. If the FDSM module is
chosen larger than the maximum number of positive edge counts during 1/fclk , the FDSM
output mean value will, from Eq. 2.16 be
ȳn =
f¯FM
fc + kx̄n
=
fclk
fclk
(3.10)
assuming low-frequency modulation. Here, xn is the modulating signal. From the previous
discussion we saw that by doubling the sampling clock frequency, the SQNR increase was
only ≈3dB, and by doubling the signal frequency fc and ∆f on the counter input, the SQNR
increase was ≈6dB. If the target is high SQNR, this is good for applications where we are
free to choose a high FM deviation. However, if the FM deviation is already given, but we
are able to use a very high sampling frequency we do not achieve to much.
45
As the system output represents the ratio of the instantaneous FM frequency to the
sampling frequency we may ask if it could be possible to exchange the FM and clock input
to the system and still keep information about the modulating signal. By doing so, we
may utilize the higher gain in SQNR resulting from the high frequency clock signal on the
counter input. By exchanging the two signals the FDSM output will, now with high quality,
represent the ratio of the clock frequency to the FM frequency, provided that the FDSM
still shapes its quantization error. Since the modulating signal now is in the denominator,
the FDSM transfer function will be non-linear, and the output mean value will be
fclk
fclk
ȳn,sc = ¯
=
f
fFM
c + kx̄n
(3.11)
Max relative non-linearity error (dB)
By fitting this function to an ideal linear characteristic, the maximum relative non-linearity
is plotted against ∆f /fc in Fig. 3.12.
-50
-60
-70
-80
-90
-100
-110
0.001
0.1
1
10
∆f / fc (%)
Figure 3.12: Maximum non-linearity error relative to signal range versus ∆f /fc
As we see from the figure, for low ∆f /fc ratios the non-linearity distortion is quite low.
For example if the FM carrier frequency is 40MHz and the FM deviation is 100KHz, the
relative non-linearity will be ≈-103dB. On the other hand, for high ∆f /fc ratios the nonlinear error will be deterministic and given by Eq. 3.11. In contrast to stochastic non-linear
errors given by process variations, temperature drift an so on, this kind of error is relativerly
easy to compensate for by following the decimator by a non-linear digital filter employing
the inverse function.
Another factor that must be taken into consideration it that by applying the FM signal
to the system clock input, the entire system will operate on a time-varying or non-uniform
timebase as shown in Fig. 3.13. To distinguish this kind of system from the sampled-signal
system we will refer to it as a sampled-clock system, as we are sampling the constant clock
frequency with the FM signal.
Depending on the user this may be acceptable or not. If the user is a large digital system
where the FDC is only a minor component this could be a problem. However, if the FDC
is a main part of the system this can, in many applications, be acceptable.
Finally, to be able to use the sampled-clock system we need to show that this system
also shapes the quantization error according to ∆-Σ theory. It is possible to prove that the
system employs ∆-Σ noise-shaping by modeling the system on a non-uniform time-base.
46
mod-2n
counter
fclk
reg
fm
mod-2n
diff
cnt
decimator
user
reg
FDSM
Figure 3.13: A modulo-2n “sampled clock” FDSM system.
However, this is not an easy way to go. In the following section, we will therefore show the
∆-Σ equivalence simply by introducing the concept of virtual frequencies.
3.2.1
Virtual frequencies
What is time? This not a simple question to answer. Most people take it for granted that
time is linear and timesteps are uniformly distributed. On the other hand, a distribution
must always be in reference to something else. By looking at the modulated FM carrier we
say that its zero-crossings are modulated or non-uniform with reference to the clock signal.
In the following, we will change the point of view and say that the clock signal’s zerocrossings are modulated with reference to the FM signal which we consider to be constant.
This change of time-base is possible because we are dealing with a digital or sampled-time
system where nothing is happening in between the sampling time-steps. From the sampledclock FDSM system this new time-base makes it easy to model the behaviour of the system.
With this new time-base, the FM frequency is now virtually constant and the clock signal
on the FDSM input is virtually varying with time. However, to be able to utilize this
simplified description we need a model of the virtual frequency on the FDSM input. As a
frequency modulated signal, this virtual frequency will be on the form fclk + k xn , where
k is a constant and xn is the virtually modulating signal. To proceed with this analysis we
will make use of the following invariant:
The ratio between the real clock frequency and the real FM signal frequency
must equal the ratio between the virtual clock signal frequency and the virtual
constant FM frequency.
This invariant is fundamental for the idea of a change in time-base. Whitout this invariant, there will be no use in a timebase shift as the system analysis would not be simplified.
So, what we have is
fclk
fclk + k xn
=
.
fc + kxn
fc
(3.12)
The virtual clock signal frequency will therefore be
fclk + k xn =
fclk fc
.
fc + kxn
(3.13)
The sampled clock FDSM will now count each positive edge in the virtual clock signal and
thereby extract a quantized representation of the virtual clock signal phase θn /2π producing
47
a quantization error φ ∈[0, 1. The difference between this system and a sampled-signal
FDSM can now be modeled as a non-linearity in the modulating signal xn given by Eq. 3.13,
thus the ∆-Σ noise-shaping equivalence is verified.
The new output signal range SRo will now be given by the difference between the maximum and minimum number of counts during the sampling interval which is
SRo =
fclk
fclk
2fclk ∆f
−
= 2
,
fc − ∆f
fc + ∆f
fc − ∆f 2
(3.14)
In most cases ∆f will be reasonably lower than fc making ∆f 2 fc2 . In this case the
output signal range may be written as
SRo ≈ 2fclk ∆f /fc2
(3.15)
n
The resolution of the sampled clock modulo-2 FDSM will now be
3/2 SRo
π
fmax
√
SQN R ≈ 20 log
− 20 log
2
6
fc
2 2
(3.16)
By doubling the constant clock frequency fclk we notice that the SQN R is now increased
by ≈6dB.
3.2.2
The SC D flip-flop FDSM
For applications aiming at high SQNR where there is available a high frequency system
clock, the sampled-clock FDSM may be a better choice than the sampled-signal converter.
As in the sampled-signal converter, the maximum operation frequency will be limited by
metastability in the parts of the converter that are asynchronous to the system clock. For
this reason the FDSM implementation should be kept as simple as possible, and the D flipflop solution should be used if possible. In addition, the resolution of the D flip-flop FDSM
is ≈6dB higher than for the modulo-2n FDSM as it counts both positive and negative
edges in the input signal. By using the sampled-clock D flip-flop FDSM, a very high clock
frequency may be used providing a high SQNR. As the sampling frequency is given by the
FM frequency and not by the high-speed clock frequency, the FDSM output data rate may
be kept at manageable level, keeping the decimator power consumption down. One must
keep in mind that for applications where the minimum FM frequency fc − ∆f is lower than
two times the clock frequency fclk , the sampled-clock converter operates in undersampling
mode.
fm
fm
fclk
clk
clk
DQ
DQ
out
Figure 3.14: The sampled-clock D flip-flop FDSM
As for the sampled-signal D flip-flop FDSM, if the converter is used in undersampling
mode, there are certain fclk /fc ratios which must be avoided to keep the modulo-2 wraparound error cancellation scheme work properly. To find these frequencies we will start by
analyzing the converter in the time-domain.
48
Time-domain analysis
As in the sampled-signal case, to ensure proper operation, the FDSM output must be
restricted to m and m + 1 where m is an integer given by the number of received signal
edges during the sampling interval. In the sampled-clock FDSM we are now dealing with
the number of received clock edges during the FM signal period.
clk(t)
fm(t)
Figure 3.15: FM signal relative to sampled clock signal
In Fig. 3.15 the clock signal is plotted against the sampling FM signal and the FM
deviation is shown by a shaded region at the positive sampling edge. If the number of clock
edges during the FM period is to be limited to m and m + 1, there must be no clock edge in
the shaded region as the previous sampling edge may be at either side of the corresponding
clock edge. In other words, the double clock frequency must not be divisible by the FM
frequency or
2fclk
−∆f < δf < ∆f
= m,
(3.17)
m∈N
fc ± δf
Equivalently
fclk ∈ [
m
m
(fc − ∆f ), (fc + ∆f )],
2
2
m ∈ N,
(3.18)
or
m
m+1
(fc + ∆f ),
(fc − ∆f ),
m ∈ N.
(3.19)
2
2
As for the sampled-signal D flip-flop FDSM, we need to ensure that the left limit in Eq. 3.19
is lower than the right limit, and this will restrict m to
fclk ∈ m<
fc − ∆f
,
2∆f
m ∈ N,
(3.20)
The maximum constant clock frequency will now, from Eq. 3.19 be
mmax + 1
(fc − ∆f ).
2
For applications where ∆f fc , the maximum constant clock frequency will be
max
fclk
=
max
fclk
≈
fc2
4∆f
(3.21)
(3.22)
As we see, in the sampled-clock D flip-flop FDSM the, maximum clock frequency is proportional to the square of the FM carrier frequency and inversely proportional to the FM
deviation. In Fig. 3.16 this result is visualized by a plot of the SQNR against constant
clock frequency. The upper graph illustrates the usable clock range for an application with
fc =400MHz, fmax =5KHz and a maximum frequency deviation of 10MHz. In the bottom
graph, the deviation is reduced to 5MHz. We notice that although the resolution is reduced
49
with ≈6dB, the maximum resolution is the same as for the previous case as the squeezing
limit is increased. However, it will be difficult to utilize the new squeezing limit as the usable
clock intervals are now quite narrow, even if the plot is compressed for high frequencies. A
slight deviation in the fclk /fc ratio may now push the converter out of the usable range.
To confirm the result of this analysis and gain more insight in the sampling process we will
now continue with a frequency-domain analysis of the converter.
140
e
130
d
SQNR (dB)
120
110
b
c
a
100
Hz
M
10
=
∆f
Hz
M
=5
f
∆
90
80
10
Figure 3.16:
100
1000
Constant clock frequency (MHz)
10 000
SQNR for a sampled-clock D flip-flop FDSM application with fc =400MHz,
fmax =5KHz
Frequency-domain analysis
To find the bandwidth of the virtual FM signal we assume that the signal is wideband
modulated. By using Carlsons rule, we need to find the maximum deviation of the signal.
The virtual frequency devation on the clock signal will be the maximum deviation minus
the minimum deviation divided by two, which from Eq. 3.13 is
fclk fc
fclk fc
fclk fc ∆f
∆f =
−
/2 = 2
(3.23)
fc − ∆f
fc + ∆f
fc − ∆f 2
For most applications the carrier frequency is somewhat higher than the deviation, giving
∆f ≈
fclk ∆f
fc
(3.24)
So, the bandwidth of the virtual FM signal will be fclk −∆f , fclk +∆f and the bandwidth
will increase with the ffclk
ratio. The corresponding square-wave signal will have harmonic
c
bands at odd harmonic frequencies as illustrated in Fig. 3.17, top. By sampling the virtual
50
square-wave FM signal with the virtual constant frequency fc , the converter will operate
in undersampling mode if fc − ∆f < 2fclk . In Fig. 3.17 a-e, the virtual FM spectrum is
illustrated for different clock frequencies, and in the following, each case will be commented.
• Point a In this case fclk =75MHz and the converter operates in FM oversampling
mode. All harmonic signal bands are folded down to 0, fc , but there is no interference
between the main signal band and the major harmonic bands.
• Point b In this case fclk =195MHz, and the converter operates just on the limit of
FM oversampling mode. We notice that the main signal band is touching its mirror
band at fc − (fclk + ∆f , fc − (fclk − ∆f ). There is heavy harmonic interference.
• Point c In this case fclk =205MHz, and the converter operates in undersampling mode.
From Eq. 3.19 we see that this clock frequency is in the first usable interval given by
m=1, also corresponding to point b in Fig. 3.16. From Fig. 3.17 b, we notice that the
main signal band has exchanged position with the mirror band and the converter will
now demodulate the FM mirror signal. There is heavy harmonic interference.
• Point d In this case fclk =850MHz, and the converter operates in undersampling mode.
From Eq. 3.19 the clock frequency is in the fourth usable interval given by m=4.
• Point e In this case fclk is set to 1.3GHz illustrating the sqeezing limit in the frequency
domain. This limit correspond to the case where the two signal bands occupies the
whole sampling interval and there are no room for a further increase in fclk as the
signal bandwidth is proportional to fclk .
Simulations
When a ∆-Σ modulator is to be simulated care must be taken to control the effect
of numerical errors. Depending of the location of the error it will be noise-shaped or not.
The sampled-signal FDSM was simulated [7], Appendix B, in a loop where each time-step
n · 1/fclk , corresponds to the sampling clock edge. The FM phase θn is then calculated from
Eq. 2.7, which for sinusoidal modulation is given by
θn = 2πfc n/fclk +
∆f
sin(2πfm n/fclk )
fm
(3.25)
In this way there is no need to numerically estimate the time for the sampling clock edge, and
all errors will be present as round-off θn errors. As round-off θn errors will not accumulate
they will represent phase-noise, which we will from Section 4.1, see is first-order noise-shaped.
By using long-double constants in C, there have not been observed any simulation quality
degradation or break-down even for simulations running through hundreds of millions of
samples.
However, to simulate the sampled-clock FDSM, a different approach must be taken. If
each time-step should correspond to each FM sampling edge, the simulator needs to know
the time for each positive FM edge. Unfortunately, there exists no analytical expression
for Eq. 2.7 resolved with respect to t, so each time-step would have to be numerically
approximated. To simulate a FDSM where the oversampling ratio can be of more than
100 000 times, there is a need for a high number of samples to achieve sufficient frequency
resolution in the signal-band. For a simulation including more than a million samples, the
estimation of the time-step will be time consuming, and the number of numerical errors will
increase. To overcome this problem another approach is taken.
51
0
-10
-20
fclk
3fclk
5fclk
7fclk
0
a) -10
-20
fclk
3fclk
fc
2fc
3fc
fc
2fc
3fc
fc
2fc
3fc
fc
2fc fclk
3fc
fc
2fc
3fc
Normalized PDS (dB)
0
b) -10
-20
fclk
0
c) -10
-20
fclk
0
d) -10
-20
0
e) -10
-20
Figure 3.17: The virtual FM spectrum for different clock frequencies
By looking at Fig. 3.18 and Fig. 3.14 we notice that for each time there is a positive FM
edge the clock signal must be sampled, and this sampled sequence must then be modulo-2
differentiated. Even if the FM edge is in continuous time, there is actually no need to know
the exact position of the edge if we know which halve fclk period it occurs in. What we
need to know is which fclk value the edge is sampling, one, or zero. As long as we know
the correct sampling value, the exact position of the sampling edge does not matter in a
non real-time simulation. The D flip-flop sampled-clock FDSM is therefore simulated in a
loop where each time-step is given by n · 1/(2fclk ). The time-step is then inserted in the
expression for the FM angle, and if the angle have past a 2π period, the value of the clock
signal is fed to the decimator. If the FM angle have not past a new 2π period, nothing is
done. In this way the time-step do not have to be estimated, and the θn round-off error will,
even now be present as phase-noise.
In Fig. 3.19 the D flip-flop sampled-clock FDSM is simulated for a modulating sinusoid
52
n=k+10
n=k+9
n=k+1
n=k
T0=1/(2fclk)
clk(t)
fm(t)
Figure 3.18: FM signal relative to the sampled clock signal
of 233Hz. The FM carrier frequency was 712kHz with a frequency deviation ∆f , of 7100Hz.
By applying a clock frequency of 12636220Hz, the FDSM output will be restricted to m=35
and m=36. A number of 32 millions clock samples was simulated decimated by 2, and the
result is seen in the figure. The inherent non-linearity of this converter is clearly seen by
the 2’th and 3’th harmonics components. To verify the resolution, we may set the signal
band to 0-400Hz and calculate the SQNR in this region. From Eq. 3.16, the ideal resolution
should then be 13.6bit. The calculated SQNR from the simulation matches almost exact
with 13.8bit. A higher resolution than the theoretical model predicts, is possible due to
pattern noise effects. From the figure we also notice some high frequency pattern noise. In
Appendix B the sampled-clock, D flip-flop FDSM simulator is listed.
0
−20
Normalized PSD (dB)
−40
−60
−80
−100
−120
−140
1
10
2
10
3
10
Frequency (Hz)
4
10
5
10
Figure 3.19: Simulated output psd of a D flip-flop sampled-clock FDSM with a single sinusoidally
modulated input signal at 233Hz. fclk =12636220Hz, fc =710kHz, ∆f =7100Hz
53
3.2.3
Resolution comparison for SS vs SC
In general, the first-order FDSM can be implemented in two ways; as a sampled-signal
converter, and as a sampled-clock converter. The sampled-signal converter is inherently
linear, and provides a constant output data-rate. On the other side, the sampled-clock
converter employs a 1/(k + x) transfer function and provides a time-varying output datarate, where the maximum variation in time is proportional to ∆f /fc. In both converters the
quantization error is first-order noise-shaped providing a decrease in in-band noise power of
≈9dB for each doubling of the sampling frequency.
In the sampled-signal converter the dynamic range is however inversely proportional to
the sampling frequency fclk and therefore, the overall increase in SQNR is only ≈3dB for a
doubling of fclk . This is not the case for the signal bandwidth fmax , and by reducing fmax
by a factor of two, the net SQNR will now increase by ≈9dB.
In the sampled-clock converter the dynamic range is inversely proportional to the square
of the sampling frequency fc . This makes the sampled clock converter behave in a somewhat
strange manner because now the net SQNR will increase by ≈3dB for each halving of the
sampling frequency. In other words, if the FM signal can be mixed down to a lower frequency
before it is fed to the FDSM, the SQNR will be increased. A main advantage of the sampledclock converter is that the net SQNR is proportional to the constant clock frequency fclk . For
both converters, the net SQNR is proportional to the deviation of the sampling frequency.
By re-arranging Eq. 2.18 and Eq. 3.16, the resolution of both converters can be compared
SQNRss
SQNRsc
∆f
= k + 20 log
+ 10 log(fclk )
f 1.5
max fclk
∆f
)
= k + 20 log
+ 10 log(fclk ) + 10 log(
1.5
fmax
fc
(3.26)
(3.27)
SQNRss is the resolution of the sampled-signal FDSM, and SQNRsc the resolution of the
sampled-clock FDSM. The constant k is 20 log(3/(2π)). From the last equations we notice
that the only difference between the two, are the term given by fclk /fc . We therefore
have that, if fc > fclk , the sampled-signal FDSM will provide a higher resolution than
the sampled-clock FDSM. If fclk > fc , the sampled-clock FDSM will provide the highest
resolution. In other words, to achieve the highest SQNR, we should use the lowest frequency
as the sampling frequency.
1.5
Another interesting observation is that the resolution is proportional to the term ∆f /fclk
.
This term is quite similar to the deviation ratio introduced in Section 3.1.2. The difference
is that here, the maximum in-band frequency fclk is raised to the power of 1.5. Since the
deviation ratio is a measure of the maximum phase deviation of the FM signal for the highest
in-band modulation frequency fmax , we notice that the resolution of the FDSM is strongly
dependent on the phase deviation of the signal. For sinusoidal modulation we should replace
fclk with the frequency fm of the sinusoid. Now the resolution is proportional to the term
1.5
∆f /fm
which is a modification of the FM modulation index. It can also be shown that
L+0.5
the resolution of a L’th order FDSM is proportional to the factor ∆f /fm
. From this,
it may be tempting to define an order of the modulation index for the FDSM application.
L+0.5
The L’th order modulation index will then be defined by ∆f /fm
.
Both the sampled-signal and the sampled-clock FDSM may be implemented as a singlebit D flop-flop FDSM. The D flop-flop FDSM counts both edges in the incoming signal and
will therefore provide ≈6dB higher resolution than a single-edge converter. If the D flop-flop
FDSM operates in FM undersampling mode we must avoid certain fc /fclk ratios.
54
In Fig. 3.20 the resolution of both the sampled-signal and the sampled-clock modulo2n FDSM is plotted against the constant clock frequency for an example with fc =80MHz,
∆f =2MHz and a signal bandwidth of 0-5KHz.
120
110
SQNR (dB)
100
90
SS D
SS m
80
lop
flip-f
lo-n
odu
70
p
-flo
60
SC
D
SC
flip
n
lo-
du
mo
50
1
10
100
Constant clock frequency (MHz)
1000
Figure 3.20: Theoretical resolution of sampled-signal and sampled-clock FDSM plotted against
constant clock frequency for an example with fc =80MHz, ∆f =2MHz and a signal bandwidth of 05KHz. The resolution of the D flip-flop FDSM’s are ≈6dB higher than the corresponding modulo-2n
FDSM’s as both signal edges are counted
The resolution of the corresponding D flop-flop converters are also shown. As we see,
the resolution of the sampled-clock FDSM increases with ≈6dB for each doubling of fclk
while for the sampled-signal FDSM the increase is only ≈3dB. Above the point fclk = fc the
resolution of the sampled-clock FDSM is higher than for the sampled-signal converter. For
these ∆f and fc values it may however be difficult to use the D flop-flop converters close to
their squeezing limits as the usable intervals are quite narrow.
3.3
Synchrounization
For many applications, the use of a sampled-clock FDSM will introduce a problem due
to the time-varying data rate. There are however techniques to resample data streams
with non-integer rate factors [19, 30], and in this way synchronize the output data sequence
with the system clock. Resampling can be carried out both on the Nyquist rate signal and
also on the high speed bit-stream. Resampling of the sampled-clock FDSM have not been
fully investigated yet, but there is reason to believe that the most simple approach is to
synchronize the bit-stream with a slightly higher frequency signal derived from the main
system clock. Generally the bit-stream can not be resampled by the clock signal due to alias
effects, but for some frequency combinations this can be done without additional filtering.
55
0
0
-20
-20
-40
-40
Normalized PSD (dB)
Normalized PSD (dB)
In Fig. 3.21 right, a sampled-clock FDSM simulation was carried out where the output bitstream was sampled by the same clock frequency that was fed to the D flip-flop input. By
doing so, a very interesting result was observed. By sampling the time varying bit-stream
with the system clock it will be introduced harmonic distortion to the demodulated signal.
This distortion was found to be the inverse of the inherent 1/(k − x) transfer function of the
sampled-clock system. As we see from the psd spectrum compared to the standard sampledclock psd in Fig. 3.21 left, the harmonic distortion is significantly reduced as the two effects
cancels each other. (Care was taken to make sure that the synchronized circuit did not equal
a sampled-signal system). From the simulation, the S/(N+D) was found to be 60dB in the
synchronized circuit and 50.2dB in the original circuit. Compared to the theoretical value
of 58dB, the synchronized circuit worked well. For this successful experiment the following
values was used: fclk =10.15MHz, fc =530kHz, ∆f =917Hz, fm =120Hz. However, for other
carrier frequencies the performance degraded significantly, and it was never found possible
to achieve proper operation for high FM deviations. The simulator is listed in Appendix B.
As already stated only preliminary work have been carried out on synchronizing the
sampled-clock FDSM, but these ad-hoc experiments indicate that it may be possible both
to cancel the inherent non-linearity, and synchronize the sampled-clock FDSM in the same
operation.
-60
-80
-100
-60
-80
-100
-120
-120
100
1000
100
Frequency (Hz)
1000
Frequency (Hz)
Figure 3.21: Simulated psd. Left: sampled-clock FDSM. Right: Synchronized sampled-clock FDSM.
fclk =10.15MHz, fc =530kHz, ∆f =917Hz, fm =120Hz. Synchronizer frequency = fclk
56
3.4
Triangularly weighted zero-cross detection
The FDSM concept combines traditional ∆-Σ theory with FM theory to obtain high
resolution frequency-to-digital converters. As a new concept combining two different fields,
the understanding of the FDSM operation can be viewed in different ways. In this section
we will look at the oversampled D flip-flop FDSM from a traditional ZC counting frequency
discriminator point of view. By doing so, we will find a simple relationship between these
two converters modeled by a difference in an inherent data window.
The traditional ZC frequency discriminator
The traditional ZC frequency discriminator operates by counting the number of zerocrossings in the FM signal during a fixed time window T0 . The number of zero-crossings is
then dumped to the output as a digital word while the counter is reset. Usually the frequency
of the time or data window 1/T0 is chosen slightly higher than the Nyquist frequency of the
modulating signal. The digital resolution of these kind of converters are normally very low
and are heavily dependent on the modulating signal bandwidth. As an example, consider
the following case; fc = 425KHz, ∆f = 550Hz, fmax =500Hz. The output signal range
(digital resolution) for fm close to 0Hz and 1/T0 set to four times the Nyquist frequency
will now be
outmax − outmin =
2(425KHz + 550Hz) 2(425KHz − 550Hz)
−
= 0.55
4000Hz
4000Hz
(3.28)
or less than 1bit. To increase the resolution, the sampling frequency could be reduced to
the Nyquist frequency but this may cause problems due to aliasing of out-of band noise.
The oversampled D flip-flop FDSM
In most applications, the D flip-flop FDSM must be followed by a standard ∆-Σ decimator as illustrated in Fig. 3.22. Normally a multi-rate architecture is chosen to reduce the
physical complexity of the decimator. For first-order modulation, a sinc2 based decimator
is found to be a proper choise [23] for the high-frequency stage.
fclk
FM
fclk
clk
clk
DQ
DQ
FDSMout
1
m
fd
m
m
m
REG
REG
xn
REG
REG
m
yn
Figure 3.22: A D flip-flop FDSM followed by a modulo-m sinc2 decimator stage
57
The output of the FDSM will, in FM oversampling mode, be HIGH when a FM edge
is detected and LOW elsewhere as illustrated in Fig. 3.23. The input to the high-speed
decimator stage xn will now be a synchronous representation of the FM edge positions.
FM
FDSM out
Figure 3.23: FDSM output for FM oversampling mode
From [23] the output of a sinc2 decimator stage is given by
yn =
D D
xD(n−2)+k+l
(3.29)
k=1 l=1
where D is the decimation ratio. As an example, for D=4 the output at n=1 will be
y1 = 1x−2 + 2x−1 + 3x0 + 4x1 + 3x2 + 2x3 + 1x4
(3.30)
In other words, the decimator output is a triangularly weighted sum of the input sequence.
If the decimator output frequency fd is chosen four times the Nyquist frequency, the width
of the triangular window will be two times 1/fd or 1/(2fN ).
To see the relationship between the traditional frequency-discriminator and the FDSM,
we notice that counting zero-crossings during a fixed time window 1/(4fN ) is mathematically
equivalent to dividing the time window into small non-overlapping sub-intervals, then count
the number of zero-crossings in each sub-interval, mutiply each number by one, and finally
add the result together to form the overall sum. The overall sum will now equal the total
number of zero-crossings during the original interval 1/(4fN ). This operation is illustrated
in the upper part of Fig. 3.24.
weigth
FM
weigth
1/fd
1/fclk
Figure 3.24: Upper part: Uniformly windowed zero-cross-counting. Lower part: Bartlett windowed
zero-cross counting
Since the number of zero-crossings in all sub-intervals is multiplied with one, there is
an inherent uniform time window involved in the operation. In the traditional frequencydiscriminator this is seen by the fact that the position of each zero-crossings in the original
58
time window 1/(4fN ) does not affect the converter output. The only thing that matters is
the total number of zero-crossings inside the main time window.
The operation of the FDSM together with the sinc2 decimator can now be decsribed
as follows; the FDSM divides the original time window 1/(fd ) into fclk /fd number of nonoverlapping sub-windows of length 1/fclk . Then the number of zero-crossings during each
sub-intervals are counted. Since the FM signal is oversampled, the number of zero-counts in
each sub-interval will be restricted to zero and one. The decimator input xn will now represent the number of zero-crossings during each sub-interval. Due to the triangularly weighted
windowing function of the decimator, the decimator output will now be the weighted sum of
each number of zero-crossing in each sub-interval as illustrated in the lower part of Fig. 3.24.
Due to the triangular or Bartlett data window, not only the number of zero-crossings during
1/(fd ) is measured, but also the position of each zero-cross inside the main time-interval
will now be of significance in calculating the output data sequence. In this way we are also
suppressing the significance of zero-crossings close to the edges of each time interval since the
FM period represented by these crossings contains a large phase error due to cutoff effects.
What we have seen now is that by exchanging the inherent uniform data window in the
traditional zero-cross frequency discriminator with a Bartlett window, ∆-Σ noise-shaping
results. Unfortunately there are no indications that the noise-shaping order will be further
increased by using a more sophisticated window.
59
3.5
The single-bit pointer FDSM
In Section 2.5 the pointer-FDSM was introduced. This FDSM variant includes the frequency modulator as a modulated ring-oscillator. The applications for this kind of converter
is analog-to-digital conversion where the analog input signal can be any kind of physical or
electrical signal modulating the inverter delays. The pointer-FDSM is therefore suitable
for integrated sensor applications as it will immediately convey the measured signal to the
digital domain. To obtain the highest resolution for a given ring-oscillator the sampling
clock frequency should be set as high as possible. Since the converter operates by sampling
the state of the ring-oscillator, there will be a certain clock frequency, for which the use of a
higher frequency, the change in state will be restricted to zero or one. This clock frequency
will be given by
fsb = 1/(τ0 − ∆τ )
(3.31)
where ∆τ is the maximum delay deviation from the nominal inverter delay. For fclk > fsb ,
by using the implementation shown in Fig. 2.16, the FDSM output will be a bit-stream. If
the number of inverters in the oscillator is high and/or a very high sampling frequency is
used, the implementation shown in Fig. 2.16 based on a binary encoder and a non-binary
differentiator, is rather complex and may be the limiting speed factor. For high speed
operation where fclk > fsb , the converter used in Fig. 2.16 may be replaced by a simpler
converter detecting whether a change of state during 1/fclk has occurred or not.
01 0 0
1
1
0 state n 0
01 0 1
1
1
0 state n+1 0
Figure 3.25: The difference between two adjacent states of a length k ring-oscillator
In Fig. 3.25 the values of the top nodes in a k-bit ring-oscillator is shown for two adjacent
states. As the number of inverters is odd there will be a specific location in the ring where
two adjacent nodes have the same value, elsewhere all nodes are stable at 0-1-0-1... The
difference between two adjacent states will be given by the value of the two equal nodes.
Therefore, by finding the number of logical “1”s in a k-inverter ring-oscillator, this number
will oscillate between (k − 1)/2 and (k − 1)/2 + 1. The new simplified FDSM may now be
implemented by a circuit, first sampling the logical node values, then adding all nodes values
together, and finally differentiating the sum to detect whether a new state has arrived or
not. As the adder output is restricted to (k − 1)/2 and (k − 1)/2 + 1, there are no need
for carry calculation and the adder may be implemented simply as a k-input XOR gate as
illustrated in Fig. 3.26. For applications where k is large and a high sampling frequency is
used, the XOR gate may be splitted into a pipelined, two-input XOR tree to increase speed.
As in the original pointer FDSM there are no problems due to race conditions or glitches
in the oscillator readout circuit as the difference between two adjacent states is the value
of a single bit. By using a pipelined XOR tree, and a multistage decimator, the maximum
sampling speed will be limited by metastability failure in the sampling D-flip-flops [21, 22].
For a modern high speed digital process, where the sampling D flip-flops are implemented
as high speed sampled comparators, the maximum sampling speed may be at several GHz.
Another factor that must be considered when such a high sampling frequency is used is
phase-noise on the system clock (see Section 4.1).
60
k
D Q
yn
clk
clk
Q
D
clk
Q
D
clk
Q
D
clk
x(t)
x(t)
x(t)
Figure 3.26: The single-bit pointer FDSM
From Section 2.5 we saw that for a given inverter delay, the number of inverter used do
not affect the SQNR. However, in [24] an interesting result is documented where it is found
that in a MOS transistor, flicker noise is reset when the current through the transistor is
turned off. In a CMOS inverter-based ring-oscillator, the MOS transistors are most of the
time switched off, causing the flicker noise to loose its correlation with itself from each time
the transistor is active to next time it is active. In this way flicker noise will loose its 1/f
spectral density shape and be significantly reduced for low frequencies. This result explains
why there was not found any noise floor down to 7.5Hz in the pointer FDSM measurement
carried out in [7]. Due to this effect the pointer FDSM will be an interesting device used
in low-noise sensor applications. When it comes to transistor thermal noise it is reason
to believe that increasing the number of inverters will decrease the overall output noise as
the thermal noise is not correlated from transistor to transistor. By doubling the
√ number of
inverters, the overall thermal noise rms value should therefore be decreased by 2. However,
this result is not yet documented. On the other hand, increasing the number of inverters
will not increase the power consumption in the ring-oscillator itself, but there will be more
power burnt in the read-out circuit and in the XOR gate.
Finally it should be mentioned that, as in the ordinary D flip-flop FDSM, the single-bit
pointer FDSM may also be used in FM undersampling mode by restricting the sampling
frequency to an interval where the change in state is limited to m and m + 1 where m is
an integer. Fig. 3.27 shows the ouput psd of a simulation of a 7-inverter FDSM based on
the architecture shown in Fig. 3.26. The nominal inverter delay was set to 180ps. The
delay was then sinusoidally modulated to ±7%, and a 1GHz clock frequency was used. For
this frequency, the number of state changes from sample to sample will be limited to 5 and
6. The SQNR was found to be 129dB for the audio band 0-20kHz. From Eq. 2.28 the
theoretical value for a 7-inverter pointer FDSM is 121dB. The difference is assumed to be
due to pattern noise effects, see Section 4.2.
61
Normalized PSD (dB)
0
-50
-100
-150
3
10
4
5
10
10
6
10
Frequency (Hz)
Figure 3.27: The simulated output psd of a 7-inverter, single-bit pointer FDSM. fclk =1GHz,
τ0 =180ps, ∆τ =13pS, fmax =20kHz
62
3.6
Paralell conversion
In ∆-Σ modulators, there are several ways to increase the SQNR. In traditional switchedcapacitor modulators the use of very high sampling frequencies are troublesome due to slewrate and finite bandwidth limitations. One way to go is to increase the modulator order, but
now the conversion challenge is shifted back towards the analog domain again and problems
due to stability and/or matching will arise. A currently popular research field is therefore
multi-bit modulators where the oversampling ratio and the modulator order may be kept
low, although a high resolution may be achieved due to the reduced quantization error rms
value. Compared to a single-bit modulator of the same order, a multi-bit modulator will also
reduce the pattern noise and for orders higher than two, increase stability. In traditionally
∆-Σ modulators where the signal amplitude is represented by a voltage, multi-bit modulators
are struggling with non-linearity problems in the corresponding multi-bit feedback DACs.
These problems may however be overcomed or reduced by a number of more or less complex
correction techniques [11, 12, 13, 14, 15].
In FDSM converters, the situation is quite different. Here, there are no feedback DAC and
thus no need for DAC non-linearity reduction techniques. Another factor is that quantization
in the FDSM is not done in voltage or current [16], but rather in time by quantizing the FM
phase. As an example, we may consider the pointer FDSM where the use of several phase
shifted versions of the FM signal increases the θn estimation accuracy. Since quantization is
done in time, the FDSM concept is suitable for parallelisation where the output from several
identical modulator structures are added together to produce a multi-bit ∆-Σ modulator.
In this way the overall resolution is increased without increasing the oversampling ratio, FM
deviation or the modulator order. To illustrate this point we will start by showing that the
single-bit pointer FDSM can be viewed as a ring-oscillator connected to a group of parallel
D flip-flop FDSM’s.
3.6.1
Parallelisation
The output signal from the single-bit modulator in Fig. 3.26 can be modelled as
yn = (Q1n ⊕ Q2n ... ⊕ Qkn ) ⊕ (Q1n−1 ⊕ Q2n−1 ... ⊕ Qkn−1 )
(3.32)
where Q1n ...Qkn are the digital outputs of D flip-flop no. 1...k at time n/fclk . However,
the XOR operator is distributive [25], and the equation can equally be written as
yn = (Q1n ⊕ Q1n−1 ) ⊕ (Q2n ⊕ Q2n−1 )... ⊕ (Qkn ⊕ Qkn−1 )
(3.33)
This equation describes a parallel modulator scheme as the content of each parenthesis is
equivalent to the output of a separate D flip-flop FDSM. Each D flop-flop FDSM output
is then added together in a k input XOR gate to form the final output. As each D flipflop FDSM operates on a phase shifted version of the overall FM signal, the resolution is
improved. This result is to some extent intuitive as the output from a ∆-Σ modulator
can be viewed as a low frequency in-band signal plus quantization noise. By adding several
slightly, continuos-time shifted versions of the signal together, the underlying signal will be
strongly correlated while the quantization noise is to some degree negative correlated. Due
to the negative correlation, the SQNR is increased by ≈6dB for each doubling of the number
63
of channels compared to ≈3dB that would have been the result if the quantization error in
each channel had been totally uncorrelated.
It is quite easy to mathematically describe the operation of the single-bit pointer FDSM
if the phase shifts are equally distributed in the [0, 2π interval. In this case the underlying
FM signal at node l can be modeled as
t
f m(t)l = sin 2πfc t + 2πk
(3.34)
x(τ )dτ + ϕl
0
where ϕl = 2πl/6 + ((−1)l − 1)π is the phase difference given by the tap number l. In
Fig. 3.28 the hard-limited continuous-time FM node values in a 3-inverter ring-oscillator are
illustrated.
2π
FM1
2π/3
FM2
FM3
FMs
FDSM out
Figure 3.28: Timing diagram of a 3-inverter, single-bit, pointer FDSM. Top signal FM1 to FM3 ,
oscillator node values. Signal FMs - equivalent FM signal for single-channel conversion
The output of the single-bit pointer FDSM will now be logical HIGH when the state of
the ring-oscillator has changed, elsewhere the output is LOW. A change of state has taken
place when there have been a logical change in one of the three nodes. The bottom signal
in the figure illustrates the FDSM output. By looking closer at the timing of the different
signals we notice that the FDSM output is identical to the output of a standard single
channel D flip-flop FDSM where the input FM signal is given by the signal FMs in the
figure. The signal FMs is actually the continuous-time XOR sum of the three node values,
and the signal itself is an ordinary limited FM signal with three times the frequency of the
FM signal in one of the ring-oscillator nodes. This result make the analysis of pattern noise
in the pointer FDSM much easier as the pattern noise will be identical to that in a ordinary
single-channel D flop-flop FDSM (see Section 4.2) but where the input carrier and deviation
are multiplied by k.
Multi-bit conversion
The parallel pointer FDSM described by Eq. 3.33 consists of k ordinary ∆-Σ bit-streams
added together in a XOR gate. As each signal by itself is a true ∆-Σ bit-stream they can
also be added together in a standard digital adder. By doing so, the FDSM output will be
a word-stream if the output dynamic range exceeds 1. In Fig. 3.29 the parallel multi-bit
modulator is illustrated.
If the dynamic range of the bit-stream in each channel is close to 1, the FDSM output
dynamic range will be close to k, yelding a log2 k-bit output signal. For equal inverter delays
64
clk
x(t)
clk
clk
D Q
D Q
1
clk
clk
1
D Q
D Q
x(t)
n
yn
k
1
x(t)
clk
clk
D Q
D Q
Figure 3.29: A multi-bit pointer-FDSM based on a k-inverter ring-oscillator and k parallel D
flip-flop FDSM’s
it can be shown that the FDSM output signal is equivalent to that of a single modulo-2n
FDSM, but where the input FM carrier frequency and deviation is multiplied by k.
3.6.2
Open-ended delay-line parallelisation
In frequency-to-digital conversion applications where the input to the converter is an externally generated FM signal, there will normally not be available any phase shifted FM
information. In this case the simplest way to achieve additional phase information is to
feed the FM signal through an open ended delay line with constant delays as illustrated in
Fig. 3.30.
FM
clk
clk
clk
D Q
D Q
1
clk
clk
1
D Q
D Q
n
yn
k
1
clk
clk
D Q
D Q
Figure 3.30: A multi-bit pointer-FDSM based on a k-inverter delay-line and k parallel D flip-flop
FDSM’s
By doing so, we can no longer expect the phase shifts to be uniformly distributed over
the [0, π interval, as will be the case in a symmetrical ring-oscillator where all inverter
65
delays are equally modulated. In principle, it is possible to adjust the FM carrier frequency
to match the inverter delays to make the phase shifts uniformly distributed over the [0, π
interval, but when the FM signal is modulated to a higher or lower frequency, the symmetry
will be disturbed. However, for modulating signals of very small amplitudes the phase
distribution may, in principle be almost equal to that in a closed ring-oscillator for a properly
chosen carrier to delay ratio. On the other hand, by making the delay line ring-connected,
modulated by the FM signal, and included in a phase locked loop, it may be possible to
distribute the phase shifts almost uniformly even for high FM deviations, but this possibility
have not been investigated yet.
To analyze the effect of non-uniformly distributed phase shifts, we may start by looking
at the FDSM output for a situation where the total delay through the line is less than half
a FM period. This situation is illustrated in Fig. 3.31.
π
FM0
FM1
FM2
ϕ
ϕ
ϕ
ϕ
FDSM out
Figure 3.31: Timing diagram of a two-inverter delay-line FDSM with two non-uniform phase shifts.
In this example a delay-line with three tappings are used where the phase shift of each
inverter is ϕ. The FDSM output will now consist of periods of pulse-trains corresponding to
the zero-crossings in each channel. To find the degradation in SQNR caused by non-uniform
phase delays, we may start by noticing that by adding k phase-shifted bit-streams together,
the output signal power will be k times the signal power in each bit-stream if the phase shifts
are small compared to the frequency of the modulating signal. This is because the amplitude
of the underlying signal is almost equal in each bit-stream causing the signal correlation to
be close to 1. The correlation of the quantization error in each bit-stream will, on the other
hand be far from 1, and the output quantization noise power can be found by expressing the
total quantization error as the sum of the quantization error in each bit-stream as follows
etot
n =
k−1
l=0
eln =
k−1
modπ (θn − ϕl )
(3.35)
l=0
In this expression eln is the quantization error in bit-stream number l at sample number n.
This is illustrated in Fig. 3.32 for a delay-line with three tappings sampled twise.
To find the total quantization noise power at the FDSM output we may start by looking
closer at the sum given by Eq. 3.35. First, we notice that the total quantization error is
dependent on the position of the sampling edge relative to the FM period. From Fig. 3.32
we see that by shifting the position of the sampling edge to the right, the total quantization
error will increase until the error in one of the channels has reached its maximum of 1
corresponding to a phase difference of π. When this situation occurs, the estimated FM angle
in that channel increases with 1 (one ZC count) and the quantization error in that channel
is reset to zero. When the sampling edge is further shifted to the right, the quantization
66
sample
π
e'0
FM0
e0
FM1
FM2
sample'
e1 e'1
e'2
ϕ
ϕ
e2
Figure 3.32: The quantization errors in a three tapping delay line FDSM for two different samples
4
4
3.5
3.5
3
3
Total quantization error
Total quantization error
error in each channel will increase again until the error in one of the other channels reaches
its maximum and the process is repeated.
In Fig. 3.33 the total quantization error in a three-inverter delay-line FDSM is shown as
the sampling edge is varied over an interval of 5/4 times the FM period.
2.5
2
1.5
1
2
1.5
1
0.5
0.5
0
2.5
0
π
2π
Sampling edge position relative to FM phase
π
2π
Sampling edge position relative to FM phase
Figure 3.33: Total quantization error in a 3-inverter delay-line FDSM versus position of sampling
edge. Equal delays for each inverter. Left picture: Blue line - no inverter delay. Red line - phase
shift for last tapping 0.4π: Black line - uniformly distributed phase shifts in the [0, π interval. Right
picture: Blue line - phase shift for last tapping 2π. Red line - phase shift for last tapping 2.4π. Black
line - phase shift for last tapping 3π
In the left picture, the blue graph illustrates the total error for the case where the inverter
delays are zero. In other words, the FM signals at each tappings are equal. In this case,
the total quantization error will be four times the error in each channel. As we see from
the graph the total quantization error varies between 0 and 4 as the sampling edge position
is shifted. In this case both the signal power and the quantization noise power will be
increased by 4 times compared to that in a single D flip-flop FDSM. In other words, the
signal to quantization noise ratio will be the same. This should not be surprising, as there
are no additional information added to the system by copying the FM signal into 4 equal
versions.
The quantization noise power can, to a first degree of accuracy, be calculated by assuming
equal possibility for the sampling edge to occur anywhere in the FM period. From this
67
20
20
18
18
16
16
Total quantization error
Total quantization error
assumption the quantization probability density
function (pdf) will be uniform over the
√
[0, 4 interval, and the rms value will be 4/ 12.
In the same picture, the red graph illustrates the total quantization error for a situation
where the total phase difference between the input and the output of the line is 0.4π. In this
case the total quantization error will be limited to the interval [0.6, 3.4]. The pdf for this
case will be divided into three different intervals each with a uniform distribution, but by
visual inspection we can expect the noise rms value to be lower than for the zero delay case.
Finally, the black graph illustrates the optimal case where the phase delays are symmetrically
distributed over the [0, π interval. In this case the total quantization error is limited to√the
interval [1.5, 2.5] and the pdf is uniform. The output noise rms value will now be 1/ 12,
and the SQNR will now be 4 times higher than for the single D flip-flop FDSM.
In Fig. 3.33 right, the total error is calculated for the case where the total delay through
the line is greater than half the FM period. For the blue graph the delay from the input of
the line to the last tapping is one FM period. In this case the error is increased to the [1, 3]
interval as the ZC distribution symmetry is disturbed. By increasing the line delay further
to 2.4π, the error interval is somewhat decreased as illustrated by the red graph. Finally,
for a total line delay of 3π the phase delays are again symmetrical, and the total error is
restricted to the [1.5, 2.5] interval.
14
12
10
8
6
14
12
10
8
6
4
4
2
2
0
0
π
2π
Sampling edge position relative to FM phase
π
2π
Sampling edge position relative to FM phase
Figure 3.34: Total quantization error in a 90-inverter delay-line FDSM versus position of sampling
edge. Equal delays for each inverter. Left picture: Blue line - no inverter delay. Red line - phase
shift for last tapping 0.4π: Black line - uniformly distributed phase shifts in the [0, π interval. Right
picture: Blue line - phase shift for last tapping 2π. Red line - phase shift for last tapping 2.4π. Black
line - phase shift for last tapping 3π
In Fig. 3.34 the same procedure is repeated for a 90-inverter delay line. Compared to
the 3-inverter case we notice that the error rms value is significantly reduced even for cases
where the total line delay is more than halve the FM period. As the number of inverters is
increased, the overall phase distribution will be more complex and seems to be more evenly
distributed causing a lower noise rms value.
For a delay line with a high number of inverters the relationship between the overall
quantization noise power and the total line delay will be quite complex. To get a impression
of this relationship the noise power for different delays are simulated in Matlab [26] and
illustrated in Fig. 3.35.
In the left figure, the quantization noise power is calculated as a function of the overal
line delay for a line of 30 inverters. The noise power is normalized to make zero correspond
68
Normalized total quantization noise power (dB)
Normalized total quantization noise power (dB)
0
-5
-10
-15
-20
-25
-30
π
2π
3π
4π 5π
6π
Delay of last tapping (rad)
7π
8π
0
-5
-10
-15
-20
-25
-30
-35
-40
π
2π
3π
4π 5π
6π
Delay of last tapping (rad)
7π
8π
Figure 3.35: Total quantization noise power as a function of line delay. Left picture - 30-inverter
delay-line. Right picture -90-inverter delay-line
to the noise power in a single D flip-flop FDSM. As the inverter delays are increased from
zero the noise power is decreased following a sinc like function with the lower extremes at
multiple locations of π. The bottom line illustrates the theoretical noise level at -20log(30)
corresponding to a perfect symmetrical distribution of the phase delays in the interval [0, π.
We notice that the first minimum at π is located in a very narrow range, and just a slight
delay deviation from this point will increase the noise power significantly. In theory, it would
be possible to choose the necessary delay / FM carrier ratio to utilize this point and obtain
a high resolution for small signal modulation. However, for large modulating signals the
overal noise power will increase significantly as the phase delay distribution will be heavily
varyed around the π point in the figure. Particularly, when the modulating signal is at
its lower extrema, the FM signal frequency will be low, causing the maximum phase delay
to be less than π which is the region where the noise power increases most rapidly. In a
practical implementation, it will also be quite difficult to utilize this point as just a slight
process deviation in the transistor parameter β [27] or a drift in the FM carrier frequency
will move the operation point out of range. However, if it is possible to dynamically adjust
the FM carrier frequency to make the phase distribution uniform, this point may be utilized
to increase the resolution for low amplitude signals. A probably better range to locate the
modulator in will be at, for example 4π where the valley is wider allowing more drift in the
FM carrier frequency and relaxed delay accuracy.
For higher line delays the sinc like function is dominated by periodic noise peaks with
triangular shapes. If the operation point is to be located in these regions, one must ensure
that there are enough room for drift and process deviations to avoid the main peaks in the
picture. In Fig. 3.35 right, the same noise power is calculated for a 90-inverter delay line.
The depth of the first valley is now increased as the power of an ideal phase distribution is
-20log(90), illustrated by the horizontal line at the bottom of the figure. Also in this case,
the noise power follows a sinc like function, and even if the number of inverters is increased,
the magnitude of this function is the same as for the 30-inverter line. However, the periodic
noise peaks at higher line delays are significantly reduced. This makes it easier to locate the
operation point in these regions.
In a practical implementation it is hard to make the inverter delays perfectly equal due
to β mismatch effects. The delay matching can for CMOS implementations be significantly
improved by increasing the gate area of each transistor [28]. On the other hand, for a
69
Normalized total quantization noise power (dB)
Normalized total quantization noise power (dB)
0
-5
-10
-15
-20
-25
-30
π
2π
3π
4π 5π
6π
Delay of last tapping (rad)
7π
8π
0
-5
-10
-15
-20
-25
-30
π
2π
3π
4π 5π
6π
Delay of last tapping (rad)
7π
8π
Figure 3.36: Total quantization noise power as a function of line delay. 10% random delay deviation
added to each inverter. Left picture - 30-inverter delay-line. Right picture - 90-inverter delay-line
delay line consisting of a large number of inverters where the total delay is longer than the
FM period, we have seen that the sum of all quantization errors follows a quite complex
pattern. Small delay deviations along the line due to mismatch effects will now increase the
complexity further, and there may be a point where complexity is so high that the total
quantization error is almost independed of small deviations from the operation point. So,
instead of trying to minimize delay mismatch, it can be interesting to increase the mismatch,
and in this way make the overall noise power less sensitive to drift of the operation point.
This will also decrease the noise power for modulating signals of high amplitude. In Fig. 3.36
the noise power is calculated for the same lines as in Fig. 3.35 but now there are added a 10%
relative mismatch to the inverter delays. From the figure we notice that the main sinc shape
is still present but the periodic noise peaks at higher line delays are significantly reduced.
As we expected, the noise function is much more convergent for higher line delays, and there
are more improvement seen in the SQNR when the number of inverters is increased.
The noise power in Fig. 3.35 and Fig. 3.36 are calculated for different constant FM
period to delay distributions. The situation for a sinusoidally modulated FM signal with
high deviation will be quite more complex as the phase distribution will vary with the
deviation of the FM signal. At the point where the FM signal frequency is at its maximum
and minimum, the noise power can be described by Fig. 3.35 and Fig. 3.36, but since the FM
frequency, and thus the phase distribution is constantly varying the picture will be much
more complex. A more accurate way to find the SQNR in this case is by a simulation of the
complete modulator.
In Fig. 3.37-left, a delay-line FDSM is simulated for different line length and inverter
delays, and the SQNR is calculated. As the number of inverters is increased, the inverter
delay is decreased to make the phase distribution uniform over the [0, π interval. This
locates the operating point to the first and deepest valley in Fig. 3.35 and Fig. 3.36 for
all simulations. The first point to the left in the figure for each curve, is the SQNR for
a single D flop-flop FDSM. The next point corresponds to a simulation with 3 inverters
where the inverter delay is 4.17ns. The last point to the right for each curve corresponds
to a 128-inverter line where the inverter delay is 130ps. The FM carrier frequency was set
to 30MHz and a sinusoidal modulating signal at 3MHz deviation was applied. By using
such a high deviation the phase distribution is heavily disturbed by the modulating signal.
The sampling frequency was 200MHz and an audio application was considered with a signal
70
130
140
125
rin
115
al
ide
110
no mismatch
10% mismatch
105
78ns
130
SQNR (dB)
SQNR (dB)
120
or
lat
cil
s
g-o
120
s
0n
15
110
al
ide
s
110n
100
100
90
95
80
10
1
100
Numb of taps
10
100
Numb of taps
1000
Figure 3.37: Simulated SQNR versus number of inverters in a delay-line FDSM. fc =30MHz,
∆f =3MHz, fclk =200MHz, signal bandwidth 20kHz. Left figure - inverter delay choosen to make
phase distribution uniform over the [0, π interval for zero modulation. Top curve: ideal SQNR for
ring-ocillator FDSM, next curve: simulated result for ring-ocillator FDSM. Bottom curves: open
delay-line FDSM with equal inverter delays and with 10% random delay mismatch. Right figure simulated SQNR for open delay-line FDSM with different inverter delays
bandwidth of 20KHz. The top curve in the figure illustrates the ideal SQNR for the case
where the phase is always perfectly distributed as it will be in a ring-oscillator based FDSM.
The next line illustrates the simulated SQNR for a practical ring-oscillator FDSM with no
delay mismatch. The SQNR is at average ≈4dB lower than the ideal curve. This is assumed
to be caused by pattern noise. The next two curves shows the SQNR for the open delay-line
FDSM both with no inverter delay mismatch and with 10% relative delay mismatch. There
are no significant differences between these two cases as the number of inverters increases,
and we may conclude that the phase distribution is already so complex in these cases that
a random delay mismatch does not affect the overall SQNR signifficantly. However, as the
number of inverters increases the difference in SQNR from the ideal curve increases as the
first valley in Fig. 3.35 and Fig. 3.36 gets narrowed. From this simulation we may therefore
conclude that if the operating point is to be located in the first valley of Fig. 3.35 and
Fig. 3.36, there is no significant increase in SQNR by increasing the number of inverters to
more than ≈80.
In Fig. 3.37-left, another situation is shown. In this case the inverter delay is kept
constant while the number of inverters in the line is increased. To make the simulation
more realistic, a 5% random delay mismatch is added to each inverter. The SQNR is found
for three different inverter delays, 150ps, 110ps and 78ps which are achievable values in a
modern CMOS process. In the left part of the figure the phase distribution is restricted
to only a fraction of the [0, π interval, and there are almost no increase in SQNR seen by
increasing the number of inverters. In the middle of the figure the phase distribution starts
to cover the [0, π interval and the SQNR increases. The SQNR for the 150ps and the 110ps
case are however far from the ideal curve even when a high number of inverters is used. From
this simulation, we can conclude that for FM signals with high deviations the SQNR may
be significantly lower than for a perfectly phase distributed ring-oscillator FDSM. However,
the SQNR is still increased by increasing the number of inverters in the line, although the
exact resolution is a complex function of different parameters.
So far we have only simulated the delay-line FDSM for FM signals with a high relative
71
deviation. Now we will verify that the delay-line FDSM can provide a much higher performance for small relative deviations by locating the operating point in one of the valleys
shown in Fig. 3.35 and Fig. 3.36. In the following example, the first valley was chosen. In
Fig. 3.38 the SQNR is found from a simulation of a 128-inverter delay-line FDSM where
the FM carrier frequency is set to 30MHz, the sampling frequency 200MHz and the signal
bandwidth set to the audio range of 0-20kHz. From Eq. 2.28 the theoretical SQNR for a
sinusoidal modulating signal causing a 3Hz FM deviation should be 5.3dB. From the simulation the SQNR was calculated to 20dB, or almost 4bit higher than the theoretical value.
The reason for this result is that the FDSM dynamic range is located in a patter noise valley,
as will be described in Section 4.2. In Appendix B, the simulator used in this example is
listed.
Nomalized power Spectral Density (dB)
-80
-100
-120
-140
-160
-180
200
1000
10 000
100 000
Frequency (Hz)
1000 000
Figure 3.38: Simulated power spectral density for a 128-inverter delay-line FDSM. fc =30MHz,
∆f =3Hz, fclk =200MHz, signal bandwidth 20kHz.
3.6.3
A 7-bit parallel audio FDSM
An experimental VLSI implementation of a delay-line FDSM have been made by the DeltaSigma Group1 at IFI, UIO. The test converter is implemented in a CMOS, single poly 0.6µm
AMS process, and are based on a delay-line of 1024 inverters. The converter is one of two
solutions targeted at a microphone interface application in an audio noise analyzer. The
other solution is based on a second-order FDSM and will not be described in this thesis.
For each solution there are scheduled several test chips to achieve more experience and
understanding of the FDSM concept. The system microphone is based on a low noise LC
oscillator and the output is a FM signal with a carrier frequency of 30MHz. The maximum
frequency deviation is 3MHz, and the goal is to achieve a dynamic range of 24bit in the
0-20kHz audio range. The first FDSM test chip consist of 1024 parallel D flip-flop FDSM’s
1 The Delta-Sigma group consists of Dag T.E. Wisland, Jan T. Marienborg, Tor S. Lande, Yngvar Berg,
Monica Finsrud and the author. The group is currently working in collaboration with the company NorSonic
in Lier, Norway, to develop high resolution digital audio noise analyzer.
72
128-inverter delay line
sinc2 decimator
as shown in Fig. 3.30, and the output bit-stream of each FDSM is summed together in a
pipelined adder treee. By using 1024 parallel modulators, the size of the chip can be quite
large, and to make the implementation more compact the system is grouped into four equal
parts consisting of 128 inverters with corresponding D flip-flop FDSM’s and a bit-stream
adder. The output from these four groups are then added together to make the final FDSM
output. The overall FDSM output is 10-bit, but for a maximum amplitude audio signal only
7-bits will be active.
adder tree
final adder
Figure 3.39: A multi-bit pointer-FDSM based on a 4·256-inverter ring-oscillator and 4·256 parallel
D flip-flop FDSM’s
In Fig. 3.39 the layout of the chip is shown. The delay line is divided in four parts and
located as a ring just inside the pads. The adder tree output for each section is at the center
of the chip, and the final adder is located on the outer side of the right delay-line section. A
30-bit wide sinc2 decimator is also included on the chip. The total chip area without pads is
7mm2 . As a test chip there have been no efforts taken to reduce area in the digital circuits
which are designed in house. The decision to locate the analog delay-line along the edge of
the circuit where substrate coupled switching noise from the pads are at its highest, have
been carefully analyzed. There have been numerous simulations indicating that switching
noise modulating the inverter delay has almost no effect on the overall signal to noise ratio
if the fundamental noise frequency is a multiple of the decimator output frequency. Even
so, the delay-line Vdd and Gnd terminals are implemented with separate routing and pads.
In the next section we will also see that phase noise in general is shaped by the FDSM.
The delay-line inverters were implemented with minimum gate lengths, and the delay
is simulated to 130ps. Under normal operation the power consumption is simulated to
73
maximum 1W. The SQNR for this circuit is high-level simulated for sinusoidal modulation at
different modulating signal amplitudes as illustrated in Fig. 3.40. For a maximum amplitude
modulating sinusoidal, the SQNR was found to be 132dB or ≈22-bit. However, as the FM
deviation is lowered the quantization noise is reduced, and the dynamic range of the converter
is found to be more than 140dB or almost 24-bit.
140
120
SQNR (dB)
100
80
60
40
20
0
-7
10
10
-6
-5
-4
-3
-2
10
10
10
10
Amplitude of modulating sinusoudal
10
-1
10
0
Figure 3.40: SQNR for the 1024-inverter delay-line FDSM for versus modulating signal amplitude.
Straight line - theoretic resolution based on the white quantiztion noise model
74
75
Chapter 4
Excess noise
4.1
Phase Noise
In many analog demodulation systems where a high signal to noise ratio is essential, phase
noise can be a serious problem. Phase noise will be present both on the analog modulated
signal, and for sampled-time systems it will, in addition, be present on the sampling clock.
This will also be the case for a practical FDSM system where the phase noise present on
the FM signal and on the clock signal is illustrated in Fig. 4.1. If a high demodulated signal
to noise ratio is to be achieved, the effect of phase noise must be carefully analyzed. In the
following, the effect of phase noise both on the FM signal and on the clock signal will be
modeled. Since the phase of a FM signal is the integral of the FM signal frequency, phase
noise can also be modeled as frequency noise by considering a 1/s relationship. It turns
out that phase noise on the clock signal is easier modeled by considering its frequency noise
equivalent, and the comparison between FM and clock noise will therefore be carried out on
their frequency noise equivalents.
To simplify the analysis, only the sampled-signal FDSM is considered. However, as the
sampled-clock FDSM is an equivalent FDSM system the analysis for this kind of modulators
will be identical by considering a change in time-base (Section 3.2.1).
fclk
+
ϕ'n
ϕn
FM
+
FDSM
yn
Figure 4.1: Phase noise on FM and clock inputs
Phase noise on the FM signal
We will begin the noise analysis be looking at phase noise on the FM signal. First, we will
recapitulate and look at the operation of a ZC counting, multi-bit FDSM which consists
of an asynchronous ZC counter followed by a synchronizing register and a differentiator as
76
illustrated in Fig. 4.2. This circuit can be viewed as an extension of the D flip-flop FDSM as
the two outputs will be identical as long as the ∆f /fclk ratio and the FM carrier frequency
is chosen to make the output limited to m and m + 1, where m is an integer. In a practical
realization, modulo arithmetic will be used both in the counter and in the differentiator
to limit the necessary word-length. However, as long as the modulo arithmetic is working
properly it will not affect the converter operation from a mathematical point of view. By
disregarding the modulo operation and considering infinite word-length, the asynchronous
ZC counter will represent the total FM phase θ(t) by the total number of received zerocrossings. In this way the FM phase is scaled and quantized since it is represented by integers
(number of halve FM periods). As an example, if the total FM phase θ(t) is (247π + 0.03),
it will be represented by the integer 247. The scaling factor is π and the quantization error
e is −0.03/π.
counter
fm
reg
fclk
θn
diff
cnt
yn = θn-θn-1
reg
Figure 4.2: A basic multi-bit FDSM
The counter output can now be considered as an estimate of the total phase given by
θ(t)
+ e(t),
−1 < e(t) ≤ 0
(4.1)
π
Notice that the counter output represents the FM phase in continuous time but in quantized
amplitude. In a FSDM the variation in kx(τ ) is small during the sampling interval 1/fclk
due to oversampling. Therefore Eq. 2.7 can be approximated by Eq. 2.8 which is repeated
here for convenience
θ̂(t) =
θn =
2π
fclk
n
(fc + kxm ).
(4.2)
m=−∞
The counter output is then synchronized with the system clock and differentiated. From
Eq. 4.1 and Eq. 4.2 the FDSM output θ̂n − θ̂n−1 will be
yn = 2
fc + kxn
+ en − en−1 ,
fclk
−1 < en ≤ 0
(4.3)
Phase noise on the FM signal can now be represented by an additive error signal ϕn on the
FM phase
fm(t) = sin[θ(t) + ϕ(t)].
(4.4)
The FDSM input is a limited FM signal, thus amplitude noise on the original FM signal
may also modulate the FM edge positions. However, this disturbance can also be modeled
as phase noise included in ϕ(t). The FDSM counter output θ̂n will now be an estimate of
the sum of the original phase θn and the phase noise ϕn given by
77
(θn + ϕn )
+ en ,
−1 < en < 0
π
this value is then differentiated and from Eq. 4.2 we get
θ̂n =
yn = 2
fc + kxn
1
+ (en − en−1 ) + (ϕn − ϕn−1 ).
fclk
π
(4.5)
(4.6)
In other words, FM signal phase noise will enter the system in the same way as the quantization error and thus be first-order noise-shaped. This is an important result as the FDSM
concept otherwise would had been unsuitable for high quality conversion.
Phase noise on the system clock
The effect of phase-noise on the sampling clock is similar to the previous case as we may
change the reference point and consider the noisy clock signal as constant with virtual phase
noise on the FM signal. However, by making a change in time-base, we need a description of
the virtual FM noise. The power of the virtual noise will not necessarily equal the power in
the original clock noise, and the systems sensitivity to clock noise may therefore be different
from its sensitivity to FM signal noise. The easiest way to compare these effects will be to
look at their equivalent frequency noise representations.
4.1.1
Equivalent frequency noise
Starting with FM signal phase noise, from Eq. 4.6 the FDSM output can be expressed as
yn = 2
(fc + kxn + fnϕ )
+ en − en−1
fclk
(4.7)
where fnϕ is a resulting frequency error given by
fnϕ = fclk (ϕn − ϕn−1 )/π
(4.8)
We notice that the frequency error is the difference of the phase error as the FM frequency
is the derivative of the FM phase. The spectral density of the frequency error will therefore
be given by a shaped and scaled version of the spectral density of the phase error.
Phase noise on the sampling clock can now be modeled as a frequency error in the clock
frequency
yn = 2
fc + kxn
(fclk + fnϕ )
+ en − en−1
(4.9)
We can now compare the FDSM sensitivity to FM signal and clock frequency errors by
considering Eq. 4.7 and Eq. 4.9 for the case where there are no modulating signal, xn = 0
and the frequency error is small compared to fclk and fc . The output sensitivity to a small
frequency error dfnϕ on the FM signal can be found from the derivative of Eq. 4.7 with
respect to fnϕ . Notice that we are looking at the derivative of yn with respect to fnϕ and not
with respect to time. So, the FDSM sensitivity to a small error in the FM frequency will be
dyn
2
=
.
dfnϕ
fclk
(4.10)
Similarly, for a small frequency error dfnϕ on the clock signal we have that the FDSM
sensitivity is given by the derivative of Eq. 4.9 with respect to fnϕ which is
78
dyn
dfnϕ
=−
2fc
(fclk + fnϕ )2
,
(4.11)
thus the output sensitivity to FM signal phase noise is
2
df ϕ ,
fclk n
and the systems sensitivity to clock signal phase noise is
dyn =
dyn = −
fc 2
df ϕ
fclk fclk n
(4.12)
(4.13)
assuming fclk fnϕ . From this analysis we can conclude that if the FM carrier frequency
is higher than the sampling frequency, the FDSM is more sensitive to frequency and thus
phase noise on the clock signal than on the FM signal. If the FM carrier frequency is lower
than the sampling frequency, the FDSM is more sensitive to phase noise on the FM signal.
In other words, the FDSM is most sensitive to phase noise on the signal with the lowest
frequency.
These results are for absolute frequency or phase errors. However, if the error specified is
relative to the corresponding signal center frequency, the situation is different. If the relative
FM and clock frequency errors are equal, we have dfnϕ /fc = dfnϕ /fclk , and in this case, |dy|
in Eq. 4.12 will equal |dy| in Eq. 4.13. In other words, the FDSM is equally sensitive to
relative frequency noise on the clock and on the FM signal.
4.1.2
Output noise power
To further illustrate the relationship between phase and quantization noise in the demodulated signal, we may simplify the analysis by consider no correlation between the quantization
error, phase errors and and the modulating signal. From Eq. 4.6, Eq. 4.12 and Eq. 4.13 we
then have the power spectral density of the sampled-signal FDSM output given by
f2
k2
Sy (f ) = 4 20 δ(0) + 4 2 Sx
f
f
clk
clk
carrier
signal
+ |(1 − e
−j2πf /fclk
)|2 Se
quantization noise
1
+ 2 |(1 − e−j2πf /fclk )|2 Sϕ
π
FM signal phase noise
f2
+ 2 c2 |(1 − e−j2πf /fclk )|2 Sϕ
π f
clk
clock signal phase noise
(4.14)
In this equation Sx is the psd of the modulating signal xn , and Se is the psd of the quantization error, assumed to be uniformly distributed in the −1, 0] interval. Sϕ is the psd of
the FM signal phase noise and Sϕ is the psd of the clock signal phase noise (in both cases
the phase error is given in radians).
79
To calculate the in-band noise power in the demodulated signal we may consider the
simplest case where both the quantization noise and the phase noise is white. Let the
variance of the quantization error be σe2 = 1/12 and the variance of the phase noises be σϕ2
and σϕ2 respectively. The resulting in-band noise can then be found by integrating Eq. 4.14
over the signal band. For the quantization error, we already know the result which from
Eq. 2.18 is
Pye = σe2
π2
3
2fmax
fclk
3
π2
=
36
2fmax
fclk
3
,
(4.15)
For FM signal phase noise we get
Ptϕ
σϕ2
=
36
fmax
fclk
3
.
(4.16)
Finally, for clock signal phase noise we get
Pyϕ =
σϕ fc 2
2
36 fclk
2
fmax
fclk
3
.
(4.17)
The output power of a sinusoidal modulating signal with maximum amplitude will be
Pyx = 4
k2
∆f 2 1
P
=
4
x
2
2 2.
fclk
fclk
(4.18)
By comparing Eq. 4.18 to Eq. 4.16 or to Eq. 4.17 the FDSM output signal to white-phase
noise ratio can be found.
4.1.3
Simulation
To verify Eq. 4.14 for FM signal noise and modulating signal power, the FDSM have been
simulated for a sinusoidal modulating signal at 67.4Hz with two harmonic FM phase noise
components added. The amplitude of the harmonic noise components was both set equal to
0.01rad, and the frequency to 2 and 0.5 times the modulating signal frequency respectively.
The frequency deviation caused by the modulating signal was 425Hz which from Eq. 4.18
should produce a signal power of Pyx = −82dB. The corresponding phase noise power for
the high frequency harmonic will from Eq. 4.14 be Pyϕ = −132dB, and for the low frequency
harmonic, Pyϕ = −145dB. By using the periodogram psd estimator (Appendix A), the
corresponding psd harmonic peaks will be Syϕ (134.6Hz) = −106.5dB, and Syϕ (33.75Hz) =
−118.6dB respectively. For the modulating signal, we have Syx (67.3)Hz) = −56.6dB. In
Fig. 4.3 the estimated psd of the simulated bit-stream is shown. By inspecting the level of
the three harmonics there is found a good match with the theory.
4.1.4
Comments on phase noise in the sampled-signal FDSM
We have shown that phase noise on both the FM signal and on the clock signal will be
first-order noise shaped and therefore suppressed for low frequencies. The theory has been
confirmed for phase noise on the FM signal by simulation. The sensitivity to absolute phase
noise measured in radians is not the same at the FM and clock inputs. At the clock input
the sensitivity is −fc /fclk times the sensitivity at the FM input. However, in some systems
the phase noise power is relative to the period of the corresponding signal. In this case,
we should keep in mind that the FDSM is equally sensitive to relative phase noise on the
80
−60
Power spectral density (dB)
−80
−100
−120
−140
−160
−180
1
10
2
10
Frequency (Hz)
3
10
Figure 4.3: Simulated FDSM output psd for two equal amplitude harmonic phase noise components.
Left peak - harmonic phase noise component, amplitude: 0.01 radians, frequency 33.75Hz. Middle
peak - frequency modulating signal itself. Right peak - harmonic phase noise component, amplitude:
0.01 radians, frequency 134Hz.
FM and on the clock input. The noise shaping effect on phase noise can be illustrated by 4
different examples
I) White phase noise
If the phase noise is white, its power will be uniformly distributed in the [0, fclk interval.
In this case a doubling of the oversampling ratio (fclk for a constant fmax ) will reduce the
in-band phase noise power by ≈9B. However, the signal range is reduced by a factor of
two reducing the signal power by ≈6dB. Therefore, by increasing fclk we will have a ≈3dB
improvement in the signal to phase noise ratio in the demodulated signal.
II) Harmonic phase noise
If harmonic phase noise is present, the frequency of the noise will determine the resulting
output noise power. Since phase noise is first-order shaped, low frequency harmonics in
the signal band are heavily suppressed. Tones outside the signal band will be removed by
the decimating filter. If a harmonic noise tone is located in the signal band, an increase in
the sampling frequency will not improve the signal to phase noise ratio in the demodulated
signal.
III) Flicker phase noise (f −1 )
The flicker phase noise floor increases by 10dB/decade as we go down in frequency. Due to
the noise shaping the resulting psd at the FDSM output will now decrease by 20dB-10dB =
10dB/decade as we go down in frequency. An increase in the sampling frequency will not
improve the signal to phase noise ratio in the demodulated signal.
81
IV) f −2 phase noise (FM noise)
Noise directly on the input signal x(t) will be present as f −2 phase noise or FM noise. In
this case the -20dB/decade slope of the phase noise will be equalized by the inverse shape of
the noise-shaping transfer function. Due to the noise-shaping, f −2 phase noise corresponds
to white noise in the modulating signal x(t).
82
4.2
Pattern noise
Although first-order ∆-Σ modulators are significantly simpler to implement in VLSI than
higher-order modulators, they are rarely used due to two problems:
1. In traditional SC ∆-Σ modulators the oversampling ratio is limited by slew-rate effects
and finite op-amp gain. As the noise-shaping is only first-order, the digital resolution
will normally not be sufficient high.
2. The quantization error in a first-order ∆-Σ modulator is highly correlated with the
input signal which may cause problems due to pattern noise.
The FDSM concept is, so far, based on first- and second-order noise-shaping. Particularly
the D flip-flop FDSM solutions are suitable for very high sampling speed operation, and can
therefore provide a high digital resolution even if the noise shaping is only first-order. In
this way problem no.1 may be overcomed. By using multi-bit quantization, implemented
either by parallel modulators, or the modulo-2n FDSM, problem no.2 can be significantly
reduced as the worst-case signal to pattern noise ratio is reduced by the number of bits
in the quantizer. In some applications it will however be desirable to use a single D flipflop FDSM with a bit-stream output, and in this case the effect of pattern noise must be
carefully analyzed. In this section we will start by verifying that the FDSM is equivalent
to a traditional ∆-Σ modulator with respect to pattern noise. However, since the internal
signal range in the FDSM may be much lower than in a traditional ∆-Σ modulator, and the
range is defined by frequency ratios and not by voltages, there can be a significant difference
in performance.
4.2.1
Background
The basis for Eq. 2.18 which predicts the resolution of the delta-sigma modulator is based
on the assumption that the quantization noise is white, and thus uncorrelated with the
input signal. This assumption is suitable for most busy input signals. However, for DC
or slowly varying inputs, the white-noise model is far from exact as the quantization error
will be heavily correlated with the input signal. When the input signal is DC, the deltasigma modulator output will bounce between two levels keeping its mean equal to the input
signal. For certain DC input values the output sequence will be repetitive. If the repetition
frequency lies in the signal band, the modulation will be noisy, if not, it will be quiet. In
Fig. 4.4 (top) the input to a traditional delta-sigma modulator is swept over different DC
values and the resulting in-band noise power is measured [10]. The horizontal line represent
the calculated in-band noise level given by the white quantization noise model. As we see
from the figure, there are certain input DC values which produce an output noise power
far above the calculated level. For other input values the measured power is far below the
white-noise level. This inherent feature is called pattern-noise. From [10] half the total
power is found to be in the end peaks while 1/16 in the central ones.
Most traditional delta-sigma modulators need to utilize most of their signal range to
reduce the effect of internal noise sources. It is therefore normally necessary to let the signal
range overlap many of the pattern noise peaks in the figure. As we soon will see, the FDSM
is equivalent with respect to pattern noise, but here the internal signal range can be very
small compared to the output levels. As the signal range location is defined by the fc /fclk
83
Total in-band noise power (dB)
DC value
20
25
30
35
40
45
0
0.1
0.2
0.3
0.4
0.5
DC value
0.6
0.7
0.8
0.9
1
20
25
30
35
40
45
0
0.5
1
1.5
2
2.5
Constant frequency (MHz)
3
3.5
4
Figure 4.4: Top) Measured DC scan, traditional delta-sigma modulator. Middle) Theoretical DC
model. Bottom) Simulated FDSM frequency scan. Horizontal lines - white noise model. For all
plots - oversampling ratios = 9.14
ratio, we may for small signal ranges, locate the signal range in a pattern noise valley and
achieve a significantly higher resolution than the white-noise model predicts. A necessary
requirement for doing so, is that we have control over practical effects such as temperature
drift and aging which may affect the fc /fclk ratio.
The pattern noise picture is a direct function of the oversampling ratio. In Fig. 4.5 a
theoretical DC scan is carried out for three different oversampling ratios. We notice that
both the heights of each peak and the valley depth is increased as the oversampling ratio is
increased. In addition, the number of visible peaks increases. However, since the widths of
the peaks are reduced, the power in each peak is inversely proportional to the oversampling
ratio cubed.
4.2.2
A theoretical model for pattern-noise
In [10] an analytical model for the output of a first-order delta-sigma modulator with DC
input is given. The analysis is carried out for a continuos-time modulator, which is shown
84
20
25
fmax = 437KHz
30
35
45
0
0.5
1
1.5
2
2.5
Constant frequency (MHz)
3
3.5
4
0
0.5
1
1.5
2
2.5
Constant frequency (MHz)
3
3.5
4
0
0.5
1
1.5
2
2.5
Constant frequency (MHz)
3
3.5
4
30
35
40
fmax = 133KHz
Total in-band noise power (dB)
40
45
50
55
60
65
50
60
fmax = 5000Hz
70
80
90
100
110
Figure 4.5: Theoretic DC model for different oversampling ratios, fclk = 8MHz. Horizontal lines white noise model.
to be equivalent to a discrete-time model. For a DC input of amplitude x, the output
components that lie in half the frequency band can be expressed as
yx (t) = x + 2
∞
sin(πlx)
l=1
πl
cos(2π frac[lx]tfclk )
(4.19)
Where frac[x] is the fractional roundoff of x, that is x minus the closest integer to x. In
Eq. 4.19 the first part is recognized to be the input itself, while the sum represents the
quantization noise. As we see, the quantization noise consists of scaled harmonic components
with a frequency dependent on the index l. For a harmonic component to lie in the signal
band 0 < f < fmax we have
f
fmax
= |frac[lx]| <
fclk
fclk
(4.20)
and the power associated with that component will from Eq. 4.19 be
Pl (x) = 2
sin2 (π frac[lx])
(πl)2
85
(4.21)
The total noise power in the signal band is then found by adding together the power of all
harmonics where the index l satisfies Eq. 4.20. The two equations Eq. 4.20 and Eq. 4.21 are
the basis for the theoretic model used in this thesis. In Fig. 4.4 (middle) the theoretic model
is used to predict the pattern noise picture for the same oversampling ratio that was used
in the measurement. Although the measured result is more smoothed, the model resembles
the main shape.
4.2.3
Verification of the FDSM equivalence by simulation
To be able to use the presented pattern noise model to describe pattern noise in the FDSM,
we must first verify that the FDSM behaves equivalent to a traditional delta-sigma modulator
with respect to pattern noise. Sweeping the component 2(fc + kxn )/fclk in Eq. 4.3 over the
interval 0-1 is equivalent to sweeping the input x in the traditional modulator over the
interval 0-1, as the traditional modulator output can be expressed yn = xn + en − en−1 .
A simulated frequency scan of a D flip-flop FDSM with fc =425KHz and fclk =8MHz
was carried out. The signal bandwidth was set to 437KHz to match the two other plots
in Fig. 4.4, and the input frequency was swept from 0 to 4MHz in 500 steps. In Fig. 4.4
(bottom) the resulting in-band noise-power is shown. The match with the theoretical model
is almost exact. The D flip-flop FDSM was simulated in C while the output bit-stream
analyzed in Matlab (Appendix B). In Fig. 4.6 the input frequency is swept from 0-12MHz
to illustrate the pattern noise picture for multi-bit conversion. By this we can conclude
that the model given by Eq. 4.20 and Eq. 4.21 is well suited to describe pattern noise in
the FDSM for constant inputs. By constant inputs in the FDSM we refer to constant or
unmodulated input frequencies.
BW noise power (dB)
20
25
30
35
40
45
0
2
4
6
8
Constant frequency (MHz)
10
12
Figure 4.6: Theoretic DC model for multi-bit conversion fclk = 8MHz, oversampling ratio = 9.14
4.2.4
Valley utilization
For systems where the FDSM signal range is small, the range may be located in a pattern
noise valley by choosing a proper fc /fclk ratio. As an example, for a specific FM demodulation system the carrier frequency was 425KHz with maximum deviation 550Hz, and a 8MHz
system clock was applied. In this case the signal range is given by 4∆f /fclk = 0.00025 or
0.025% of the quantization level spacing illustrated in Fig. 4.5. In Fig. 4.7 a zoom of the
quantization level interval is shown where the signal range is illustrated by a short horizontal
line on top of the peak/valley landscape. The oversampling ratio is 10 000 and there are
peaks at ≈20dB above the white noise level. We also notice valleys far below this level. If
the fc /fclk ratio can be properly chosen and fixed we may gain a significantly amount of
resolution by locating the range in one of these valleys.
86
BW noise power (dB)
In Fig. 4.9 the picture is zoomed down to the size of the dynamic range, and the range
is now located over one of the highest peaks in Fig. 4.7. Now the structure of the peak is
revealed showing a symmetrical bat shape. The top is ≈20dB higher than the white noise
level while the area close to its side walls are >30dB lower than the white noise level.
In many systems it is not possible to keep a fixed fc /fclk ratio due to temperature drift
and process deviations. In this case the dynamic range may accidentally be located over
one of the peaks in the pattern noise landscape, and a significantly performance reduction
will result. One way to overcome this problem may be to use a feedback arrangement where
the mean value of the decimator output is used to tune either fc or fclk to achieve a proper
fc /fclk ratio. Another solution is to use a dither signal to smooth out the pattern noise
landscape. In this way the peaks are removed at the cost of shallower valleys as we will see
next.
100
110
120
130
140
3.8
3.9
4
4.1
4.2
4.3
4.4
Constant frequency (Hz)
4.5
4.6
4.7
4.8
5
x 10
Figure 4.7: Frequency scan, theoretic model. Zoom of Fig. 4.5 (bottom). Short horizontal line in
center/top indicates FDSM dynamic range. Long horizontal line - white noise model.
87
4.3
Time-domain dithering
A frequently used technique to reduce the effect of pattern noise in traditional delta-sigma
modulators is dithering [3]. There are two main topologies for dithering. I) Adding a pseudo
random signal to the input of the modulator. II) Adding a noise shaped pseudo random
signal to the input. The first method may reduce the signal to noise ratio significantly
while the second method preserves the resolution by adding mainly out of band noise to
the modulator. This noise will then be removed by the decimator. Adding noise-shaped
dither to the input is equivalent to adding white noise to the quantizer input as illustrated
in Fig. 4.8. For the FDSM, this is equivalent to adding white phase noise to the FM (or
clock) signal. In applications where it is difficult to locate the signal range in a pattern noise
valley, white phase noise can be added to the FM / clock signals to reduce the correlation
between the signal and the noise floor.
dn
xn
dn
z -1
Q()
yn
z -1
z -1
Figure 4.8: Two different dithering strategies
100
100
110
110
120
120
BW noise power (dB)
BW noise power (dB)
In a traditional delta-sigma modulator, the recommended dither magnitude is 1-2LSB
of the decimated word. If a maximum-length pseudo random sequence generator [29] is
used, a sequence length of > 226 is recommended together with a 8 level quantization of the
pseudo random output [3]. These values are also found to be convenient in the FDSM by
simulations and measurements.
130
140
130
140
150
150
160
160
170
4.44
4.442
4.444
4.446
Constant frequency (Hz)
4.448
170
4.45
5
x 10
4.44
4.442
4.444
4.446
Constant frequency (Hz)
4.448
4.45
5
x 10
Figure 4.9: Simulated frequency scan. Zoom of Fig. 4.7 down to dynamic range of FDSM, centered
over right twin-bat. Horizontal line - white noise model. Left figure: No phase noise added, right
figure 0-30ns white phase noise added
The same frequency scan that produced the result in Fig. 4.9 left have been repeated
for the same modulator, but now a 0-0.73rad pseudo random dither signal is added to the
88
FM phase. The simulation result is shown in Fig. 4.9 right. The bat magnitude is now
reduced to maximum ≈0.5dB above the white noise level at the cost of a higher noise level
in the neighborhood. In this case the FDSM output noise floor will be almost independent
on the modulating signal amplitude and the signal range location which can be a desirable
situation.
4.3.1
Measurements
To verify the theory a test board was build where the FDSM, decimator and pseudo random
generator was implemented in Altera FLEX 10K20 Fig. 4.10. White phase noise was added
to the FM signal by the use of a 74AS04 based delay line. By selecting one tapping at a
time through a pseudo randomly controlled multiplexer the time shift was approximately
uniformly distributed in the 0-30ns interval. A SUN workstation was used to collect and
analyze the output data, and the FM signal was made by a GPIB controlled HP33120A
signal generator.
Signal gen
HP33120A
Pseudo random
generator
ALTERA FLEX9000
Matlab
sinc2 decimator
bus interface
and diver
SUN
workstation
GPIB
FDSM
S16D interface
74AS04
MUX
Crystal
oscillator
Figure 4.10: The FDSM test board
In Fig. 4.11 the output psd is shown for two measurements where the FM carrier frequency is 425kHz. The maximum deviation caused by the 67Hz modulating sinusoidal is
∆f =550Hz, and a sampling clock frequency of 8MHz was used. In the left figure no extra
phase noise is added to the system. The noise floor is dominated by spurious noise tones
which indicates that the quantization noise is far from white. In the right figure a 0-30ns
pseudo random phase noise is added to the FM signal. We notice that the noise floor is
slightly increased and more smooth as the quantization noise is whitened.
In Fig. 4.12 two measured amplitude scans are shown for a carrier frequency fc of 425KHz,
and a clock frequency fclk of 12MHz. A number of 75300864 clock samples where taken for
each measurement. 1000 measurements are carried out for different constant FM deviations
caused by a sinusoidal. As the amplitude of the sinusoidal increases, the S/(N+D) follows.
A decimation ratio of 2048 is choosen. The upper graph represent the S/(N+D) ratio where
no dithering is applied. For all signal amplitudes the S/(N+D) ratio is well above the white
noise model shown by the bottom line. This indicates that the dynamic range is located in
a pattern noise walley. For certain signal amplitudes the extremal values of the modulating
89
0
Normalized PSD (dB)
Normalized PSD (dB)
0
-50
-100
-150
10
100
Frequency (Hz)
-50
-100
-150
1000
10
100
1000
Frequency (Hz)
Figure 4.11: Measured result, fc = 425KHz, fclk = 8MHz, ∆f =550Hz, fmax =500Hz. Left figure no extra phase noise is added. Right figure - 0-30ns pseudo random phase noise is added to the FM
signal
sinusoid are close to a pattern noise peak producing excess noise. This is clearly seen for
deviations slightly above 200Hz where the curve drops rapidly.
In the next measurement, 0-30ns dither is added to the FM signal. Now the curve is
an almost ideal straight line increasing by 20dB/decade with the FM deviation. The most
interesting point is where the dithered curve exceeds the non-dithered curve at ≈225Hz.
This shows that phase noise can be used to increase the resolution for certain input levels
confirming the simulated result in Fig. 4.9.
Finally, just to illustrate that the D flip-flop FDSM also can be used in high resolution
applications, it is included a measurement where the frequency deviation is set to 2.6MHz
and the corresponding FM carrier frequency is raised to 7MHz. The psd of the measured
output signal is shown in Fig. 4.13. The measured harmonic distortion is considered to be in
the frequency modulator and not in the FDSM, as it corresponds well to the specifications
of the FM signal source which is in the -80dB range. By disregarding the 2’th harmonic
component, the resolution is found to be almost 20bit in the 0-500Hz signal band.
90
60
55
1000 measurements, each 73536000 fclk cycles
sinc2 decimator, dec ratio 2048
50
45
S/N+D (dB)
d
de
40
ise
ad
s
tep
o
en
as
h
op
35
s
0n
N
ise
ase
30
m
do
FM
eu
25
Ps
8s
0-3
no
ph
l
de
ise
an
r
do
in
mo
o
en
hit
W
20
15
10
1
2
10
10
FM deviation (Hz)
Figure 4.12: Measured result.
Amplitude (deviation) scan.
fc = 425KHz, fclk = 12MHz,
fmax =500Hz
S/N = 118dB (19.7bit), S/D = 83dB, f0 = 6.4MHz, FMdev = 2 .6MHz, fm = 179Hz, fclk=32.7MHz
0
−20
Normalized PSD (dB)
−40
−60
−80
−100
−120
−140
−160
−180
1
10
2
10
Frequency (Hz)
3
10
Figure 4.13: Measured result illustrating high frequency operation. Deviation 2.6MHz, decimation
ratio 2048
91
Chapter 5
Conclusion and future work
In this thesis four novel first-order FDSM techniques have been proposed and analyzed.
Practical effects such as phase noise and pattern noise have been modeled and evaluated.
Compared to previously existing FDSM techniques, some of the techniques presented here
will increase the digital resolution significantly for certain applications. Other techniques
make the FDSM concept more suitable for very high frequency operation by extending the
usable range of the D flip-flop FDSM.
5.1
Summary
In the following the main contribution of this thesis to the FDSM research field is summarized.
Triangularly weighted ZC counting
The most straight-forward way to do frequency-to-digital conversion is to count the number
of FM zero-crossings during a fixed time interval, and then let this number be the digital
representation of the FM frequency. This is done in the classical zero-cross counting frequency discriminator. In this converter the position of each zero-count within the counting
time interval do not affect the output signal as the converter employs a uniform window
on the input data. In this thesis we have seen that by using a triangularly weighted data
window, equivalent first-order ∆-Σ noise-shaping results. In this way the difference between
the ordinary zero-cross counting frequency discriminator and the FDSM can be modeled as
a difference in an inherent data window, and the understanding of the FDSM operation is
simplified.
Undersampling
In this thesis, we have shown that the D flip-flop FDSM can be operated in FM undersampling mode where the sampling frequency is lower than 2(fc + ∆f ). This means that the
D flip-flop FDSM can replace the modulo-2n FDSM in applications where the input FM
frequency is very high. Since the maximum input frequency in a FDSM is limited by synchronizer metastability effects, it is important to keep the synchronizing elements as simple
as possible. From this point of view the D flip-flop FDSM is an ideal choise as there are
no simpler way to synchronize a signal than using a single D flip-flop. In addition, the D
92
flip-flop FDSM provides ≈6dB higher digital resolution than the modulo-2n FDSM as it
counts both positive and negative FM signal edges.
The operation of the FDSM in undersampling mode is analyzed both in the time and in
the frequency domain. In the frequency domain analysis, the D flip-flop FDSM is modeled
as a converter digitizing the FM signal, directly followed by a digital demodulator. In other
words, the FDSM is now modeled without considering the phase of the FM signal. By doing
so we have seen, without proving it mathematically, that pattern noise can be modeled as
interference between the FM signal band and higher harmonics of the FM band that are
folded down in frequency.
The sampled clock FDSM
By doubling the sampling frequency in the traditional first-order FDSM, the in-band quantization noise is reduced by ≈9dB. However, the signal range is also reduced by a factor
of two. The net gain will therefore only be ≈3dB. In this thesis we have shown that by
exchanging the clock and FM input signal to the FDSM, a similar noise-shaping converter
results. This converter operates by counting the number of zero-crossings in the clock signal
during the time varying FM period, thus the name sampled-clock FDSM. In this converter
the SQNR is increased by ≈6dB for each doubling of the constant frequency, and a higher
digital resolution can be achieved for applications where the clock frequency is higher than
the FM carrier frequency. To analyze this circuit mathematically, the concept of virtual
frequencies have been introduced. The sampled-clock FDSM can be realized both as a
modulo-2n FDSM, and also as a D flip-flop FDSM. The sampled-clock D flip-flop FDSM
have also been analyzed in undersampling mode, both in time and in frequency.
The sampled-clock FDSM is inherent non-linear with a 1/(k +x) signal transfer function.
The non-linearity is given by the ∆f /fc ratio. For low relative deviations the THD can be
in the <-100dB range. For applications with high relative deviations, the non-linearity can
be significantly reduced by digital correction since its transfer function is well defined. The
ouput data-rate of the sampled-clock FDSM is given by the FM signal frequency and is
thus time varying. It have been shown that resampling of such time-varying data-rates are
possible [19, 30]. A single experiment carried out in this thesis indicates that it may also be
possible to remove most of the non-linearity in the resampling operation.
The D flip-flop ring-oscillator FDSM
It is shown that the pointer FDSM read-out circuit can be simplified by replacing it with
a parallel connection of D flip-flop FDSM’s. In this way the maximum sampling frequency
can be somewhat increased, increasing the SQNR. The new circuit is a single-bit FDSM but
by replacing the output XOR gate with a binary adder, the concept of parallel conversion is
introduced. It is recently proved [24] that flicker noise is reset and thus significantly reduced
in a CMOS ring-oscillator. This result combined with the fact that phase-noise is noiseshaped in a FDSM (se next), makes the ring-oscillator FDSM a very interesting candidate
for low-noise integrated sensor applications.
Parallel conversion
With the D flip-flop ring-oscillator FDSM, the concept of parallel conversion was introduced.
Parallelisation is based on the use of several signal channels carrying different FM phase
information. However, if the input to the converter is a single FM signal, no extra phase
information is supplied, but one way to obtain additional phase information is by the use
93
of a open-ended delay line. This solution have been analyzed both theoretically and by
simulations.
For small relative FM deviations, the open-ended delay-line FDSM can be biased to
behave almost exactly like the ring-oscillator FDSM with respect to quantization noise.
However, for high relative FM deviations the distribution of the phase information over the
channels will be disturbed causing a degradation in the overall SQNR. For a high number
of channels where inverter delay mismatch is present, the overall effect of this disturbance
will follow a very complex pattern and should rather be modeled by statistical methods.
This is not done yet, but by simulations it is found that for a high number of poorly
matched inverters, where the total line delay is more than ≈5 times the FM period, the
overall SQNR tends to follow the SQNR of the ring-oscillator FDSM with a maximum loss
of ≈15dB. From these results, the delay-line FDSM seems like an interesting way to go for
increasing the digital resolution in first-order FDSM’s.
To verify the analysis, a 1024-inverter delay-line FDSM have been implemented in CMOS
VLSI by a collaboration between the author and the ∆-Σ group at IFI. The chip is targeted
at 24-bit audio conversion and will soon be returned from the AMS foundry.
Phase noise analysis
Phase noise is a major problem in many FM demodulation systems. In this thesis the effect
of phase noise, both on the FM signal, and also on the clock signal have been analyzed, both
analytically, by simulations and by measurements. It is found that phase noise, both on the
FM signal and on the clock signal, is first-order shaped by the FDSM. By considering FM
signal phase noise, clock signal phase noise and the quantization noise as uncorrelated, a
model for the resulting in-band noise power in the demodulated signal is given. As the phase
noise is shaped, the resulting output power from a harmonic phase noise component will be
dependent on its frequency. Low frequency components in the signal band will be heavily
suppressed while out-of-band components will be removed by the decimator. White phase
noise may actually improve the performance of the FDSM as it will act as a noise-shaped
dither signal and suppress pattern noise.
Pattern noise analysis
A major problem in traditional first-order ∆-Σ modulators is pattern noise. In this work,
we have found that the FDSM is equivalent to a traditional ∆-Σ modulator with respect to
pattern noise. By using a well established model for pattern noise [10], we have been able
to model pattern noise in the FDSM to a high degree of accuracy. Then we have discussed
three strategies that may eliminate this problem. First, we have presented the multi-bit
parallel FDSM concept. In a multi-bit ∆-Σ modulator the worst case signal to pattern noise
ratio is reduced by the number of bits used. As an example, we have designed a delay-line
FDSM with an effective word length of 7-bit. In this modulator problems due to pattern
noise is expected to be almost eliminated. Next, for applications where the ∆f /fclk ratio
is small, the FDSM internal dynamic range will be small, and by controlling the location
of the dynamic range in the quantization level interval, given by the fc /fclk ratio, we can
locate the dynamic range in a pattern noise valley. In this way the problem with pattern
noise is reversed to an advantage making the effective digital resolution higher than the
white quantization noise model predicts. This result is verified both by simulations and
measurements.
In some applications it will be difficult to maintain a fixed fc /fclk ratio due to various
practical effects such as temperature drift, aging and so on. In this case, it can be impossible
94
to locate the dynamic range in a pattern noise valley, and in the worst case, the range can
be accidentally located at the top of a pattern noise peak. For these cases, it will be possible
to add phase noise to decorrelate the quantization error and the modulating signal as we
will see next.
Time-domain dithering
In this thesis it is shown that adding white noise to the quantizer input in a traditional ∆-Σ
modulator is equivalent to adding white phase noise to the FM signal in the FDSM. In this
way, the most frequently used dithering technique in the traditional ∆-Σ modulator can be
applied to the FDSM. A simple way to add white phase noise to the FM signal, is to feed the
FM signal through a delay-line and select one tapping at a time with a multiplexer controlled
by a pseudo random sequence. This technique have been verified both by simulations and
measurements.
5.2
Conclusion
The main aim of this thesis was to develop techniques making it possible to reduce the
analog complexity of ∆-Σ converters by the use of first-order FDSM solutions. This aim is
met in the following way:
1. Modeling and understanding Through the concept of triangularly weighting and
the work done on phase and pattern noise, the behavior of the FDSM is now extensively
modeled and understood. This is a necessary requirement for using the FDSM in
practical applications.
2. Pattern and phase noise The problem with pattern noise is significantly reduced or
eliminated through the multi-bit parallel FDSM concept. Alternatively, time domain
dithering and pattern noise valley utilization have been proposed to reduce or eliminate
this problem. Phase noise is found to be noise-shaped by the FDSM. By this, it is
shown that the first-order FDSM can be used in practical high resolution applications.
3. Resolution By the sampled-clock and the parallel FDSM concept, the resolution of
the FDSM is significantly increased making it possible to use the first-order FDSM
even in high-bandwidth / high-resolution applications.
4. Extended use By the concept of FM undersampling the usable input frequency range
of the most simple D flip-flop FDSM is extended allowing for use in high frequency
RF applications.
By the D flip-flop ring-oscillator FDSM we have presented an example where a ∆-Σ analogto-digital converter can be made only by standard digital gates. In this case the only analog
node in the converter is the power-supply line to the ring-oscillator inverters. As an analogto-digital converter it is not possible to reduce the analog circuitry further.
5.3
Future work
The FDSM research field is still in its infancy, and there are many leads to follow, both to
increase the performance in already developed solutions, but also by using the FDSM idea
in other applications. In the following a brief list of topics are given.
95
Massive parallelism
Since quantization in the FDSM is done in time or phase, we have seen that the FDSM
can be implemented by a delay line and a parallel collection of D flip-flops plus an adder.
Since each D flip-flop FDSM is very compact, the main chip area will be dominated by the
adder tree. The adder tree can be significantly simplified by extensive use of modulo adders
or XOR gates, and it will be possible to make converters with a very high number of parallel
channels. Another interesting feature is that the parallel FDSM is quite fault tolerant, as
stuck at 1 or stuck at 0 errors in a few channels will almost not be of no significance at the
output since this effect only represents a bias in the output signal.
The resulting quantization noise from a delay-line FDSM with a large number of channels,
including random inverter delay mismatches, have not been statistically modeled yet. It
would be interesting to know more about the noise propertied of a ∆-Σ modulator based on
a “sea of D flip-flops”.
Low noise integrated sensors
As proved in [24], flicker noise is reset and thus significantly reduced in a CMOS ringoscillator. In addition, we have seen that phase-noise is noise-shaped in a FDSM, and this
makes the ring-oscillator FDSM very interesting for low-noise integrated sensor applications.
This result explains why there was not found any noise floor down to 7.5Hz in the pointer
FDSM measurement carried out in [7]. When it comes to transistor thermal noise, we have
reason to believe that increasing the number of inverters will decrease the overall output
noise as the thermal noise is not correlated from transistor to transistor. By doubling the
number of inverters,
the overall thermal noise rms value should therefore be decreased by
√
a factor of ≈ 2. However, this result is not yet documented but it may be an interesting
way to go.
Linearity improvement in ADC applications
The FDSM concept can be used both in ADC and FDC applications. By replacing a
traditional feedback ADC ∆-Σ modulator by a FDSM, the overall linearity of the converter
will be given by the linearity of the frequency modulator in the actual frequency range.
Deterministic non-linearity given by a non-linear frequency modulator transfer function can
be compensated for digitally at low sampling frequency if the transfer function is known.
On the other hand, non-linearity given by random variation in process parameters and
temperature drift requires a more complicated calibration process before digitally correction
can take place. To improve linearity in ADC applications one may therefore try to design the
frequency modulator in a way that keeps the random or stochastic part of the non-linearity
as small as possible. A differential solution may be a good starting point for this work.
New applications
Most activity in the ∆-Σ research field today is focused on fine tuning more or less
classical SC circuits to squeeze out another bit in resolution. We will not revile this activity
as this is outmost important from an industrial point of view. However, from an academical
point of view it is more interesting to catch the basic ideas behind noise-shaping. By
understanding the underlying basics we may be able to use the technique in other, more
distant fields where the name ∆-Σ is still unknown.
The FDSM concept have, to some extent achieved this, as it is based on viewing the ∆-Σ
process as a cascade of a modulo integrator and a modulo differentiator with a quantizer in
between. By peeking into the RF field, the main feature of the ∆-Σ noise shaping idea, the
modulo integrator was first found in the standard FM signal represented by the FM phase.
96
When this was done, all we needed was a quantizer (ZC counter or D flip-flop) and a digital
modulo differentiator. Then the way to high quality FM demodulators were relatively short.
Noise-shaping is actually a more general technique than described here. The very basic
idea is to suppress the effect of an interfering signal on another signal. The signal that we
want to shelter is first protected from the interference by changing its structure in one or
another way. When the interference is over, the structure of the original signal is changed
back again. When the structure is changed back, the structure of the interference is changed
similarly. So what we are aiming for is to change the structure of the interference to make
it less troublesome in the final signal. In low-pass ∆-Σ modulators the structure reversal
is done by digital high-pass filtering, and the interference is quantization noise. By using a
high-pass filter, the interference in the signal band is reduced.
In bandpass ∆-Σ modulators [4, 5] it can be shown that the underlying operation can be
described by a cascade of a resonator (bandpass filter) and an anti-resonator (bandstop filter)
where the quantization error is entering in between. In this case the final filter suppresses
the interference in the signal band that now are located some where up in frequency. So,
one way to change the structure of the original signal is by linear filtering, but in principle,
the original signal can be protected in many different ways.
In the RF field today, there are numerous modulating techniques FSK, QAM, SSB, ASK..
[31]. There have not yet been searched in any other modulation technique for noise-shaping
features, but there is reason to believe that there may be something out there.
97
Chapter 6
Publications
6.1
IEE Electronics Letters no. 1
Vol.31, no.2, pp.81-82, 1995
98
99
6.2
ISCAS no. 1
Proceedings IEEE ISCAS’95, pp.175-178
102
103
6.3
IEEE Journal of Solid State Circuits
IEEE Journal of Solid State Circuits, vol.32, no.1, pp.13-22, January 1997
108
109
6.4
ISCAS no. 2
Proceedings IEEE ISCAS’97, pp.77-80
120
121
6.5
IEE Electronics Letters no. 2
Vol.33, no.13, pp.1121-1122, 1997
126
127
6.6
Low Power
Proceedings on the 1997 International Symposium on Low Power Electronics
and Design, Monterey, CA, USA, pp.52-55, August 1997
130
131
6.7
NorChip
Proceedings 17’th IEEE NorChip’99, pp.391-398
136
137
Appendix A
PSD definitions
The following definitions are used througout this thesis.
The Wiener Khintchine theorem
Sx (f ) =
rxx (k)e−jk2πf
(A.1)
k
The total power definition
Ptot =
f
clk /2
1
fclk
Sx (f )df
(A.2)
−fclk /2
White noise
Sx (f ) = σx2
(A.3)
Ptot = σx2
(A.4)
Harmonic component A sin(2πfm n)
Sx (f ) =
fclk A2
[δ(f − fm ) + δ(f + fm )]
2
Ptot =
,
−fclk
fclk
<f <
2
2
A2
2
(A.5)
(A.6)
Sx (f ) estimation
The modified periodogram estimator
1
Ŝx (f ) =
NU
N −1
2
−jn2πf wn xn e
n=0
148
(A.7)
U=
N −1
1 |wn |2
N n=0
(A.8)
The expected value
E{Ŝx (f )} =
1
Px (f ) ∗ |W (f )|2
2πN U
(A.9)
Ŝx (fm ) versus Ptot
Ŝx (fm ) =
Ptot =
Ptot
N − loss
4
(A.10)
4
(Ŝx (fm ) + loss)
N
(A.11)
Loss: Rectangular window: 0dB, Hamming: 1.6dB, Blackman: 2.4dB, BHH: 4.2dB.
The Blackman-Harris-Hoodie window
wk = w0 −
6
wm cos
m=1
w0 =0.6164032131405
w1 =0.98537119272586
w2 =0.49603771622007
w3 =0.14992232793243
w4 =0.02458719103474
w5 =0.0017660465148687
w6 =0.000031581188567106
149
2mπk
N
(−1)m
(A.12)
Appendix B
C simulators
150
159
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