Scaling of SiGe Heterojunction Bipolar
Transistors
JAE-SUNG RIEH, SENIOR MEMBER, IEEE, DAVID GREENBERG, MEMBER, IEEE,
ANDREAS STRICKER, MEMBER, IEEE, AND GREG FREEMAN, SENIOR MEMBER, IEEE
Invited Paper
Scaling has been the principal driving force behind the successful
technology innovations of the past half-century. This paper investigates the impacts of scaling on SiGe heterojunction bipolar transistors (HBTs), which have recently emerged as a strong contender
for RF and mixed-signal applications. The impacts of scaling on
key performance metrics such as speed and noise are explored, and
both theory and data show that scaling, both vertical and lateral,
has mostly beneficial effects on these metrics. However, it is shown
that the scaled devices are increasingly vulnerable to device reliability issues due to increased electric field and operation current
density. Bipolar transistor scaling rules are reviewed and compared
with accumulated reported data for verification. A review of scaling
limits suggests that bipolar scaling has not reached the physical fundamental limit yet, promising a continued improvement of bipolar
performance in the foreseeable future.
Keywords—Heterojunction bipolar transistors (HBTs), scaling,
silicon germanium.
I. INTRODUCTION
The performance of semiconductor devices tends to improve as the device dimensions shrink. This simple principle
of scaling has been the key to the spectacular success of
semiconductor industry over the past half-century. It has
worked for virtually all types of transistors, including the
Si-based bipolar transistor as will be detailed in this paper.
Historically, scaling has run into apparent hard limits multiple times in the course of bipolar technology evolution,
which have been successfully overcome with help from
material and structural innovations, such as the self-aligned
base, poly emitter, epitaxial base, and, most recently, the
Manuscript received August 18, 2004; revised March 16, 2005.
J.-S. Rieh is with the Dept. of Electronics Engineering, Korea University,
Seoul 136-701, Korea (e-mail: jsrieh@korea.ac.kr).
D. Greenberg is with the IBM T. J. Watson Research Center, Yorktown
Heights, NY 12533 USA (e-mail: drgreen@us.ibm.com).
A. Stricker is with IBM Microelectronics, Essex Junction, VT 05452 USA
(e-mail: stricker@us.ibm.com).
G. Freeman is with IBM Microelectronics, Hopewell Junction, NY 12533
USA (e-mail: freemang@us.ibm.com).
Digital Object Identifier 10.1109/JPROC.2005.852228
Fig. 1. The trend of cutoff frequency f over the past two
decades, categorized by conventional implanted-base Si BJTs (I/I
Si BJT), epitaxial-base Si BJTs (Epi Si BJT), SiGe HBTs (SiGe
HBT), and SiGe HBTs with carbon-doped base (SiGeC HBT).
SiGe base. SiGe heterojunction bipolar transistors (HBTs),
which incorporate such a SiGe base, benefit from the
availability of “bandgap engineering” owing to the smaller
bandgap of SiGe than that of Si. This adjustable bandgap
provides an entirely new dimension for device design
and serves as an enormous leverage for performance enhancement, especially when combined with the excellent
scalability of Si technologies. Such improvement is evidenced by the recently reported SiGe HBTs exhibiting
exceeding 350 GHz [1], [2]. The purcutoff frequency
pose this work is to discuss the impacts of scaling on the
performance of Si-based bipolar transistors, with a main
focus on SiGe HBTs.
It would be helpful to first take an overview of the performance trend of Si-based bipolar transistors. Fig. 1 shows
since the early 1980s, which
accumulated data points for
include traditional implanted-base Si bipolar junction transistors (BJTs) [3]–[24], epitaxial-base Si BJTs [25]–[32],
SiGe HBTs [27]–[60], and SiGeC HBTs (a variation of
0018-9219/$20.00 © 2005 IEEE
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PROCEEDINGS OF THE IEEE, VOL. 93, NO. 9, SEPTEMBER 2005
that compose the system. The speed of a device can be represented by various measures and corresponding speed parameters. Although some alternatives have been proposed [75],
the most widely used speed parameters for transistors are the
and the maximum oscillation frequency
cutoff frequency
, which are defined as the frequency point where the current gain and the power gain become unity, respectively. In
this section, the impact of scaling on speed is discussed for
and
separately, and then experimental data will be
presented.
A. Impact of Scaling on
Fig. 2. The trend of the gate delay over the past two decades
for Si-based bipolar transistors.
SiGe HBTs which incorporate a carbon-doped SiGe base)
[1], [2], [59]–[74] (These sets of references will be reused
for trend charts throughout this paper). Over the span of
was increased by a factor of 30, almost
two decades,
doubling every four years. It is noted that the trend can be
characterized by a “double wave,” the first wave having
reached the peak in the early 1990s, while the second one is
still going on. The saturation of the first wave was caused by
the rapid replacement of bipolar logic with CMOS logic due
to the excessive heat generation in highly integrated bipolar
digital chips, which resulted in power dissipation densities
exceeding 10 W/cm (it is interesting to note that the most
advanced CMOS chips of today have already reached this
point, too). However, Si-based bipolar technologies were
quick to discover another attractive application field, RF and
mixed-signal applications, which favor high device speed
yet which do not require as high a device density as the
digital applications. This fueled another round of research
and development activities on Si-based bipolar technologies, generating the second wave in the trend that continues
through today. Shown in Fig. 2 is the trend of the gate delay,
which is a measure of technology performance rather than
of individual device performance. It also approximately follows the performance trend doubling every four years (delay
reduced by half) over the past two decades. These trends
for speed parameters are the evident results of incessant
vertical and lateral scaling efforts, supported by material and
structural innovations in parallel.
This paper is divided into five parts. In Section II, the impact of scaling on the speed of Si-based bipolar transistors is
discussed, followed by Section III, which covers the scaling
impact on the noise performance of the devices. The relation between scaling and reliability issues are described in
Section IV, and an overview of the bipolar scaling rules are
presented in Section V. Finally, scaling limits for bipolar transistors are discussed in Section VI.
II. SPEED AND SCALING
Excellent speed performance is favored for most practical
semiconductor applications of today. The efficiency of information processing strongly depends on the speed of devices
RIEH et al.: SCALING OF SiGe HETEROJUNCTION BIPOLAR TRANSISTORS
The effect of device scaling on
can be more effectively viewed through a parameter
, the emitter-to-collector delay time, defined as the reciprocal of
multiplied
by a factor of , which can be expressed in terms of bipolar
device parameters as
(1)
where is the Boltzmann constant, is temperature, is
unit electronic charge,
is collector current,
and
are emitter-base and collector-base capacitances,
and
are collector and emitter resistances,
is neutral base
width,
is base-collector space charge region (SCR)
width,
is electron diffusion constant,
is the saturation velocity, and is the field factor which is a measure of
the quasi-electric field established in the base. Both vertical
and lateral scaling affect the device parameters presented in
(1), with vertical scaling having the primary impact because
typical bipolar transistors are vertically layered as shown in
the schematic cross section of a modern SiGe HBT (Fig. 3).
For vertical scaling, collector scaling and base scaling
have the major impacts in practical device structures. The
primary effect of collector scaling is the reduction of
,
which is usually achieved by increasing the collector doping
concentration
, resulting in a reduction in the transit
time across the B-C SCR,
. The reduction of
,
however, necessarily involves an increase in
, leading
to increased RC delay. Therefore, collector scaling requires
a precise balance between these two conflicting parameters
for the optimal speed improvement. A commonly practiced approach for Si-based bipolar transistors to minimize
the
increase due to the increased
is to selectively implant the intrinsic portion of the collector [the
resultant pedestal-shaped structure is called the selectively
implanted collector (SIC)], suppressing the extrinsic component of
. A secondary effect of the collector scaling
with increased
is the increase of the Kirk current
,
the collector current at which a base-widening known as
the Kirk effect takes place. As the Kirk effect occurs when
the mobile carrier concentration becomes comparable to the
background doping concentration, higher doping concentration effectively delays the onset of the base-widening,
1523
Fig. 3. Schematic cross section of a modern SiGe HBT.
thus increasing the maximum driving current level and reand . Another effect
ducing the minimum values of
of collector scaling is an increase in the average velocity
across B-C SCR due to enhanced ballistic transport [76],
.
and
tend to decrease
leading to a reduced
with vertical scaling as the resistive parasitic vertical paths
for current are shortened.
and
The key effect of base scaling is the decrease of
resultant reduction of the transit time across the neutral base
region, , which is usually achieved by reducing as-grown
boron-doped layer thickness along with the suppression of
boron outdiffusion in the subsequent process steps. For the
outdiffusion suppression, reduced thermal cycle and the
inclusion of carbon in the SiGe base region (for SiGeC
HBTs) are currently the most viable options [61], [77]. A
secondary effect of base scaling, especially for devices with
graded base bandgap such as typical SiGe(C) HBTs, is the
increased quasi-electric field in the base region that leads
to reduced
(when the peak Ge composition is assumed
fixed). Base scaling, however, tends to increase the intrinsic
base sheet resistance and, therefore, the total base resistance
. Although
is insensitive to
variation, it will
affect
, as will be discussed shortly. One advantage of
base scaling over collector scaling is the fact that it does
not degrade the B-C breakdown voltage, which makes base
scaling a more favored option for the speed enhancement
in power devices.
The impact of lateral scaling on
is not as pronounced
as vertical scaling, but a certain level of lateral scaling needs
to accompany vertical scaling. Most evidently, the inevitable
increase from vertical scaling can be effectively compensated by lateral scaling. Such compensation applies to
, too. However, lateral dimension reduction leads to the
degradation of
and
as a result of the laterally pinched
vertical current paths. The fringing current component due to
increased emitter P/A ratio also tends to grow when emitter
stripe width is decreased.
2
Since
is positively correlated to , as indicated by the
expression, the benefits of vertical scaling on
also apply
to
, although the impact level is relatively lower. Howdepends on
and
, too, which are actually
ever,
degraded by vertical scaling as briefly described earlier. As a
is complicated
result, the impact of vertical scaling on
and may turn out either positive or negative, depending on
structural details of the given device. On the other hand, lateral scaling, which has only limited influence on , plays
a major role on
. Base current is supplied laterally to
the intrinsic device, unlike emitter or collector currents, and
lateral scaling reduces the resistive current path for base, rereduction. B-C junction area decreases with
sulting in
lateral scaling, too, leading to a reduction in
. As
has a direct correlation with
and
, it greatly benefits
from lateral scaling.
C. Measurement Data
B. Impact of Scaling on
of bipolar transistors can be approximated as
follows:
(2)
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Fig. 4. Effect of the SIC total implant dose variation on:
(a) peak f and f
, and (b) W
(B-C SCR width), C
(B-C capacitance), and J (collector current density) at peak f .
The values of SIC dose, W
, C , and J are normalized to
the control device values. Emitter size is 0.12 2.5 m .
Experiments have been performed to explore the effects
of scaling (vertical and lateral) on IBM’s SiGe HBTs with
GHz [1], [2], [78], [79]. For collector scaling
study, devices with three different SIC implant dose levels
were implemented: a control device and two scaled devices
with total implant dose increased up to 1.7% and 3% of the
PROCEEDINGS OF THE IEEE, VOL. 93, NO. 9, SEPTEMBER 2005
Fig. 5. Effect of the as-grown base width (boron-doped layer width) variation on peak f and
f
. Also shown in the inset is the effect on R and C . The values of the as-grown base width,
R , and C are normalized to the control device values. Emitter size is 0.12 2.5 m .
2
control case. As shown in Fig. 4(a),
exhibits a significant
increase with increased implant dose, which can be ascribed
to reduced
. On the other hand,
shows a slight
degradation with increased dose, mostly due to increased
. No noticeable change in
was observed with the
dose variation. Fig. 4(b) depicts the effect of collector scaling
and
, which are responsible for the observed
on
opposite trends for
and
. The B-C SCR width was
estimated from the intrinsic capacitance density of the B-C
junction. Also shown in the plot is the collector current
at peak , which is raised with increased SIC implant dose
owing to the delayed onset of the Kirk effect, partially responsible for the increased peak .
The effect of base scaling was investigated with devices
with three different as-grown boron-doped layer widths. A
control device and two scaled devices with as-grown borondoped layer widths reduced by 22% and 44% from the control case were fabricated and characterized. As-grown boron
concentration was kept identical for the three cases. Note that
the final values of the boron-doped layer width and the concentration will be different from the as-grown values due to
the thermal cycles that follow the base layer growth step.
Fig. 5 clearly shows an improvement in
with reduced
base thickness, apparently from reduced .
exhibits
an overall degrading trend with base scaling, which can be
attributed to increased
(see inset of Fig. 5) with reduced
base width, resulting from the increased intrinsic base sheet
resistance.
exhibits a small but finite reduction with the
reduced as-grown base width (see inset of Fig. 5), stemming
from a finite reduction in
as the boron-doped layer
was shrunk from both emitter and collector side.
The impact of lateral scaling on speed performance is illustrated in Fig. 6, in which emitter stripe width
was scaled
from 0.2 m down to 0.12 m. Unlike the vertical scaling
case, peak
values show only a limited change over
variation, implying that the effect of the reduced
and
RIEH et al.: SCALING OF SiGe HETEROJUNCTION BIPOLAR TRANSISTORS
Fig. 6. Effect of emitter stripe width W
f .
variation on f and
are canceled out by the increased
and
for the
scaled devices, leaving the RC delay largely unchanged. On
the other hand,
exhibits a substantial increase with the
lateral scaling, which can be attributed to the reduced base
spread resistance due to the shortened lateral current path.
from the reduced B-C
Reduced intrinsic component of
junction area also contributes to the increased
. It is notable from Fig. 6 that the current level does not scale linearly
, the current ratio being smaller than
ratio bewith
tween different scaling levels. For example, the current level
GHz is reduced by only 20 for the
for
scaling from 0.2 m to 0.12 m. At low-current regime,
it can be ascribed to the fact that
does not scale linearly with
due to the perimeter and fixed components.
Note that
, along with
, comprises most of the delay
time in this regime in conjunction with . At high-current
regime, it is attributed to the base push-out being a function
of the carrier density in the B-C SCR, which scales linearly
1525
Fig. 8. Simplified small-signal equivalent circuit model for a
bipolar transistor, including the dominant sources of broad-band
noise.
Fig. 7.
Evolution trend of IBM’s SiGe HBT technologies.
with the effective B-C junction width rather than the emitter
stripe width.
As is clear from the measured data, vertical scaling, which
has been the major driving force for bipolar transistor evoluenhancement. However,
tions, is an obvious enabler for
, which is a key parameter for analog and RF applications, does not always benefit from vertical scaling and may
be adversely influenced depending on the structural details.
This implies that a blind vertical scaling may not necessarily
improve the speed performances of bipolar transistors for
every aspect, and appropriate lateral scaling needs to be
accompanied to achieve a balanced performance. In addition, parasitic reduction and thermal cycle reduction are also
to be carried out along with the scaling. A typical bipolar
technology evolution, such as the one from IBM as depicted
in Fig. 7 as an example, is mostly driven by vertical and
lateral scalings supported by additional structural/process
innovations.
It is noted that the discussions so far have been made for
vertical transistors only, as they are the exclusively adopted
type of SiGe HBTs for practical applications of today. For
lateral SiGe HBTs, as extensively described in [80], lateral
scaling would be a major driver for
improvement while
vertical dimension optimization would also be required for
balanced speed enhancement.
III. NOISE AND SCALING
A. Broadband Noise
The scaling and structural advances aimed at improving
RF figures of merit such as
and
provide a direct benefit for broad-band noise performance as well [81], which is
typically described through four parameters: the minimum
noise figure
, the noise resistance
and the real and
imaginary components of the optimum noise impedance
. These test metrics may be related to more basic device
design parameters such as
and thus to the scaling of
these parameters, by representing each physical noise source
as a component in a small-signal equivalent circuit model
and using this model to determine each noise parameter. An
HBT contains several such physical noise sources. Electrons
moving from emitter to base approach the p-n junction with
1526
a statistical distribution of directions and energies and a
probability of crossing the energy barrier. This process gives
rise to collector current shot noise,
, where
is the measurement bandwidth [82]. Holes moving in
the opposite direction lead to a similar base current shot
. Since both space-charge region and
noise
neutral base recombination are low in a modern HBT, these
two noise sources are typically uncorrelated [83]. Parasitic
resistances, dominated by base resistance
and emitter resistance
, contribute uncorrelated thermal noise voltages
and
, respectively.
Fig. 8 includes these noise sources in a common-emitter
equivalent circuit noise model that is simple yet works remarkably well for capturing the essential bias and frequency
behaviors of the HBT noise parameters. The parameter to
which circuit designers often turn first in evaluating the noise
performance of an RF technology is
, which can be expressed in terms of the model parameters as [83], [84]
(3)
where
and is the
ideality factor. This expression can be simplified for modern HBTs in which is
very close to one, is typically greater than 100 and
is
much larger than
(4)
For an HBT biased at a given current,
exhibits distinct
frequency dependencies at low and high frequency. In the
low-frequency regime at which
,
is constant over frequency, with a value given by
(5)
and inHere, scaling for low noise requires reducing
creasing . The value of
at the device bias is less important, as long as it remains much greater than
. In
the high-frequency regime at which
, however,
rises linear with frequency, as expressed by
(6)
PROCEEDINGS OF THE IEEE, VOL. 93, NO. 9, SEPTEMBER 2005
p
2
While each of these device parameters is influenced by deproduct varies as a function of
vice structure, the
layout as well. Since
and
vary in reciprocal fashion
with total emitter stripe length
,
itself is actually
. The intrinsic portions of both
and
insensitive to
are increasing functions of stripe width
, however,
bringing great benefit to scaling down this dimension.
Proper matching is essential to achieving low noise in a
circuit. Ideally, the real part of the optimum noise impedance
will be equal to the system impedance (typically 50 ), allowing a simplified matching network. This real part
can also be calculated from the equivalent noise circuit model
Fig. 9. Equations for F
optimized over I in the
f = ) regime, related to the F versus
high-frequency (f
I curve for a sample (0.2 19.2) 2 m HBT. Smaller plot
illustrates a graphical means of determining the noise-optimal I
using the device f versus I relationship.
2
(10)
In this regime, reducing
and increasing
at bias become the critical scaling goals and becomes unimportant.
When designing a low-noise circuit, a circuit designer
will typically target an application-specific frequency and
examine the bias dependences of the noise parameters in
aporder to select an optimal bias. Although bias current
pears in (4) directly,
contains an implicit
dependence
as well, which may be expressed in reciprocal form as
(7)
where input capacitance
sets the
versus slope at low bias and determines the upper limit
that would be approached by
at high
if there were
no high-level injection or the Kirk effect. This relationship
may be substituted into (4) to yield an
expression containing fully explicit references to , which may then be
minimized with respect to and simplified according to frequency regime.
In this manner, the bias-optimized
in the low-frequency regime is found to be
opt.
(8)
while the same result simplified for the high-frequency
regime becomes
opt.
(9)
Fig. 9 illustrates these results of this optimization over
bias for the high-frequency case, plotting
versus
at 15 GHz for a 120-GHz 0.18- m HBT, with an inset
connecting the noise-optimal bias value to the behavior of
versus [85]. Note that this bias value is not near peak
, but rather near the 50% of peak- point (for a device
designed for high
rather than for breakdown), or at about
10% of peak
current.
These expressions emphasize the importance of scaling
the product of
and
, which impacts the bias-optimized value of
at all frequencies. In addition to
minimizing this product, maximizing remains important
at low frequencies while minimizing
becomes key at
higher frequencies.
RIEH et al.: SCALING OF SiGe HETEROJUNCTION BIPOLAR TRANSISTORS
The first factor in this expression, equal to the noise resis, is simply a combination of the base resistance with
tance
the emitter-base diode small-signal resistance and is dominated by the former at high currents and the latter at low.
and
are decreasing functions of
,
Since both
optimum match can be tuned through overall emitter length
scaling, unlike
.
The theoretical noise parameter expressions described
above can be used to predict noise scaling trends based
on the expected trends for the related device parameters.
Although
in the low-frequency regime can be improved by increasing , continued scaling with technology
generation is limited by the adverse impact on breakdown
voltage
. In contrast,
and
are each expected
to scale linearly with
, paced by lithographic generation,
in both low- and high-frequency regimes to
allowing
continue to scale down linearly with
. Finally, as vertical
scaling of the HBT structure continues to scale down
and
thus peak ,
in the high-current regime is expected
to decrease as the square root of this scaling factor. Note
that product
closely tracks
in devices
optimized for peak
(optimized to delay the onset of the
Kirk effect at the expense of breakdown voltage), which, in
turn, is proportional to
. Thus, efforts already in place
to increase
with each technology node will naturally
lead to a reduction in
.
The scaling of
expected from the modeling treatment is borne out in practice. Fig. 10 compares
versus frequency for several generations of SiGe HBT
technology ranging from 0.5 m
GHz down
GHz [85].
drops with each
to 0.13 m
generation at every frequency, with an approximately 0.8 dB
overall improvement at 5 GHz and a greater than 3-dB
decrease at 25 GHz. The range of reported
values
for production GaAs PHEMT devices is shown for reference and indicates that low-cost, high-integration silicon
technology can now attain the levels of noise performance
previously associated with a more esoteric process.
Equation (9) indicates that
is expected to scale linearly with
in the high-frequency regime. To
evaluate this expectation, Fig. 11 plots bias-optimized
versus
at 15 GHz for the 0.13–0.5 m nodes,
including two variants of the 0.13- m node in which
has
been varied through a processing split. The measured
1527
Fig. 10. F
versus frequency for three generations of SiGe
BiCMOS technology, with the range of reported GaAs PHEMT
values included for reference.
Fig. 11. F
versus [R C ]
at 15 GHz for three
generations of SiGe BiCMOS technology, including two 0.13-m
200-GHz variants with different base resistance values. The straight
line indicates a strong correlation between the axis variables,
validating the scaling predictions of the simple equivalent circuit
model.
data indeed conforms quite well to the theoretical scaling
trend, validating the use of a relatively simple model for predicting HBT noise as the technology evolves.
B. Low-Frequency Noise
Despite operating at high carrier frequencies or data rates,
wireless and optical communications systems are impacted
not only by broad-band noise but by low-frequency noise as
well. For example, in the local oscillator circuit central to
both types of systems, low-frequency noise is upconverted
by the nonlinear nature of the circuit to create phase noise
skirts around the fundamental frequency. This phase noise
can be downconverted subsequently in the mixer, combining
with the low-frequency noise from the baseband amplifier to
degrade the baseband signal in a direct-conversion receiver.
Although there are several sources of low-frequency noise,
the variety most dominant in modern HBTs is
noise,
so called because it falls approximately inversely with frequency before ultimately merging into the broad-band noise
background at higher frequencies. This
character is actually the composite result of a individual noise generators,
each displaying a Lorentzian noise power spectrum that is
1528
constant below a characteristic frequency and which falls off
above this frequency [86], [87]. For a large number
as
of such generators distributed uniformly in characteristic frebehavior.
quency, the combined spectrum tends toward a
Due to advantages in gain, an HBT in a wireless circuit is
most typically connected in a common-emitter configuration.
For a modern, polysilicon-emitter HBT wired in this mode,
noise is generated primarily in the base current , with
base current noise power
found to increase proportionally with . This noise stems from carrier number fluctuation arising from several trap-related mechanisms [88]–[91].
At medium-to-high bias, carriers are trapped and released
by defects that are typically spread across emitter area
,
concentrated near the thin interfacial oxide layer at the
polysilicon-to-silicon emitter interface. Devices with large
(e.g., 1 m ) contain a large number of traps (e.g.,
30–60 for a 1- m device [88], [91]) and thus display a
relatively smooth
spectrum with little device-to-device
variation. Smaller devices, on the other hand, may contain
relatively few traps and thus show wiggles in
versus ,
with spectra that vary considerably between devices.
At very low biases, the dominant noise mechanism may
shift to recombination and generation along the emitter
stemming from defects in the emitter-base
perimeter
spacer layer. The number of such defects may be small in
virgin devices but can increase significantly as the result of
stress-related damage [88], [89].
can be written emWhere area-related traps dominate,
pirically as
(11)
is a coefficient dependent on areal trap density as
where
well as on the strength of the carrier-trap interaction. Typical values for
from the recent literature fall within the
2–4 10 range, independent of the Ge mole fraction in
the base [91], [92]. This relationship can be used to predict a
scaling trend as well as to guide device optimization specifically for low noise.
The scaling down of emitter width
with lithography
generation may be expected to impact low-frequency noise
through at least two mechanisms. To the extent that emitter
area
scales down along with
, (11) predicts either an
increase in
if
and are help constant or a decrease in
noise if the current density is held constant instead. A smaller
emitter area also implies a larger perimeter to area ratio,
enhancing the role of perimeter noise mechanisms at low
bias such as the generation-recombination from stress-induced traps. Both of these mechanisms are under the control
of the designer, who can select layout and bias appropriately. From a technology design perspective,
may be
reduced by increasing , although this design choice can lead
to a reduced breakdown voltage
. In addition, since
the dominant source of traps at medium-to-high bias is the
emitter-base interfacial oxide layer,
noise should yield
to efforts to reduce the thickness of this layer or to move toward a single-crystal emitter.
PROCEEDINGS OF THE IEEE, VOL. 93, NO. 9, SEPTEMBER 2005
IV. RELIABILITY ISSUES AND SCALING
A. Avalanche and Scaling
Avalanche multiplication due to impact ionization in
semiconductor devices affects not only breakdown voltages but device reliability as well. In bipolar transistors,
avalanche-generated carriers tend to attain sufficient kinetic
energy while traveling along the high field region and interact with dielectric or semiconductor-dielectric interfaces,
thus damaging the devices. A typical degradation signature
at
due to such damage is an increase in base current
range, which is an indication of trap generation
lowwithin E-B SCR or at interface/surface exposed to E-B SCR.
Carriers generated at the reverse-biased E-B junction, which
affect dielectric interface along the emitter periphery, are
degradation, while it is also
mainly responsible for such
reported that avalanche-generated carriers at the reverse-biased B-C junction possibly travel to the emitter region and
induce similar damage [93]. For devices with oxide isolation
such as shallow trench, the avalanche-generated carriers
at B-C junction may induce an increase in B-C junction
leakage as well, by degrading the isolation oxide interface.
Scaling tends to enhance avalanche multiplication in
general. Vertical scaling typically involves increased doping
concentration, which strengthens the peak electric field
inside space charge regions. Since avalanche multiplication
has a positive correlation with the peak electric field, it is
enhanced by increased doping concentration and thus by
vertical scaling. Compared to implanted-base Si bipolar
transistors, SiGe HBTs typically maintain a lower doping
concentration at E-B junction owing to the in situ doped
epitaxial base layer. This suppresses avalanche multiplication as well as band-to-band tunneling, making the devices
less vulnerable to reliability concerns (This is true also for
epitaxial-base Si homojunction bipolar transistors, which
never took off as a mainstream device before the rapid emergence of SiGe HBTs). Lateral scaling of emitter width has
no first-order impact on avalanche multiplication. However,
overall shrinkage of lateral dimensions may lead to increased
multiplication, as the lateral overlap of highly doped regions
is enhanced. For instance, the overlap of extrinsic base and
diffused emitter and the overlay of extrinsic base and SIC
region can cause a local increase of the multiplication rate.
The effect of vertical scaling on avalanche multiplication
was explored with three different levels of SIC doses implemented on IBM’s 300-GHz SiGe HBTs (identical set of devices as used in Section II-C). Multiplication factor
was measured as a function of
for one control device and
two scaled devices with increased SIC doses, as illustrated in
exhibits a clear
Fig. 12. As is obvious from the plot,
increase with SIC dose, indicating enhanced avalanche multiplication rate with vertical scaling. Corresponding breakdown voltage variation is also plotted in Fig. 13 in terms of
(open-emitter B-C breakdown voltage) and
(open-base E-C breakdown voltage), which tend to decrease
with increasing multiplication factor and thus with vertical
scaling.
RIEH et al.: SCALING OF SiGe HETEROJUNCTION BIPOLAR TRANSISTORS
0
Fig. 12. Measured multiplication factor M 1 for three devices
with different levels of the SIC total implant dose. M 1 was
extracted from I values while I is fixed at 10 A.
0
Fig. 13. Measured breakdown voltages shown as a function of the
normalized SIC total implant dose.
The decreasing trend of the breakdown voltages with vertical scaling naturally establishes a tradeoff relation with the
device speed which tends to improve with scaling. Such a
tradeoff has received attention from the early stage of bipolar
device development, and, in the 1960s, Johnson proposed an
upper limit of —breakdown voltage product for Si bipolar
transistors, which was estimated to be 200 GHzV [94]. As is
apparent from Fig. 14, however, the performance of some devices, especially recent SiGe(C) HBTs, already has exceeded
such limit (note that the small amount of Ge in the base has
negligible effect on the limit). Recently, Rieh et al. [95] sug(collector doping concentragested that such limit has an
levels of modern Si-based
tion) dependence and typical
bipolar transistors would lead to a much greater value than
originally estimated.
B. Current Density and Scaling
Increased operation current density of a device is favored
for current drivability as well as speed improvement. From
the reliability perspective, however, it imposes mostly adverse effects on the device. Several types of degradations
have been reported for bipolar transistors operated under
1529
Fig. 14. Correlation between peak f and BV
for Si-based
bipolar transistors, shown along with the Johnson limit. It is clear
that recent high-speed SiGe(C) HBTs as well as some Si BJTs have
already exceeded the limit.
elevated collector current density
: base leakage current
increase [96]–[98], emitter resistance variation [96], [97],
range base current level shift [97], [98],
[99], and mid[100]. Although complicated, most of these degradations
can be attributed to the damage of Si-dielectric interface
around the emitter and the instability of the thin oxide layer
inserted at the emitter poly-mono interface. Also aggravated
is the electromigration in the metal
by the increased
lines attached to devices, potentially leading to disconnected
wiring or a shift in the operation current due to induced strain
, too,
[101]. Self-heating becomes severe with increased
resulting in junction temperature rise and the acceleration
of device degradation, as will be discussed in more detail in
Section IV-C.
Vertical scaling tends to increase the collector current
increase,
level. Both base and collector scalings promote
but by distinct mechanisms and from different aspects. Base
for a given
,
scaling generally leads to an increase in
decreases the base Gummel number.
since the reduced
In actual circuit design, however, there is no hard constraint
tuning in most cases, and preferred
level can be
for
. Hence,
increase due to
recovered by readjusting
base scaling is not quite a practical reliability issue. On the
would raise
other hand, collector scaling with increased
at peak
condition, due to the delayed onset of the
Kirk effect. Therefore, for device operations near peak
condition, raised
from collector scaling would actually
enhance the overall operation current level, leaving a device
potentially more susceptible to the reliability issues.
at peak
over
Fig. 15 illustrates the trend of
for Si-based bipolar transistors, which is princithe peak
pally driven by collector vertical scaling.
was typGHz,
ically around 1 mA m for devices with
but it was pushed up to near 20 mA m for the recent deGHz. This apparently excessive current
vices with
density, however, is still much lower than typical density for
the channel current in most advanced nMOS devices, which
is 50–100 mA m when channel conducting path width
nm is assumed. It is also noted from the trend that
of
1530
Fig. 15. Increasing trend of J
transistors.
with f for Si-based bipolar
Current per unit length I and current per unit area
compared for various generations of IBM SiGe HBT
technology. If W is reduced from 0.13 to 0.1 m for the 375-GHz
device, I increase would be substantially suppressed.
Fig. 16.
J
for epitaxial-base Si BJTs is slightly higher than that
of SiGe HBTs with a similar speed. In other words, epitaxial-base Si BJTs is slower than SiGe HBTs for a similar
, which is a clear evidence of the superior speed performance of SiGe HBTs, largely due to their smaller .
Lateral scaling leads to a slight apparent increase in , as
the relative contribution from the fringing current becomes
more pronounced. However, the most influential impact of
lateral scaling comes from the fact that the current per unit
decreases linearly with reduced emitter width.
length
Electromigration, the greatest current level-related reliability
concern for modern SiGe HBT technologies, is dictated by
, rather than , as emitter and collector currents are typically provided from the longer side of the stripes. Fig. 16
and
for various generations of IBM SiGe
compares
HBT technology. It is apparent from the plot that the increase
in the overall trends, owing
of is not as steep as that of
reduction) performed in parallel
to the lateral scaling (
is slightly steeper for
with vertical scaling. The slope of
transition from 200 to 375 GHz, since
reduction
the
PROCEEDINGS OF THE IEEE, VOL. 93, NO. 9, SEPTEMBER 2005
did not accompany the
(and
) transition. If
is reduced from 0.13 to 0.1 m for such transition, increase
is substantially suppressed, as shown in Fig. 16 as a dotted
reduction due to lateral
line. In theory, if the pace of
increase from vertical scaling,
scaling is same as that of
should remain constant over the generation [102].
C. Self-Heating and Scaling
Junction temperature rise
due to self-heating is another reliability concern related to the raised device operation
current level, since increased temperature accelerates most
is expressed as
of device degradation mechanisms. As
and dissipated power
a product of the thermal resistance
, the strategy for the suppresbecomes rather straightforward—the reduction
sion of
and
. In general,
of a device is closely
of both
related to the horizontal cross-sectional area of the device,
since a wider cross section facilitates the vertical heat dissipation from the device toward substrate [103], [104]. As
and
a result, there exists a close correlation between
for devices
lateral scaling in general. Fig. 17(a) plots
with various emitter stripe lengths
, implemented on the
IBM’s 200-GHz SiGe technology [105]. It shows a sharp
with decreasing
, as a result of the reincrease in
duced cross-sectional area for shorter devices. In contrast,
the actual increase in junction temperature exhibits an opposite trend, showing smaller junction temperature rise for
shorter devices, when constant power density for different
sizes of devices is assumed. Such trend is due to the larger
cross-sectional area-to-emitter area ratio for shorter devices,
which roughly indicates a larger heat dissipation-to-power
also results in an increase in
application rate. Scaling of
as shown in Fig. 17(b) based on thermal model [103],
scaling case due
but the variation is not as strong as the
to the relatively small change in the cross-sectional area. As
penalty for scaled devices is smaller with
scaling
the
scaling,
suppression for scaled devices is more
than
scaling case for a typical range of dipronounced for
mensional variation. Overall, lateral scaling imposes positive
impacts on devices in terms of self-heating management.
Vertical scaling is expected to have a much less impact
than lateral scaling, since it does not alter the heat
on
of vertically
dissipation path significantly. Increased
level leading
scaled devices, however, results in raised
to an increase in
, although
remains roughly unchanged. SiGe alloys exhibit substantially smaller thermal
conductivity than Si due to enhanced scattering rate of
phonons (1.41 versus 0.08 W/cmK for Si and Si Ge ,
K [106]). However, its impact on
respectively, at
of SiGe HBTs is not significant, since SiGe alloy does
not block the major heat dissipation path in the device. Note
that in bipolar transistors, heat is mostly generated in B-C
SCR where electrons lose most of their kinetic energy, and
the majority of generated heat is dissipated downward to
substrate, which path is more conductive than upward path.
RIEH et al.: SCALING OF SiGe HETEROJUNCTION BIPOLAR TRANSISTORS
1
Fig. 17. R and T for devices with (a) various emitter stripe
lengths L and (b) various emitter stripe width W . Constant
power density was assumed for various device sizes. Symbol is
measured data point and line is estimation from a thermal model.
V. SCALING RULES
A scaling rule provides a set of preferred device design
parameters and expected performance parameters for a given
scaling factor, based on requirements for proper device operation and assumed constraints. The scaling factor commonly
pertains to the lateral dimension which is typically limited by the lithography. Scaling rules for CMOS devices,
the performance of which is dictated by lateral scaling,
have been extensively developed and served as a precious
tool for the successful evolution of CMOS technologies
[107]–[109]. For bipolar transistors, the dependence on lateral scaling is less critical and their scaling rule has been
of lower interest than CMOS case. Nevertheless, there have
been appreciable efforts to establish useful scaling rules for
bipolar transistors, too, as is reviewed below.
Solomon et al. [110] proposed a bipolar scaling rule for
ECL circuits assuming constant voltage (CV) and constant
current (CI), and expected that the gate delay tends to decrease at the same rate as lateral scaling. Bellaouar et al.
1531
Table 1
Summary of Bipolar Scaling Rules [110]–[113]
[111] developed a bipolar scaling rule based on CI scheme,
but with an extended set of independent scaling factors, each
corresponding to lateral dimension, vertical dimension, and
voltage across base and collector. Rosseel et al. [112] took
a slightly different approach in developing a scaling rule for
bipolar transistors embedded in BiCMOS logic gates (which
consist of both bipolar and CMOS devices as inverter components), in which greater performance of BiCMOS gates
over CMOS gates was taken as a constraint. Raje et al. [113]
also established a scaling rule for bipolar devices employed
for BiCMOS gates, but took into account the fact that bipolar
and CMOS devices in a gate cannot be considered independently and interactions should exist between these devices in
terms of scaling. The bipolar scaling rules from these various approaches are summarized in Table 1. Despite the different constraints and approaches assumed, overall trends
suggested by these scaling rules for key bipolar parameters
are not significantly far apart. For example, a scaling factor
is expected for the gate delay, while current
of
from most scaling
density is expected to increase by
rules.
Bipolar scaling rules have taken slightly different path than
CMOS case in terms of the constraints assumed. For CMOS
scaling rules, constant electric-field (CE) [107] or relaxed
1532
(generalized) CE [111] have been widely accepted as constraints. For bipolar transistors, on the other hand, CI scaling
has been the most popular one. Another probable scaling
scheme for bipolar transistors, the constant current density
(CJ) scaling, is expected to be more susceptible to device reliability issues related to emitter periphery degradation than
CI scaling [114]. The difference in scaling constraints for
bipolar and CMOS devices stems from the different device
structures and operation principles.
It would be intuitive to compare the trends suggested by
the bipolar scaling rules to the actual data accumulated over
a long time period. The correlation between the collector
and emitter width are presented in
current at peak
Fig. 18(a), which shows compiled published data obtained
from Si-based bipolar transistors over the past two decades.
Contrary to the widely adopted CI assumption for scaling,
shows a slightly decreasing
the collector current at peak
.
trend with emitter width scaling, with a factor of
It should be noted, though, that the data points in the plot
is only 0.15,
are wide spread and the correlation factor
leaving the trend not highly decisive. Fig. 18(b) shows the
over the emitter
trend of the current density at peak
width, which is better correlated than the current trend.
is extracted, which is slower
A scaling factor of
PROCEEDINGS OF THE IEEE, VOL. 93, NO. 9, SEPTEMBER 2005
Fig. 19. Scaling trend for the gate delay . Trend equations over
W are obtained for Si BJTs and SiGe(C) HBTs separately. Si
BJTs show 2.4 longer delay than SiGe(C) HBTs for a comparable
scaling level (W ).
2
Fig. 18. Scaling trend for: (a) the collector current I at peak f
and (b) the collector current density J at peak f . Trend equations
over W are also shown, along with correlation factor R .
than expected
from most scaling rules based on CI
scaling. Recalling the fact that the current density at peak
is driven by
, this observed slower factor indicates
too fast.
the reluctance of device designers to increase
The trend of the gate delay is plotted in Fig. 19, which
for both Si BJTs and
exhibits a scaling factor of
SiGe(C) HBTs. This is a slightly lower rate than suggested
from most scaling rules. It is interesting to note
that the extracted factor is almost identical for both types of
bipolar transistors, indicating that there is no fundamental
difference in scaling mechanisms for the two kinds. However, the trend line of Si bipolar transistor is shifted up by
2.4 compared to that of SiGe(C) HBTs, which number
can be interpreted as the average performance difference between the two types of devices.
VI. SCALING LIMITS
While in CMOS the scaling is mostly limited by lateral
dimensions and doping profiles [115], [116], state-of-the-art
SiGe HBTs experience more vertical limitations due to their
design and manufacturing [117]. It is clear that the scaling of
RIEH et al.: SCALING OF SiGe HETEROJUNCTION BIPOLAR TRANSISTORS
HBTs will end at a single atom level, but the onset of scaling
limitations happens much earlier, if the technology has to
comply with the requirements of industrial mass-production
[118]. Manufacturability means that, besides the electrical
specifications, also reliability, yield, and tolerance criteria
have to be met. These additional boundary conditions favor
Si-based technologies, which rely on the well developed and
understood mechanisms of CMOS manufacturing, avoiding
exotic processing steps or materials.
The scaling limitations may be classified into four categories: 1) limitations affecting the vertical profile and the film
stacks; 2) restrictions on the lateral dimensions; 3) thermal
issues; and 4) constraints due to manufacturability.
In traditional implanted-base Si BJTs, the most prominent
vertical scaling limit was the punch through across the base
layer [119]. It usually occurs when an aggressive scaling of
the base is done without raising its doping concentration.
But the increased doping level in the base, which also
induces raised doping level at the metallurgical E-B junction,
results in a much steeper doping profile at the junction
leading to excessive band-to-band tunneling and thus to
a reduced current gain. Because SiGe HBTs are grown
with an in situ doped epitaxial base, the profile at the E-B
junction can be controlled more favorably, enabling a base
concentration that are higher at the peak and lower at the
E-B junction. Combined with the reduced base bandgap
due to the incorporation of Ge, this avoids punch through
as well as excessive tunneling currents, allowing sufficient
current gain even with base doping concentrations higher
than those of the emitter. Therefore, punch through is much
less a limitation for SiGe HBTs than it used to be for
implanted-base Si BJTs.
For SiGe HBTs, the vertical scaling limit is envisioned
to come from material- rather than electrical-related issues.
Through optimized cleaning before the LTE growth and
the inclusion of carbon into the base layer [77] to suppress
doping diffusion, the electrically active impurities could
have been constrained to very thin layers of typically less
1533
than 25 nm. A further reduction of the base thickness,
however, requires epitaxial layers in the range of some few
nanometers, which make a reliable reproduction of the film
very difficult. In addition, the solid solubility of the dopants
in the SiGe layer puts a limit to the sheet resistance of
the transistor’s three layers. Even if those problems could
be overcome, the compression of the vertical profile leads
to another problem. The small dimensions of the vertical
doping distribution require steep junction profiles, resulting
in high electric fields and therefore low breakdown voltages.
For example, a space charge region width of 3–5 nm results
in a breakdown voltage of less than 0.2 V [120]. Operating
circuits at such low voltages makes them very susceptible
to electromagnetic interference (EMI) and electrical over
stress (EOS) [121].
Limitations to the lateral scaling may go beyond the
emitter width and include the whole layout of the device.
In a SiGe HBT, the lateral scaling mostly affects the total
and the collector base capacitance
.
base resistance
as shown in (2). A low
Together with , they define
is therefore essential to achieve good control over the
intrinsic base resulting in a high gain at maximum speed.
Because of the vertical arrangement of the SiGe HBT, the
base and collector layers are buried. To contact these two
layers a laterally staggered approach is necessary in order
to arrange the C, B, and E contacts next to each other
(refer to Fig. 3). While the collector is connected to a low
ohmic buried layer, the base doping usually is extended
laterally and then merged with a source/drain type diffusion.
All three terminals may be silicided to provide the lowest
possible resistive path to the transistor’s active area. Such a
and
:
contacting scheme adds parasitic resistance to
a portion resulting from the buried layer
in the case of
and it’s diffusion to the surface
have to
breaks down to an intrinsic part
, a
be added.
,
part under the isolation between emitter and base
.
and to a link portion to the diffusion to the contact
Lateral scaling may reduce these parasitic resistances, but a
complete elimination is impossible due to the need to bring
the terminals to the surface.
As outlined earlier, electromigration and EOS also set a
limit to the minimal dimensions of the contacts, which have
become a major part of the transistors layout. Besides the
linear reduction of the dimensions, scaling imposes additional stress on the emitter contact because smaller emitter
widths have a higher fringing to area current ratio, which
leads to an increase of the current density and therefore to
an earlier failure of the contact.
As described in Section IV-C, the reduced trench-enclosed
area, paired with low thermal conductivity, may cause the
junction to overheat and to fail. Self-heating has not been
one of the limiting factors in the scaling of SiGe HBTs so
far, but it may become crucial since the silicon volume of
and
the C-B junction needs to be reduced to control
thus gain speed. With a reduction of the vertical profile as
well as the transistor’s width and length, the heat absorbing
volume shrinks in all three dimensions leading to an increase
1534
in the effective thermal resistance. Also the trend to higher
resulting from the relentless vertical scaling leads to even
higher power densities in the device and therefore to a further
increase of the junction temperature. Although alleviated by
a proper lateral scaling, this may emerge self-heating as one
of the vertical scaling limitations in the future.
Currently, the scaling of HBT is clearly limited by
technology and the requirements of an industrial manufacturability, which includes reliability, high, yield, and low
tolerances of the specifications [122]. In the vertical dimension, limitations arise from insufficient control of thin-film
growth parameters as well as from the tradeoff between
deposition speed and film quality [123]. The control of the
emitter profile depth also appears to be a limitation as it
causes fluctuations in collector current and therefore device
mismatch, especially for steep Ge concentration gradients
in the base. Limitations on the lateral scaling are similar to
the ones encountered in CMOS technology [115], [116].
However, as bipolar performance is modulated more by the
vertical profile than its lateral dimensions, the limitations
on lateral scaling from a manufacturability point of view
is less severe than those for CMOS devices, which suffer
from device mismatch due to lateral dimension variations.
Instead, one of the biggest problems in SiGe HBT manufacturing is a close contacting of the transistor’s E, B, and
C areas. Lithography [124], reproducibility of the targeted
geometry, and film quality currently prevent a drastic reduction of the layout and its associated parasitic parameters.
In addition, the interconnecting metal lines with their tight
ground rules also prevent too aggressive lateral scalings,
if the transistor has to be reliably manufactured with high
yield.
VII. CONCLUSION
In this paper, the impacts of scaling on SiGe HBTs have
been overviewed with an extensive data set collected from
literature and recent experiments on IBM SiGe HBTs. It is
shown that the scaling, both vertical and lateral, has mainly
beneficial effects on key device performances such as speed
and noise. On the other hand, device reliability is expected
to be a growing concern for scaled devices due to increased
electric field and operation current density, which lead to enhanced avalanche multiplication and raised junction temperature. Bipolar scaling rules were reviewed, indicating that the
scaling factors predicted from reported scaling rules roughly
follow the actual measured trend, if not precisely. Overview
of scaling limits suggests bipolar technology has not reached
an ultimate limit yet, although manufacturability consideration increasingly imposes practical limits. Looking back,
bipolar scaling seemed to have reached the limit repeatedly
in the course of technology evolutions, but they were overcome with material and structural innovations that opened
new spaces for further performance improvement. As it is
apparent the bipolar scaling has not reached the physical fundamental limit yet, the efforts for scaling and the march for
performance improvement will continue for the foreseeable
future.
PROCEEDINGS OF THE IEEE, VOL. 93, NO. 9, SEPTEMBER 2005
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Jae-Sung Rieh (Senior Member, IEEE) received
the B.S. and M.S. degrees in electronics engineering from Seoul National University, Seoul,
Korea, in 1991 and 1995, respectively, and the
Ph.D. degree in electrical engineering from the
University of Michigan, Ann Arbor, in 1999.
From 1999 to 2004, he was with IBM Semiconductor R & D Center, Hopewell Junction,
NY, where he was involved in the development
of high-speed SiGe BiCMOS technologies. In
2004, he joined the department of electronics
engineering, Korea University, Seoul, Korea, where he is currently an
assistant professor. His major interest lies in the Si-based RF devices and
their system applications.
Dr. Rieh is a recipient of 2005 IBM Faculty Award and a corecipient of
the 2002 IEEE EDS George E. Smith Award.
1538
David Greenberg (Member, IEEE) received the
B.S. degree in electrical engineering at Columbia
University, New York, under a Pulitzer scholarship in 1988 and the M.S. and Ph.D. degrees at
the Massachusetts Institute of Technology, Cambridge, under Hertz and Intel Foundation fellowships in 1990 and 1994, respectively.
He is a semiconductor device researcher
working in advanced RF technology development and assessment. During his graduate
school tenure, he explored the use of GaAs and
InP-based FETs for power and laser driver applications and completed two
summer internships at AT&T Bell Labs performing software and board
design for ISDN and DSP chipsets. He joined the IBM T. J. Watson Research Center, Yorktown Heights, NY, as a Research Staff Member in 1995,
where he has played key roles in the development of several generations
of SiGe BiCMOS and RF CMOS technologies, including device design
and evaluation, power transistor development, noise measurement and
modeling, technology versus application assessment, and interfacing with
customer circuit design groups. He is an author or coauthor of seven issued
patents and over 35 technical papers.
Dr. Greenberg is a Member of Tau Beta Pi.
Andreas D. Stricker (Member, IEEE) was
born in Bern, Switzerland, in February 1965.
He received the M.S. degree in applied physics
from the University of Bern in 1992, where he
worked in the field of laser interaction with solid
state materials, and the Ph.D. degree from the
Integrated Systems Laboratory, Swiss Federal
Institute of Technology, Zurich, in 2000, working
on on-chip ESD protection circuits as well as
their development using process and device simulations. He published his thesis, “Technology
Computer Aided Design of ESD Protection Devices,” in 2000.
He is currently with the IBM Systems and Technology Group, Burlington,
VT, where he joined the Device Development and Modeling Department.
Dr. Stricker won the IEEE Electron Device Society’s George Edward
Smith Award in 2002 together with other members of IBM’s SiGe technology team for the development of the first 200-GHz hetero bipolar transistor in a manufacturable technology.
Greg Freeman (Senior Member, IEEE) received
the Ph.D. degree in electrical engineering from
Stanford University, Stanford, CA, in 1991.
Since 1991, he has been with IBM Microelectronics, Hopewell Junction, NY. He has worked
in a variety of areas at IBM, including characterization, yield diagnostics, high-speed SiGe
HBT device characterization and design, and
FET design. He is currently a Senior Technical
Staff Member, managing a department with
responsibility for designing high performance
devices for IBM’s 65-nm SOI technology. He is an author or coauthor of
four patents and over 50 technical papers. His research interests are in the
field of high-performance device design and application.
PROCEEDINGS OF THE IEEE, VOL. 93, NO. 9, SEPTEMBER 2005