HUF76629D3ST_F085
N-Channel Logic Level UltraFET® Power MOSFET
100V, 20A, 52mΩ
D
Features
„ Typ rDS(on) = 41mΩ at VGS = 10V, ID = 20A
„ Typ Qg(tot) = 39nC at VGS = 10V, ID = 20A
G
„ UIS Capability
„ RoHS Compliant
„ Qualified to AEC Q101
S
Applications
„ Automotive Engine Control
„ Powertrain Management
„ Solenoid and Motor Drivers
„ Distributed Power Architectures and VRM
„ Primary Switch for 12V Systems
MOSFET Maximum Ratings TJ = 25°C unless otherwise noted
Symbol
VDSS
Drain to Source Voltage
VGS
ID
EAS
PD
Parameter
Ratings
100
Units
V
±16
V
Gate to Source Voltage
Drain Current - Continuous (VGS=10) (Note 1)
TC = 25°C
20
Pulsed Drain Current
TC = 25°C
See Figure4
Single Pulse Avalanche Energy
(Note 2)
231
A
mJ
Power Dissipation
150
W
Derate above 25oC
1
W/oC
TJ, TSTG Operating and Storage Temperature
RθJC
Thermal Resistance Junction to Case
RθJA
Maximum Thermal Resistance Junction to Ambient
-55 to + 175
oC
1
oC/W
52
oC/W
(Note 3)
Package Marking and Ordering Information
Device Marking
HUF76629D3ST
Device
Package
HUF76629D3ST_F085 D-PAK(TO-252)
Reel Size
13”
Tape Width
12mm
Quantity
2500 units
Notes:
1: Current is limited by bondwire configuration.
2: Starting TJ = 25°C, L = 1.8mH, IAS = 16A, VDD = 100V during inductor charging and VDD = 0V during time in avalanche
3: RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder
mounting surface of the drain pins. RθJC is guaranteed by design while RθJAis determined by the user's board design. The maximum rating
presented here is based on mounting on a 1 in2 pad of 2oz copper.
©2013 Fairchild Semiconductor Corporation
HUF76629D3ST_F085 Rev. C1
1
www.fairchildsemi.com
HUF76629D3ST_F085 N-Channel Logic Level UltraFET ® Power MOSFET
April 2013
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Drain to Source Leakage Current
IGSS
Gate to Source Leakage Current
ID = 250μA, VGS = 0V
VDS = 100V,
VGS = 0V
100
-
-
V
-
-
1
μA
TJ = 25oC
TJ = 175oC(Note 4)
-
-
1
mA
-
-
±100
nA
1.0
1.6
3.0
V
-
41
52
mΩ
-
102
128
mΩ
47
55
mΩ
115
135
mΩ
VGS = ±16V
On Characteristics
VGS(th)
rDS(on)
Gate to Source Threshold Voltage
Drain to Source On Resistance
VGS = VDS, ID = 250μA
ID = 20A,
VGS= 10V
ID = 20A,
VGS= 4.5V
TJ = 25oC
TJ = 175oC(Note 4)
TJ = 25oC
TJ = 175oC(Note 4)
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Rg
Gate Resistance
f = 1MHz
Qg(ToT)
Total Gate Charge
VGS = 0 to 10V
Qg(th)
Threshold Gate Charge
VGS = 0 to 2V
Qgs
Gate to Source Gate Charge
Qgd
Gate to Drain “Miller“ Charge
-
VDS = 25V, VGS = 0V,
f = 1MHz
VDD = 50V
ID = 20A
-
1280
-
pF
-
214
-
pF
-
33
-
pF
-
2.5
-
Ω
-
39
43
nC
-
2.3
3
nC
-
3.5
-
nC
11
-
nC
Switching Characteristics
ton
Turn-On Time
-
-
27
ns
td(on)
Turn-On Delay Time
-
7
-
ns
tr
Rise Time
td(off)
Turn-Off Delay Time
tf
toff
-
12
-
ns
-
38
-
ns
Fall Time
-
5
-
ns
Turn-Off Time
-
-
47
ns
ISD = 20A, VGS = 0V
-
-
1.25
V
ISD = 10A, VGS = 0V
-
-
1.0
V
IF = 20A, dISD/dt = 100A/μs,
VDD=80V
-
77
99
ns
-
221
305
nC
VDD = 50V, ID = 20A,
VGS = 10V, RGEN = 8.2Ω
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Voltage
Trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
Notes:
4: The maximum value is specified by design at TJ = 175°C. Product is not tested to this condition in production.
HUF76629D3ST_F085 Rev. C1
2
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HUF76629D3ST_F085 N-Channel Logic Level UltraFET ® Power MOSFET
Electrical Characteristics TJ = 25°C unless otherwise noted
25
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
0.2
0.0
0
25
50
75
100
125
150
TC, CASE TEMPERATURE(oC)
VGS = 10V
15
VGS = 4.5V
10
5
0
25
175
50
75
100
125
TC, CASE TEMPERATURE(oC)
150
175
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
Figure 1. Normalized Power Dissipation vs Case
Temperature
NORMALIZED THERMAL
IMPEDANCE, ZθJC
20
DUTY CYCLE - DESCENDING ORDER
1
D = 0.50
0.20
0.10
0.05
0.02
0.01
0.1
PDM
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TC
SINGLE PULSE
0.01
-5
10
-4
10
-3
-2
-1
0
10
10
10
t, RECTANGULAR PULSE DURATION(s)
1
10
10
Figure 3. Normalized Maximum Transient Thermal Impedance
1000
IDM, PEAK CURRENT (A)
VGS = 10V
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
100
175 - TC
I = I2
150
SINGLE PULSE
10
-5
10
-4
10
-3
-2
-1
10
10
10
t, RECTANGULAR PULSE DURATION(s)
0
10
1
10
Figure 4. Peak Current Capability
HUF76629D3ST_F085 Rev. C1
3
www.fairchildsemi.com
HUF76629D3ST_F085 N-Channel Logic Level UltraFET ® Power MOSFET
Typical Characteristics
100
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
100
100us
10
1ms
1
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(on)
0.1
1
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
10ms
100ms
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
IS, REVERSE DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
TJ = 175oC
1
TJ = -55oC
2
3
4
VGS, GATE TO SOURCE VOLTAGE (V)
10
100
VGS = 0 V
10
TJ = 175 oC
TJ = 25 oC
1
0.1
0.2
5
0.4
0.6
0.8
1.0
1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 7. Transfer Characteristics
Figure 8. Forward Diode Characteristics
80
50
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
1
100
10
0
0.1
Figure 6. Unclamped Inductive Switching
Capability
30
TJ = 25oC
0.01
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
VDD = 5V
20
STARTING TJ = 150oC
tAV, TIME IN AVALANCHE (ms)
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
40
STARTING TJ = 25oC
10
1
0.001
300
Figure 5. Forward Bias Safe Operating Area
50
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
60
VGS
10V Top
8V
6V
5V
4.5V
4V Bottom
40
20
80μs PULSE WIDTH
Tj=25oC
0
0
1
2
3
4
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
VGS
10V Top
8V
6V
5V
4.5V
4V Bottom
20
10
0
0
5
Figure 9. Saturation Characteristics
HUF76629D3ST_F085 Rev. C1
40
80μs PULSE WIDTH
Tj=175oC
1
2
3
4
VDS, DRAIN TO SOURCE VOLTAGE (V)
5
Figure 10. Saturation Characteristics
4
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HUF76629D3ST_F085 N-Channel Logic Level UltraFET ® Power MOSFET
Typical Characteristics
ID = 20A
3.0
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
rDS(on), DRAIN TO SOURCE
ON-RESISTANCE (mΩ)
200
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
2.4
150
TJ = 175oC
1.8
100
1.2
50
0.6
TJ = 25oC
0
0
2
4
6
8
VGS, GATE TO SOURCE VOLTAGE (V)
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE(oC)
200
Figure 12. Normalized Rdson vs Junction
Temperature
1.4
1.2
VGS = VDS
ID = 250μA
1.2
ID = 1mA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
ID = 20A
VGS = 10V
0.0
-80
10
Figure 11. Rdson vs Gate Voltage
1.1
1.0
1.0
0.8
0.9
0.6
0.4
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE(oC)
0.8
-80
200
Figure 13. Normalized Gate Threshold Voltage vs
Temperature
VGS, GATE TO SOURCE VOLTAGE(V)
Ciss
1000
Coss
100
f = 1MHz
VGS = 0V
10
0.1
Crss
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
100
Figure 15. Capacitance vs Drain to Source
Voltage
HUF76629D3ST_F085 Rev. C1
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
200
Figure 14. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
10000
CAPACITANCE (pF)
PULSE DURATION = 80μs
DUTY CYCLE = 0.5% MAX
10
ID = 20A
8
VDD = 40V
6
VDD = 50V
VDD = 60V
4
2
0
0
10
20
30
Qg, GATE CHARGE(nC)
40
Figure 16. Gate Charge vs Gate to Source
Voltage
5
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HUF76629D3ST_F085 N-Channel Logic Level UltraFET ® Power MOSFET
Typical Characteristics
tm
tm
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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THEREIN, WHICH COVERS THESE PRODUCTS.
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As used here in:
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and (c) whose failure to perform when properly used in accordance with
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expected to result in a significant injury of the user.
2.
A critical component in any component of a life support, device, or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
effectiveness.
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Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative / In Design
Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
Preliminary
First Production
Datasheet contains preliminary data; supplementary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
notice to improve design.
No Identification Needed
Full Production
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.
Obsolete
Not In Production
Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.
Rev. I64
HUF76629D3ST_F085 Rev. C1
6
www.fairchildsemi.com
HUF76629D3ST_F085 N-Channel Logic Level UltraFET ® Power MOSFET
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