Analog Circuits for CCD and IR Array Detectors
Bruce Atwood
Imaging Sciences Laboratory, Department of Astronomy
The Ohio State University, 174 West 18th Ave., Columbus OH 43210-1106
Abstract
Despite the advances in digital signal processing, the analog circuits which amplify and define the bandwidth of the low
level signals from CCD and IR array detectors are a critical element in obtaining the best possible signal-to-noise-ratio.
The choice of components and topology for these front-end circuits is discussed, including the effects of input voltage
and current noise density, coupling strategies, shield driving, physical layout, and grounding. The signal chain use in
Imaging Sciences Laboratory instruments is presented as an interpretation of these considerations.
1. Introduction
While the trend in electronics is very strongly in the direction of processing signals digitally, as shown by the almost
complete conversion of electronics engineers into C programmers for digital signal processors, it is still necessary to
take great care with the analog signal from the time it leaves a detector until it arrives at the analog to digital converter
(ADC). Herein I explain the choices made in the design of the analog chain that carries the signal from the detector to
the ADC in the Imaging Sciences Laboratory’s (ISL) CCD and IR array imaging systems.
2. The Detector and its Signal
Modern CCD and IR array detectors sense light by the photo generation of a hole-electron pair in a semiconductor. The
electric field in the semiconductor is controlled so that the electrons are collected in a potential well while the holes are
allowed to find a harmless electron with which to recombine. The packet of electrons that corresponds to the light
detected by a pixel is converted to a voltage signal by transferring it to a capacitor. The signal is then the change in
voltage on the capacitor caused by the addition of the photo-generated electrons.
The nearly infinite DC impedance of the capacitor is buffered by an amplifier integrated into the detector. The value of
the capacitor, the gain of the amplifier, and the charge of the electron combine to produce a signal at the output of the
detector of a few micro-volts per electron. Two types of noise contaminate this signal. The first, normally called KTC
noise, is the unavoidable uncertainty in the final voltage on a capacitor when any circuit is used to pre-charge it, and
amounts to about 100 electrons RMS for typical temperatures and capacitances. The second noise is from the amplifier
integrated into the detector. This noise is white at high frequencies with a voltage density of typically 20 nV/%Hz and
rises approximately as T-" where T is the frequency and " is a constant near unity, below a corner frequency, typically
10 to 100 kHz . The output impedance of the on detector amplifier is of the order of 1 to 20 K ohms, and in the case of
CCD's the DC level is 10 to 20 volts above the practical ground point.
3. Detector Cabling
For improved modularity, flexibility in component selection, and to support our grounding strategy we do not include
any electronics components in the detector Dewar. In addition all circuits that connect to the detector are located on a
single board, the Clock-Bias-Board (CBB), which has a robust ground plane. All connections between the CBB and the
detector Dewar are made with a cable having either 37 (CCD or NICMOS) or 62 (Aladdin) miniature coaxial cables
with an overall shield. The coaxial cables provide clean connection for the clock, bias, and signal connections to the
detector. The shields for the clock and bias connections are connected at both the CBB and the Dewar end, and, in
addition shielding their respective signals, form a ground connection that has a very low impedance at all important
frequencies. The shields for the signal leads are connected at only the CBB end.
For some detectors, most notably the Thomson THX 7897, the time constant formed by the output impedance of the
detector and the coaxial cable capacity is unacceptably long. A shield drive circuit is included to force the shield to
follow the signal level. Since both ends of the capacitance of the coaxial cable have the same potential, the signal does
not have to charge the capacitance and the capacitance is effectively nulled. The shield continues to be effective since
the current produced by any outside field flows through the low impedance shield drive and does not couple into the
signal. Noise from the shield drive is tightly coupled into the signal but a very low noise amplifier can be used because
its input is the very low impedance summing junction of the first gain stage.
4. The DC Offset
Even though the fad in analog electronics is towards ever lower voltage swings, following the trend towards ever lower
digital voltage levels, it appears that a rich selection of components designed to overate over a ±10 volt signal range will
continue to be available for the foreseeable future. The choices for components designed to include the 10 to 20 volt DC
level from a CCD are much more limited and require either that devices with markedly inferior specifications be used
just for their "high voltage" capability or that additional, also perhaps sub-optimal, circuitry be used just to subtract off
the DC level. We find that, with the proper choice of capacitor, the traditional method of changing the DC level of a
signal, AC coupling, is entirely satisfactory and does not require any additional circuitry. Several factors must be
included in selecting the capacitor and the resistor used to establish the time constant for charging the capacitor to the
CCD DC level. The first is the photometric error introduced when the mean signal level changes producing an
exponential tail at the output of the coupling capacitor. The worst error is introduced when the signal changes from
either a long (several time constants) string of bright pixels to all dark pixels, or vice versa. The problem arises from the
fact that the signal is extracted as a difference over a finite time and is therefore sensitive to the slope of the voltage on
the capacitor. If the AC coupling has a time constant t and the signal processing differences over a time J, the error is
less than J/2•t times the maximum signal. (The two arises from the fact that the signal is present for only about ½ the
total pixel time). For typical J's of 2x10e-5 sec and practical t's of 1 sec the error amounts to a base line shift of only -1
electron immediately after a scene averaging 100,000 electrons.
The noise current from the first off-detector stage of amplification must flow through the coupling capacitor to the output
impedance of the on-detector amplifier. For some choices of first stage amplifier the acceptable level of voltage noise
produced by this noise current could set a minimum value for the coupling capacitor. For one of the best choices of OPAmp from the standpoint of its voltage noise, the OP-37 family, the relatively high noise current still does not require an
impractically large coupling capacitor in order to keep the noise from the noise current at insignificant levels.
Hysteresis, commonly called dielectric absorption, in the coupling capacitor would lead to photometric errors. The
errors produced by the hysteresis of capacitors with either Teflon™ or polystyrene dielectrics is negligible.
5. First Gain Stage
In a well designed system the noise introduced by the first gain stage is much less than the noise in the signal, and the
first stage has enough gain so that the noise introduced by subsequent stages is also negligible. There was a time when
front end amplifiers with the required noise, gain, and input impedance demanded careful design with discrete
components. For several years now there have been easy to use integrated circuit operational amplifiers, OP-Amps,
with excellent noise and bandwidth. The graph below shows the noise characteristics for a selection of OP-Amps
familiar to the author. It is interesting to note that they group almost exclusively into two categories, those with bipolar
input transistors and input noise powers near 2•10-21 W and those with field effect transistors with noise powers of 5•1026
W. In order for the input noise of an amplifier to have minimum effect on the signal-to-noise ratio (SNR), the noise
input impedance of the amplifier, that is the input noise voltage density divided by the input noise current density, should
be close to the output impedance of the detector. Unfortunately all the devices with very low noise powers have noise
impedances much higher than the 1 to 20 K ohm output impedances of detectors. The lowest noise amplifier would be
formed with transformer coupling between the detector and the input stage, the turns ratio of the transformer chosen to
be the square root of the
ratio of the output
impedance to the noise
impedance. Transformers
have their own problems
1E-7
1E+09
(although the transformer
would be a natural way to
1E+08
remove the DC component
of the signal) and fortunately
1E+07
1E-8
(?) the noise level from
1E+06
CCDs and IR arrays is high
enough that an optimal
1E+05
amplifier is not needed. As
1E-9
mentioned above, the
1E+04
typical voltage noise density
of the signal from a detector
1E+03
is 20 nV//Hz and since the
noise
of the noises add in
1E-10
1E+02
quadrature,
the total noise
1E-16
1E-15
1E-14
1E-13
1E-12
1E-11
from detector and front end
Noise Current Density (A/Hz^0.5)
with 4 nV//Hz is only 20.4
nV//Hz. A very small
Noise Voltage
Noise Impedance
2x10^-21 Watts
5x10^-24 Watts
noise penalty to pay.
Input Noise Impedance (Ohms)
Noise Voltage Density (V/Hz^0.5)
OP-Amps of the World
Figure 1: Voltage noise densities as a function of current noise density for an arbitrary For detectors with output
selection of OP-Amps. The Noise Impedance, voltage noise divided by current noise, is
impedances less that about
also plotted. Note that the noise power densities form two reasonably well defined groups. 6k ohms, which includes
most CCDs and IR arrays,
the lowest noise OP-Amp that has a bandwidth allowing readout rates of 100 k pixels/second is the OP37. For devices
with higher output impedances, such as the Thomson devices with their on-detector active loads, the OPA637 works
better and has a wider bandwidth. In any case the gain determining resistors must be of low enough value that their
Johnson noise is not significant.
6. Second Stage
The best SNR is obtained when the signal is amplified to use the full dynamic range of the analog chain as early as
possible. For CCDs with typical on-detector conversion gains of 1 micro volts/electron a voltage gain of 40 or more is
needed to amplify the peak detector signal to several volts. The OP-Amps with the best noise performance do not have a
large enough gain-bandwidth products to operate with a gain of 40, and two stages are required. In addition, the low
values for the gain determining resistors, required for the best noise performance, limit the voltage swing at the output of
the first stage. The second stage can use larger value gain determining resistors and therefore drive the output to the full
dynamic range.
7. Post Amplifier
Hegyi and Burrows1 have shown that to maximize the SNR in a pixel, independent of the value of other pixels, the signal
must be extracted with a sampling function, S(t), having a Fourier Transform (FT) given by
SOF(T)'
ṽ(T)
N(T) 2
(1)
where ṽ(T) is the FT of the signal component of the voltage output from the detector, #N(T)#2 is the power spectrum
of the noise from the detector and the subscript OF indicates optimal filter. As described above the signal from CCDs
and IR arrays is well modeled by 1/f noise. For high pixel rates, where the short time available for processing each pixel
limits the low frequency response of the signal processing system, the noise is nearly white and the optimal filter has the
same functional form as the signal. When the noise is white the simple differential averager (SDA) or correlated
double sampling (CDS), first applied in astronomical CCD system by Marcus2, is the optimal filter. As the integration
time used by the SDA is increased the system becomes sensitive to frequency components where the noise power is
rising faster than the signal power and increasing the integration time does not improve the SNR. In the transition
region some small gain in SNR can be made by using a SDA, which instead of having a fixed gain of -1 before t=0 (the
moment when the charge is transferred to the output) and +1 after t=0, is tapered in time, giving maximum weight to
times near zero and less weight as the differencing is done farther from t=0, where the correlation of the noise is less.
Unfortunately the SNR increases, even in the white noise region, only as the square root of integration time. The
additional gain from increasing the integration time in the transition region is truly marginal. What can make significant
improvement in SNR is to shift the signal power to frequencies where the amplifier noise is white as in the Skipper3 type
readout. The result is that SDA or multiple SDA (Skipper) signal processing is always very nearly optimal.
We have implemented the SDA with a true resetable integrator, using four analog switches (HI201HS) to select either
polarity of integration, hold, or integrator reset. By connecting the analog switches directly to the summing junction of
the integrator a major source of non-linearity is removed since the both the input and output of the analog switch operate
very near ground and therefore have nearly constant "on-resistance".
While the on-resistance of the analog switches is low, it is not zero and the reset of the integration capacitor can only be
as rapid as the time constant given by the product of the on-resistance and the integrator capacitance. For the system to
operate with full sixteen bit performance the reset switch must be on for at least 11 time constants in order to reset from
full scale. It is therefore helpful to keep the integration capacitor as small as possible consistent with the DC errors of the
circuit to minimize the reset time.
The OP-Amp used for the integrator must be unity-gain stable, have adequate slew rate to follow full scale signals in the
shortest anticipated integration time, have enough open loop gain to give good linearity, and have reasonably low voltage
and current noise.
The envelope of the frequency response of the SDA is equivalent to a 6 dB/octave high pass filter and a 6 dB/octave
low pass filter. Therefore, the track and hold amplifier need only follow the relatively slow signal coming from the
integrator and does not require a slew-rate or bandwidth adequate for the signal entering the integrator. The Track and
Hold amplifier does require good feed-through isolation in the hold mode to allow the integrating capacitor to be reset
while the ADC is processing the signal.
8. Analog to Digital Converter
Since the integration time required to get good signal to noise from a detector is several times the ADC conversion time
a single ADC can service several analog channels. Fast high precision analog to digital converters, and if included their
associated sample and hold amplifiers, have high noise bandwidth. It is therefore necessary that any circuit needed to
multiplex several analog channels into an ADC have very low voltage noise density. If the ADC(s) are located on a
separate ground plane from the preceding analog circuitry it is very helpful to have differential input on the ADC
modules.
9. The ISL Signal Chain
For CCDs with up to four channels and for the four channel NICMOS III array we developed an analog signal chain
with gain stages located on the detector electronics board, CDS circuits on a post-amplifier board, and an ADC board
with four sample and hold amplifiers multiplexed into a single 500 KHz 16 bit ADC. It was clear that this packaging
would be cumbersome if applied to arrays with significantly more outputs, and when we installed an ALADDIN InSb
Figure 2: Simplified schematic of ISL signal chain configured for CCD type detectors.
array with 16 working outputs in our MOSAIC camera we developed a small module with all the circuitry necessary to
support a signal chain for either a multiplexed device like Aladdin or NICMOS, or a CCD. The module, designed to be
used as one of up to 32 daughter boards on the Clock-Bias-Board includes gain stages, a CDS integrator which can be
used a single slope integrator for devices like Aladdin where the subtraction to remove KTC noise must be done
digitally, a sample and hold, and an output multiplexer to allow from 1 to 32 boards to drive a single ADC. The board
was designed to be mounted on a relatively fine pitch of 0.45 inches to allow good packing density. A detector
electronics board has been developed which, in addition to the circuitry necessary to drive an array, accommodated up to
32 analog channels on a 9U wide board or 8 channels on a 6U board. A slightly simplified schematic of the board in its
CCD configuration is shown in figure 2. For use with Aladdin arrays the input coupling capacitor is shorted and the
Figure 3 Photograph of the ISL signal chain daughter-board configured for CCDs.
Included are gain stages, CDS
circuits, a sample and hold and an output multiplexer. The board is designed to be mounted on 0.45" centers for multichannel systems.
second gain stage is used as a buffer to drive the low end of the gain setting resistor to subtract off the DC level from the
detector. The shield drive circuit is used for arrays such as the Thomson THX 7897 where the capacity of the shielded
cable would make the bandwidth unacceptably low. Figure 3 is photograph of the component side of the board. The
board is of six-layer construction: two signal planes, two ground planes and two power planes. The signal planes are
located on the outside with a ground plane directly below. Full ground and power planes combined with substantial
bypassing provides very low impedance power supplies for all circuits on the board while the use of on-board threeterminal regulators minimizes channel-to-channel cross-talk. . Connections to the Clock Bias board are via two singlerow 20-pin headers. Seventeen of the 40 pins are devoted to ground connections to insure that the ground system for
signal processing is very close to the ground system where the detector drive signals are generated.
10. References
1. Hegyi,D.J., Burrows,A.(1980). Astron. J. v85 1421
2. Steven Marcus, KPNO Internal Report 73, 1978
3. Janesick, James et.al. in CCDs In Astronomy, Astronomical Society of the Pacific Conference Series, V8,
1989, George H. Jacoby Ed,