III-V Integrated Circuit
Fabrication Technology
Shiban Tiku
Dhrubes Biswas
III-V Integrated Circuit
Fabrication Technology
III-V Integrated Circuit
Fabrication Technology
Shiban Tiku
Dhrubes Biswas
Published by
Pan Stanford Publishing Pte. Ltd.
Penthouse Level, Suntec Tower 3
8 Temasek Boulevard
Singapore 038988
Email: editorial@panstanford.com
Web: www.panstanford.com
British Library Cataloguing-in-Publication Data
A catalogue record for this book is available from the British Library.
III–V Integrated Circuit Fabrication Technology
Copyright © 2016 by Pan Stanford Publishing Pte. Ltd.
All rights reserved. This book, or parts thereof, may not be reproduced in any form
or by any means, electronic or mechanical, including photocopying, recording
or any information storage and retrieval system now known or to be invented,
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For photocopying of material in this volume, please pay a copying fee through
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ISBN 978-981-4669-30-6 (Hardcover)
ISBN 978-981-4669-31-3 (eBook)
Printed in the USA
Contents
Preface
xxiii
Acknowledgmentsxxvii
1.
Semiconductor Basics
1.1Introduction
1.1.1 GaAs Device Applications
1.2
GaAs Crystal Structure
1.3
Bonding in III–V Semiconductors 1.3.1 Bonding in a Doped Crystal
1.4
Energy Band Structure
1.4.1 Band Structure and Mobility 1.4.2 Free Carrier Concentration and
Fermi Level
1.4.3 Energy Levels in Doped Semiconductors
1.4.4 Impurities in GaAs
1.4.4.1 Specific impurities
1.5
Crystal Defects
1.5.1 Point Defects
1.5.2Dislocations
1.5.3 Other Defects
1.6
Other Properties
1
1
2
3
8
9
9
13
14
17
20
22
23
24
25
27
27
2. GaAs Devices
31
2.1
p–n and Metal–Semiconductor Junctions 31
2.1.1 p–n Junction Physics
31
2.1.1.1
I–V characteristics 33
2.1.1.2 Space charge and junction
capacitance36
2.1.2 Metal–Semiconductor Junctions
38
2.1.2.1 Junction physics
39
2.1.2.2 Junction characteristics
43
2.2MESFETs
45
2.2.1 Basic MESFETs 45
2.2.2 Low-Noise FETs
50
2.2.3 FETs for Digital Logic Circuits
51
vi
Contents
2.3
HEMTs and PHEMTs
52
2.3.1 Device Operation
54
2.4
Bipolar Junction Transistors
54
2.4.1 Phenomenological Description of
the BJT
55
2.4.2 Current–Voltage Characteristics
of a BJT
60
2.5
HBT Principles of Operation
61
2.5.1 Basic Transport Equations
62
2.5.2 Current Gain and Injection Efficiency
63
2.5.3 Figures of Merit for HBTs
65
2.6
PIN Diodes
66
2.7IMPATT 68
2.7.1 Read-Type IMPATT
69
2.8
Gunn Diodes
69
2.9MOSFET
70
2.9.1Metal–Insulator–Semiconductor
Devices71
2.9.2
I–V Characteristics
73
2.10 Remarks on Applications
76
3. Phase Diagrams and Crystal Growth of Compound
Semiconductors79
3.1
Phase Diagrams
79
3.1.1Introduction
79
3.1.2 Phase Diagram Types
80
3.1.2.1 Isomorphous phase diagram
81
3.1.2.2 Eutectic diagrams
81
3.1.2.3 Peritectic diagrams
82
3.1.3 Congruent Transformation
83
3.2
Crystal Growth
84
3.2.1 Starting Materials and Compounding
Method85
3.2.2 Single-Crystal Growth
86
3.2.2.1 Bridgman/gradient freeze
technique87
3.2.2.2Liquid-encapsulated
Czochralski method
88
3.2.2.3 Vertical boat and vertical
gradient freeze methods
89
Contents
3.3
3.2.2.4 Vapor pressure–controlled
Czochralski method
3.2.3 InP Crystal Growth
Doping and Resistivity Control
3.3.1 n- and p-Type Crystals
91
91
92
94
4.Epitaxy
97
4.1
Liquid-Phase Epitaxy
98
4.2
Vapor-Phase Epitaxy
99
4.2.1 System Configuration
99
4.2.2 VPE Chemistries for GaAs
101
4.2.2.1 Substrate orientation
101
4.2.2.2 Halide process Ga–AsCl3–H2101
4.2.2.3 Hydride process
Ga–AsH3–HCl–H2 103
4.2.3MOCVD
103
4.2.3.1 Process control and
mechanisms105
4.2.3.2 MOCVD sources
110
4.2.3.3Doping
110
4.2.3.4 HBT growth 114
4.2.3.5 Volume production
115
4.2.3.6 Specific materials
117
4.2.3.7 Selective epitaxy
119
4.2.3.8 In situ monitoring of
epigrowth119
4.3
Molecular Beam Epitaxy
120
4.3.1 System Description
120
4.3.2 MBE Sources
122
4.3.2.1 RHEED intensity oscillation
123
4.3.3 Specific Materials
124
4.3.3.1AlGaAs
124
4.3.3.2InGaAs
124
4.3.3.3InGaAlAs
124
4.3.3.4 GaN and related alloys
124
4.3.4Doping
125
4.3.5 HBT Growth
126
4.3.5.1 AlGaAs HBT
126
4.3.5.2 InGaP HBT
127
vii
viii
Contents
4.4
4.5
4.6
4.3.5.3 InP HBT
4.3.5.4 GaN HBT
4.3.6 PHEMTs Atomic Layer Epitaxy
4.4.1 GaAs on Silicon Substrates
Epilayer Characterization
Concluding Remarks
5.Photolithography
5.1Introduction
5.2
Mask Making
5.3
Basics of Printing/Imaging
5.3.1 Typical Etch Photoresist Process
5.3.2 Lift-Off Photoresist Process
5.4Photoresist
5.4.1 Resolution and Contrast
5.4.2Sensitivity
5.4.3 Optical Photoresist Reaction Mechanism
5.4.4 Image Reversal of a Positive Photoresist
5.4.5 Negative Resists
5.4.6 Resolution Improvement
5.5
Physics of Photolithograpy
5.5.1Diffraction
5.6
Step and Repeat Projection Aligner
5.7
Pattern Registration
5.8
Resist Processing
5.8.1 Prebake Dehydration
5.8.2 Adhesion Promoter
5.8.3 Resist Coating
5.8.4 Soft Bake
5.8.5Exposure
5.8.6 Standing Waves and Other
Interference Effects
5.8.7Developing
5.8.8De-scum
5.8.9Postbake
5.8.10Stripping
5.9
Electron Beam Lithography
5.10 X-Ray Lithography
5.11 Process Monitoring
127
128
128
129
130
132
132
137
137
138
139
143
143
145
147
148
149
149
150
152
152
152
156
156
157
157
157
158
158
159
160
162
163
163
163
164
165
166
Contents
6.
5.11.1 Optical Systems
167
5.11.2SEM
167
5.11.3 Advanced Photolithography
Techniques168
Wet Etching, Cleaning, and Passivation
169
6.1Introduction
169
6.1.1 Wet Etch Advantages
170
6.1.2 Wet Etch Disadvantages
170
6.2
GaAs Etching Basics
171
6.2.1Mechanism
173
6.3
GaAs Etch Chemical Systems
175
6.3.1 Hydrogen Peroxide–Based Etches
176
6.3.1.1H2SO4:H2O2:H2O system
176
6.3.1.2H3PO4:H2O2:H2O system
6.3.1.3 Citric acid system (C3H4(OH)
(COOH)3 H2O:H2O2:H2O)177
6.3.1.4 Ammonia peroxide system
177
(NH4OH:H2O2:H2O) 6.3.1.5 HCl-based systems 178
6.3.2 Special Etches
178
6.3.2.1 Polishing etches
178
6.3.2.2 Crystallographic etches
179
6.3.3 Wet Etches 179
6.3.3.1 InP 179
6.3.3.2InGaP
179
6.3.3.3InGaAs
180
6.3.4 Wet Etching of GaN/AlN
181
6.3.5 Etching of Other Materials
181
6.4
Wet Etching in Production
181
6.4.1 Wet Etch Application Examples
182
6.4.1.1 Ion damage avoidance
182
6.4.1.2 Wet etching of multilayer
III–V compounds
184
6.5Cleaning
185
6.5.1 Plasma Cleaning
187
6.6
Surface Passivation 187
6.6.1 Wet-Chemical Passivation
187
6.6.2 Chalcogenide Passivation
188
6.6.3 Dielectric Passivation 188
ix
x
Contents
7. Plasma Processing and Dry Etching
191
7.1
Plasma Processing
191
7.1.1 Plasma Basics
191
7.1.2 Glow Discharge Plasma
192
7.1.3 Voltage Distribution
195
7.1.4 Interaction of Ions with a
Surface/Sputter Yield
199
7.2
Dry Etching
202
7.2.1 Problems with Wet Etching 202
7.2.2 Advantages of Dry Etching
202
7.3
Plasma Etch Systems
204
7.3.1 Reaction Basics
204
7.3.2 Rate Equation
206
7.3.3 Process Parameters
207
7.3.4 Plasma Etch System Types
208
7.3.4.1 Barrel reactor
208
7.3.4.2 Parallel-plate planar reactor
209
7.3.4.3 Downstream reactor
211
7.3.4.4 High-density plasma reactor
211
7.3.4.5ECR
212
7.3.4.6ICP
212
7.3.4.7 Ion milling
213
7.4
Etch Processes
214
7.4.1 Etch Rate and Selectivity
215
7.4.1.1Loading
215
7.4.1.2 Selectivity 216
7.4.1.3Uniformity
216
7.4.1.4Microuniformity
217
7.4.2 CD and Etch Profile
217
7.5
Plasma Etching of Materials Used in III–V IC
Processing218
7.5.1 Selective Etches
219
7.5.2 Silicon Nitride and Oxide Etching
221
7.5.3 Metal Etching 222
7.5.3.1 Refractory metals
224
7.5.3.2Aluminum
224
7.5.3.3Gold/copper
224
7.5.3.4 Organic films
225
7.6
High-Aspect-Ratio Etching
225
7.6.1 Through-Wafer Via Etching
225
Contents
7.7
7.8
7.6.1.1 Etch chemistry for profile
control226
7.6.2 Wet Etching
226
7.6.3 Aspect-Ratio-Dependent Etching 228
Plasma Damage
230
7.7.1 Particle and Veil Generation
232
Etch Process Monitoring
232
7.8.1 Film Monitoring
233
7.8.2 Gas-Phase Monitoring
233
7.8.3 Optical Emission
233
8. Deposition Processes
237
8.1
Physical Vapor Deposition: Introduction
237
8.2
Vacuum Basics
238
8.2.1 Flow Regimes
240
8.3
Pumping Systems for Semiconductor
Processing241
8.3.1 Cryogenic Pumps
241
8.3.2 Turbomolecular Pumps
242
8.4
Pressure Measurement
243
8.5Evaporation
244
8.5.1 Evaporation Sources
245
8.5.1.1 Electron beam sources
246
8.5.2 Deposition Rate 247
8.5.2.1 Vapor pressure
247
8.5.2.2 Evaporation rate
248
8.5.2.3 Film thickness variation
249
8.5.3 Deposition Rate Monitors
251
8.5.4 Alloy Deposition 252
8.5.5 Film Growth Mechanism
252
8.6
Sputter Deposition
255
8.6.1 Advantages of Sputter Deposition
255
8.6.2 Deposition System Types
256
8.6.2.1 Planar diode
256
8.6.2.2Triode
256
8.6.2.3 Magnetron sputtering
257
8.6.3 RF Sputtering
258
8.6.4 Reactive Sputtering
259
8.6.5 Bias Sputtering
259
8.6.5.1 System selection
260
xi
xii
Contents
9.
8.7
8.8
8.6.6 Mechanism and Rates
Plasma-Enhanced Chemical Vapor Deposition
8.7.1 Film Requirements
8.7.2 CVD Systems
8.7.2.1 CVD reactor types
8.7.3 Plasma-Enhanced CVD
8.7.4 Production Multistation System 8.7.4.1 High-density plasma systems
Atomic Layer Deposition
8.8.1 ALD Principles
8.8.2 ALD Reactors
261
264
264
265
265
267
267
270
270
270
272
Ion Implantation and Device Isolation
275
9.1Introduction
275
9.1.1Advantages
276
9.1.2Disadvantages
276
9.2
Ion Implantation: Theory
276
9.2.1 Theory of Ion Stopping
277
9.2.2Channeling
283
9.2.3 Transverse Effects
283
9.2.4 Implant Damage
284
9.3
Ion Implantation Systems
286
9.3.1 Implantation System Parts
287
9.3.1.1 Ion source
287
9.3.1.2 Ion extraction and analyzing
device288
9.3.1.3 Accelerator tube
289
9.3.1.4 Beam scanning system
289
9.3.1.5 System end station
289
9.3.2 Ion Implanter Types
290
9.4
System/Process Issues
291
9.4.1 Masking Considerations
291
9.4.2 Doubly Ionized Species
292
9.5
Common Ion Implant Species for GaAs
292
9.5.1 n-Type Dopants
292
9.5.2 p-Type Dopants
295
9.5.3 Implants for Isolation
295
9.6
Ion Implant Characterization
296
9.6.1 Sheet Resistivity Monitoring
296
9.6.2 Optical Dosimetry 296
Contents
9.6.3
C–V Method
9.7
Implant Activation
9.7.1Annealing
9.7.2 Encapsulation for Annealing
9.7.3 Rapid Thermal Annealing
9.7.3.1 History of development
9.7.3.2 System description
9.7.3.3 Temperature control
9.7.4 Process Description 9.8
Activation of Dopants
9.8.1 n-Type Dopants
9.8.2 p-Type Dopant Activation
9.9
Device Isolation
9.9.1Introduction
9.9.2 Isolation by Etching
9.9.3 Ion Implant Isolation
9.9.4Mechanism
9.9.5 Isolation-Related Reliability Issues
for HBT
296
297
297
299
299
301
301
302
303
303
303
305
306
306
307
307
310
310
10. Diffusion in III–V Compound Semiconductors
315
10.1Introduction
315
10.1.1 Rate Equations
316
10.2 Diffusion Basics
317
10.2.1 Basic Mechanisms
317
10.2.1.1 Interstitial mechanism
317
10.2.1.2 Substitutional mechanism
318
10.2.1.3 Kick-out mechanism
319
10.2.1.4Interstitial-substitutional
mechanism319
10.2.2 Impurity Diffusion Rates in GaAs
320
10.3 Diffusion Equations for III–V Semiconductor
Processing321
10.3.1 Constant Diffusion Coefficient
322
10.3.1.1 Thin-film solution
322
10.3.1.2 Diffusion from a constant
source323
10.3.1.3 Diffusion from a limited
source 324
xiii
xiv
Contents
11.
10.4
10.5
10.6
10.7
10.3.1.4Concentration-dependent
diffusion coefficient
10.3.2 Interstitial-Substitutional Diffusion
Measurement of Diffused Layers
Diffusion in GaAs
10.5.1 Diffusion by Periodic Table Groups 10.5.2 Zn Diffusion in GaAs
10.5.3 Sulfur Diffusion in GaAs
Diffusion Systems
Rapid Thermal Diffusion
325
325
325
326
326
327
329
329
333
Ohmic Contacts
335
11.1Introduction
335
11.2History
336
11.3 Theory of Metal–Semiconductor Ohmic
Contacts337
11.3.1 Contact Resistance
339
11.4 Contact Resistance Measurement by TLM
340
11.5 Ohmic Contact Technology for n-Type Contacts 345
11.5.1 Epigrown Contacts
345
11.5.1.1 Contacts with heavy donor
doping345
11.5.1.2 Contacts with lower barrier
height346
11.5.2 Alloyed Ohmic Contacts
346
11.5.2.1 Gold:germanium contacts
346
11.5.2.2 Silicon:tin contacts
347
15.2.2.3 Indium-based contacts
347
11.5.3 Ohmic Contact Deposition
348
11.5.4 Alloy Process and Alloying Systems 348
11.5.4.1 Alloying systems
349
11.5.5 Mechanism of Contact Formation
351
11.5.6 Refractory Contacts
351
11.6 Ohmic Contacts to p-Type GaAs
353
11.7 Ohmic Contacts to InP Devices
355
11.8 Ohmic Contacts to GaN 355
11.8.1Mechanism
356
11.9 Ohmic Contact Corrosion
357
Contents
12.
Schottky Diodes and FET Processing
12.1 Schottky Diodes
12.1.1 Depletion Width
12.1.2 Schottky Diode Metallization
12.1.3 Reverse Breakdown
12.2 FET Gate Fabrication
12.2.1 Gate Metallization and Fabrication
12.2.2 Gate Recess Process
12.2.3 Gate Formation 12.2.3.1T-gate
12.3 Digital FETs
12.3.1 Gate Fabrication
12.3.2 Self-Aligned n+-Technique
12.3.3 Substitutional Gate Processes 12.3.4 Mixed-Signal Process
12.4 Heterojunction and Insulated Gate FETs
12.4.1HMESFET
12.4.2 SAG FET Technology: Remarks
12.5 Pregate Surface Preparation and Passivation
12.6 Current Developments
361
361
362
363
364
365
365
365
366
367
369
369
369
371
371
372
373
374
376
377
14.
HBT Processing
14.1Introduction
14.2 Review of HBT Process Evolution
14.3 Basic HBT Fabrication Process
14.4Self-Alignment
14.4.1 Base–Emitter Self-Alignment
399
399
400
403
406
407
13.
HEMT Process
13.1Introduction
13.2 Device Fabrication
13.2.1 InGaP HEMT
13.2.2 Low-Noise Process 13.2.3 Power Amplifier Process
13.2.4 Switch Process
13.3 InP HEMT
13.4 Processing Issues
13.4.1 Gate Walk
13.4.2 Gate Sinking
13.4.3 Breakdown Voltage Improvement
379
379
380
384
386
387
388
390
393
393
394
396
xv
xvi
Contents
14.4.2 Other Self-Alignment Schemes 409
14.5 Collector-Up HBT
410
14.6 Common HBT Epimaterials
411
I4.6.1 InGaP/GaAs HBTs 411
14.6.2 InP HBTs
412
14.7 HBT Contacts
413
14.8 HBT Geometry
416
14.8.1 Base Width
416
14.8.2 Layout Comparison
417
14.9 HBT Fabrication Issues
418
14.9.1 Junction Considerations
420
14.10 HBT Epilayer Design
422
14.10.1 Emitter Layer Design
422
14.10.2 Collector Layer
423
14.10.2.1 Subcollector layer
424
14.10.3 Base Layer Design
424
14.11 Other HBT Structure Improvements
424
14.11.1 Graded-Base HBTs
426
14.11.2 Double-Heterojunction Bipolar
Transistor426
15. BiFET and BiHEMT Processing
429
15.1 BiFET Process
430
15.1.1 Stacked Devices
430
15.1.2 Merged Devices
430
15.1.3 Guidelines for Extra Layers
433
15.1.4 Epitaxial Layer Screening
433
15.1.5 Fabrication Process
433
15.1.6 BiFET Gate Process
435
15.2 BiHEMT Process
439
15.2.1 BiHEMT Process and Yield
Improvement444
16.
MOSFET Processing
16.1Introduction
16.2Oxidation
16.2.1 Wet Oxidation
16.2.2 Liquid-Phase Oxidation
16.3 Dielectric Passivation
16.4 Atomic Layer Deposition
447
447
448
449
451
453
453
Contents
17.
16.5
16.6
p-Type Devices
Concluding Remarks
Passive Components
17.1Resistors
17.1.1 Semiconductor/GaAs Resistors
17.1.2 Thin-Film Resistors
17.1.3 Common TFR Materials
17.2Capacitors
17.2.1 MIM Capacitors
17.2.2 Silicon Nitride for MIM
17.2.2.1 Stacked capacitors 17.3Inductors
457
458
461
461
461
464
465
468
469
472
476
477
18. Interconnect Technology
483
18.1Introduction
483
18.2 Interconnect Requirements
484
18.2.1 Electrical Requirements
484
18.2.2 Adhesion and Barrier Requirements
485
18.2.3 Diffusion and Electromigration
Effects486
18.2.4 Interlevel Dielectric Layer
Requirements487
18.3 Production Interconnect Processes
487
18.3.1 Baseline Gold Interconnect Process
487
18.3.2 Plated Metal Interconnect Process
490
18.3.3 Air Bridge Process
491
18.3.4 Digital GaAs Interconnect Process
493
18.4 Future of Interconnect Technology
494
18.4.1 Copper Interconnects
494
19. Backend Processing and Through-Wafer Vias
497
Section I: Through-Wafer Via Process
497
19.1
19.2
19.3
19.4
19.5
19.6
497
498
500
501
502
504
504
Introduction Wafer Bonding
Wafer Thinning
TWV Photolithography
TWV Etch
Backside Metallization
19.6.1 Backside Plating
xvii
xviii
Contents
19.7
19.8
19.9
Section II: Wafer-Bumping Process
510
510
19.10Introduction
19.10.1 Advantages of the Wafer-Level
Bump Process
19.11 Requirements of Components of the Solder
Ball or Pillar Process
19.11.1 Underbump Metallurgy 19.11.2 Solder Ball and Pillar
19.12 Fabrication Process
19.12.1 Solder Ball Process
19.12.2 Copper Pillar Process
512
512
514
514
514
516
21.
Measurements and Characterization
21.1Introduction
21.2 Sheet Resistance
21.2.1 Four-Point Probe Method
21.2.2 Van der Pauw Method
21.3 Contactless Resistivity Measurement
535
535
535
536
538
539
Backside Street Etching Wafer Demounting/Debonding
Wafer Dicing
19.9.1 Scribe and Break
19.9.2 Laser Dicing
20.Electroplating
20.1 Electroplating History
20.2 Electroplating Fundamentals
20.3 Electroplating Bath Types
20.4 Electroplating Deposition Process
20.4.1 Pulse Plating
20.5 Metal Deposition Mechanisms
20.5.1 Polarization 20.5.2 Diffusion and Mass Transport
20.5.3 Microthrowing Power
20.5.4Brightening
20.6 Process Monitoring
20.6.1 Hull Cell
20.7 Electroless Plating
20.8 Copper Electroplating
20.8.1 Large-Volume Production
507
507
508
508
509
512
521
521
521
522
525
525
526
526
526
527
529
529
529
530
531
532
Contents
21.4
Carrier Mobility
540
21.4.1 Hall Mobility
540
21.4.2 Drift Mobility
542
21.5 Doping Profile by C–V Method
543
21.6 Schottky Diode Parameter Measurement
544
21.6.1 Current–Voltage Method
546
21.6.2 Activation Energy Method
547
21.6.3 Capacitance–Voltage Method for
Schottky Diode Barrier Height
Measurement547
21.7 FET Characteristics
549
21.7.1 FET Transconductance
549
21.7.2 FET Source Resistance Measurement
549
21.8 HBT Parameter Extraction
551
21.8.1Output I–V characteristics
551
21.8.2 Gummel Plot
551
21.8.3 Emitter Resistance
551
21.8.4
VCE Offset
553
21.8.5
Ron553
21.9 RF Characterization
553
21.9.1Introduction
553
21.9.2 S-Parameter Measurements
554
21.9.3 RF Figures of Merit
557
21.9.3.1VSWR
559
21.9.3.2 Load pull test
560
21.9.3.3PAE
560
21.9.3.4Linearity
560
21.9.3.5 Noise figure
561
21.9.4 Smith Chart
563
21.10 Film Thickness and Refractive Index
563
21.10.1Ellipsometry
564
21.10.2Interferometry
566
21.11 Film Stress Measurement
566
22.Reliability
22.1Introduction
22.2 Basic Reliability Testing
22.3 Test Procedure
22.3.1 Step Stress Test
22.3.1.1 Temperature measurement
571
571
572
574
575
577
xix
xx
Contents
22.4
22.5
22.3.1.2 Simulation of operation
FET/HEMT Failure Modes and Mechanisms
22.4.1 Gate Sinking
22.4.2 Ion-Induced Failure Mechanisms
22.4.3 Effect of Hydrogen 22.4.4 Mobile Ion Contamination
22.4.5 Hot Electron Trapping
22.4.6 Surface State Effects
HBT Degradation and Reliability
22.5.1 HBT Reliability Issues Related to
Base Doping
22.5.2 Hydrogen and Ion Implant Isolation
Ohmic Contact Degradation
Other III–V IC Failure Mechanisms
22.7.1Electromigration
22.7.2 Moisture Ingression and Corrosion
22.7.3 Stress-Induced Burnout
GaN Device Reliability
577
578
579
580
580
581
581
582
582
23. GaN Devices
584
587
588
588
588
589
589
590
Section I: GaN Electronic Devices
593
23.1
23.2
593
594
596
598
599
599
600
601
603
604
605
605
610
22.6
22.7
22.8
23.3
23.4
23.5
Introduction Bulk Crystal Growth
23.2.1 Hydride Vapor-Phase Epitaxy
23.2.1.1 MOCVD templates
23.2.2 High-Pressure Solution Growth
23.2.3 Ammonothermal Growth
Epitaxial Growth
23.3.1MBE
23.3.2OMVPE
23.3.2.1Doping
23.3.3HVPE
Device Physics and Device Types
Process Technology
23.5.1 Etching and Surface Passivation
of GaN
23.5.2 Ohmic Contacts
23.5.3 Schottky Contacts 23.5.4 Implant Isolation
593
610
610
612
613
Contents
Device Fabrication
23.6.1 AlN/GaN HEMT
23.6.2 Device Performance Optimization
23.6.2.1 Surface passivation
23.6.3 Normally Off GaN Devices
23.6.4 MMIC Fabrication
23.7Reliability
23.7.1 General Reliability Concerns
23.7.1.1 Gate sinking
23.7.1.2 Ohmic contacts
23.7.2 Current Collapse
23.8 III–N HBT Devices
23.8.1 GaN HBT Device Challenges
23.8.2 Current State-of-the-Art Performance
23.9 Other Devices
Section II: GaN Optical Devices
628
23.10 Introduction to LEDs
23.11 Junction Luminescence
23.11.1 Device Behavior: Electrical 23.11.2 Optical Characteristics
23.12 LED Processing
23.12.1 Visible LEDs
23.12.2 UV LEDs
23.12.3 Epitaxial Growth
23.13 Current Challenges
23.13.1 Current Performance
23.14 Introduction to III–N Lasers 23.14.1 Basic Principles
23.15 Diode Laser Fabrication
23.15.1 Fabry–Perot Semiconductor
Diode Laser
23.15.2 VCSEL 628
629
632
634
635
635
637
638
640
640
641
641
643
24.
23.6
RF MEMS
24.1Introduction
24.1.1 Differences with Silicon
24.2 Basics of MEMS
24.3 Ohmic Contact Switches
24.4 Capacitive Switches
614
614
614
617
617
617
620
620
620
621
621
624
625
627
628
643
645
651
651
652
652
652
653
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Contents
24.5
24.6
24.4.1 Electrostatic or Capacitive Excitation
24.4.2 Actuation Voltage
24.4.3 Piezoelectric Excitation
Process Technology
24.5.1 OMMIC Process
24.5.2 University of Illinois Process
Examples of Applications
24.6.1 Waveguide Switch
24.6.2 Fabry–Perot Filter 24.6.3 MEMS on MMIC
24.6.4 Hybrid Circuits
653
655
657
658
658
660
661
661
661
662
663
Appendix667
Acronyms673
Index
677
Contents
Preface
In this Internet age, practicing engineers still need a book that they
can keep on their desk. This book is aimed for them and also graduate
students and engineers new to the field of III–V semiconductor
integrated circuit (IC) processing. This book specifically addresses
the needs of students who know semiconductor theory but lack
detailed processing knowledge. The content is chosen on the
basis of the needs of students as seen by a teacher and the needs
of practicing engineers dealing with processing issues as seen by
an experienced process engineer. GaAs processing has reached
a mature stage, a long way from a few decades ago, when it was
more of an art than a science. New semiconductor compounds are
emerging that will dominate future materials and device research;
however, the processing techniques used for GaAs will still remain
relevant. This book covers all aspects of the current state of the
art of III–V processing, with emphasis on heterojunction bipolar
transistors (HBTs), the volume leader technology, having grown
due to the explosive growth of wireless technology. The book’s
primary purpose is to discuss processing; only necessary equations
are derived and device behavior is discussed for the purpose of
understanding device figures of merit and electrical parameters that
engineers need to understand and control. All aspects of processing
of active and passive devices, from crystal growth to backside
processing, including lithography, etching, and film deposition, are
covered. New material systems based on GaN are playing a larger
role on the development side; although the etching chemistries,
deposition materials, and temperature regimes are different, similar
principles apply. The most promising structures of these material
systems and devices are covered in the book.
The book covers semiconductor material basics, physics of
devices used in semiconductor IC processing, and all the processing
technologies used in III–V semiconductor fabrication. In the
discussion, differences with silicon IC processes are emphasized.
Crystal growth and particularly epitaxy are discussed in depth
because of the special role played by them and device structures
xxiii
xxiv
Preface
made possible by them. Photolithography, ion implantation, wet
and plasma etching, and deposition of films are covered in detail.
Thermal processes and diffusion are discussed to the level needed for
III–V processing. Schottky and ohmic contact physics and processing
are discussed from a practical point of view for controlling these
in high-volume production. All the device technologies currently
in use in the III–V semiconductor marketplace are discussed in
depth, including recently introduced bipolar field-effect transistor
(BiFET) and bipolar high-electron-mobility transistor (BiHEMT)
technologies. Device types that are emerging and expected to be
important in the near future, like metal–oxide–semiconductor
field-effect transistors (MOSFETs), are also introduced. Passive
devices and interconnects are covered, being integral to monolithic
microwave integrated circuit (MMIC) fabrication. Also, backside
processing, which is absolutely necessary for high efficiency,
is described in detail and wafer-scale bumping is introduced,
being critical to future higher-frequency needs. Characterization
of films and semiconductor layers, as well as device parameter
measurement, is covered in detail. Reliability issues relevant to III–V
semiconductors are discussed. Finally, emerging GaN devices and
microelectromechanical systems (MEMS) are briefly described.
Most published books on the market emphasize III–V device
physics. No new processing book has been published in a decade.
Published books are old and cover mostly FET processing. Ralph
Williams’s book, Modern GaAs Processing, is over 20 years old and
does not cover processing technologies in detail. S. K. Ghandhi’s
book, VLSI Fabrication Principles: Silicon and Gallium Arsenide,
covers processing techniques in detail but IC processing very briefly.
This book is also old, published in the 1980s. Fazal Ali’s book, HEMTs
and HBTs: Devices, Fabrication and Circuits, covers fabrication
very broadly and was also published in 1991, over 20 years ago.
Baca and Ashby’s book, Fabrication of GaAs Devices, has a narrow
focus, specializing in cleaning and passivation; basic IC processing
techniques are not covered. It was published in 2005, a decade old
now.
This (present) book covers all aspects of processing, from
crystal growth to backside processing. It covers the current volume
production device types, HBTs, HEMTs, etc. The book is not restricted
to GaAs; other emerging III–V materials are covered, too.
Preface
Epigrowth, device structure, and processing discussions
are connected together through different chapters. Processing
techniques relevant to III–V IC fabrication are described as they are
used in III–V processing facilities in high-volume production. Process
flows are illustrated by step-by-step block diagrams. Scanning
electron microscopy (SEM) pictures of actual devices are included,
where needed. This is one book to find any topic relevant to III–V
processing. Practical process problems and ways to handle these are
described.
The current understanding of III–V processing has come a long
way from the era when GaAs processing was based on practical
knowledge and company trade secrets. This book attempts to connect
practice on the fabrication floor to current scientific understanding.
Shiban Tiku
Dhrubes Biswas
xxv
Acknowledgments
The earlier books on GaAs and III–V semiconductor materials processing were written in an era when GaAs was considered the “technology of the future.” This present work, although inspired by those,
is aimed at fulfilling the needs of this era in which the technology is
well established and perhaps becoming the “technology of the past,”
while paving the way for future technologies. Many minds and hands
have contributed to this work. I am indebted to all my teachers over
the years, who left an indelible mark on my life. I also thank the people of India for the almost free education I received.
This book would not have been possible without support
from Skyworks Solutions’ management, Ravi Ramanathan, Nercy
Ebrahimi, and Andy Hunt, and IP council Donald Bollella, who
weighed the benefits of contributing to the III–V industry worldwide
over the risk of disclosing trade secrets. A lot of data came from my
fellow engineers at Skyworks and the CS MANTECH community
in general. Early feedback from Martin Brophy (Avago) and Peter
Asbeck (UCSD) encouraged me. In particular, help from the following
Skyworks colleagues is acknowledged: Heather Knoedler, Jens
Riege, Dave Crawford, Ravi Ramanathan, Mike Sun, Jiro Yota, Pete
Zampardi, Lance Rushing, Cristian Cismaru, Sam Mony, Lam Luu,
and Manjeet Singh. Constant support from my wife, Sushma, and
son, Vikram, helped me during difficult times. I am also thankful to
Archana Ziradkar of Pan Stanford Publishing for systematic editorial
help and to Barron Miller for drafting of many of the figures.
Shiban Tiku