Said El-Barbari and W. Hofmann
CHEMNITZ UNIVERSITY OF TECHNOLOGY
Department of Electrical Machines and Derives
D-09107 Chemnitz, Germany
Tel: ++49 371 531 3319 / Fax: ++49 371 531 3324 e-mail:
URL:
Keywords: Control, Design, Harmonics, Simulation, Three phase system, Renewable energy system,
Solar cell system, UPS
The Microcontroller based digital control of a three phase 4 wire PWM inverter for simultaneously supply of three phase and single phase load in transformerless stand alone photovoltaic application with battery energy storage (BES) and LC output filter is described. An observer is implemented to estimate the load current and to predict the space states for one step ahead. A control method based on the dead beat control algorithm is described to regulate the output voltage of the LC filter so that disturbance of the output voltage due to load unbalances is eliminated. Simulation results for various operation conditions are presented to verify the validity of the control method.
P V
G e n e r a t o r
D C / D C
2
B a t t e r y
S t o r a g e
D C / D C
1
D C
L i n k
3
Φ
4 W i r e
I n v e r t e r
O u t p u t
F i l t e r
D C D C D C
S L C
F i l t e r
L o a d
A C
D C D C
Z i n t
Fig.1: stand alone photovoltaic system with 3 phase 4 wire PWM voltage source inverter
Nowadays more attention is paid to PV systems and their related technology for domestic applications as well as in large central power stations. PV systems are advantageous because they are abundant, pollution free and distributed through the earth. The only draw back is that the initial installation cost is considerably high.
Since the power generated by an array of PV panels is direct-current, it may be transformed, either into a power with constant voltage for dc applications or into ac power. In both cases it is important to draw as much energy as possible from the PV panel. The output power of PV generators vary extensively with the weather conditions such as solar insulation, temperature and cloudy skies. To obtain the maximum power from such an array under any weather condition, it is necessary to connect the PV array to a converter that can adapt itself to the changing
V-I characteristic of the PV generator (MPPT).
In the system illustrated in figure 1 this is provided by the DC/DC2. In this way the battery will be always charged at the Maximum Power
Point. The goal of the system illustrated in figure
1 is to supply three as well as single phase loads of any art with constant amplitude sinusoidal voltage and constant frequency. For this propose the neutral point of the LC output filter and load is connected to the midpoint of the DC link capacitor bank. Due to load unbalances an intruding current flows throw the impedance between the neutral point and midpoint and a voltage drop occurs which distorts the symmetrical output voltage. To solve this problem the following measurements were taken
•
• a zero sequence current and voltage control is implemented a DC/DC converter is used to control the DC link voltage according to load unbalances
In this way the symmetry of the output voltage is achieved and the linear region of the PWM
1

modulator of the DC/AC VSI (Voltage Source
Inverter) is extended. For three phase inverters the dead beat control based on space vector was discussed in [3]. In [4] the disturbance observer, state variable observer and the dead beat control were combined to improve the transient and overall behaviour of the system. The digital control of the current minor loop for UPS applications to achieve quick and exact current response and to provide low THD of the output voltage waveform was described in [5]. The decoupling dead beat control of three phase inverter in dq -frame was explained in [1] and
[2]. In [1] the voltage and current equations were discretised separately, thus the final discrete inverter model is simplified whereas in [2] the voltage and current equations were combined during the discretisation and thus a precise full inverter discrete model is provided.
In this paper the dead beat control in [1] and [2] is adopted and extended to match for three phase four wire VSI . In addition, an observer is also implemented. The observer has the following tasks.
•
Estimation of the load currents which act as disturbance on the plant
•
One step ahead prediction of the VSI voltages and currents
In system proposed the neutral point of the output LC filter and the load are connected directly to the midpoint of the capacitor bank.
Figure 2 illustrates the basic circuit of the VSI.
The reference vector to be synthesised by the
SPWM (Sinus Pulse Width Modulation) is given by the output of the control loop. For three phase four wire PWM inverter, the voltages and currents can be obtained by using the average circuit model of fig. 2 shown in figure 3. In figure 3 the voltages and the currents are given by
V
I d
=
=
=
[ i u
[
[ d v u u i v v v d i w v v w d
]
T
]
T w
, I
]
T
L
, V
C
=
[
= i
Lu
[ v
Cu i
Lv v
Cv i
Lw
]
T v
Cw
,
]
T
, where V
= v d
/ 2
⋅ d (1) and d u
,d v
and d w
are the line to neutral duty cycles. The voltages and currents equations of the inverter and the output filter are given by i b i d + u
R
L
2 C b
R b v v d w
V b
2 C b i d -
C v
N 0 v u i
N 0
R
N 0
Fig.2: main circuit
C d dt
V
C
=
I
−
I
L i u i
L u
Z w
Z v
Z u v
C u
(2) d
L dt
I
= −
I R
+
V
−
V
C
− v
N 0 where v
N 0
=
R
N 0
( i u
+ i v
+ i w
)
R L i u
(4)
(3) i
Lu v u
≈
≈ C
≈ v
N0 v
Cu
≈
Fig.3: average model of three phase four wire inverter with output LC filter
The block diagram of phase u is illustrated in figure 4. The block G
PWM
describes the nonlinear behaviour of the PWM modulators. As it can be seen from this figure, the reference voltages of all three phases must stay within the linear region. In the conventional three phase inverter with balanced load and without fourth wire neutral connection the linear region will never be exceeded because the average of v
N 0
=
( d u
+ d v
+ d w
) v d
/ 6 is equal zero.
Whereas in three phase four wire inverter with unbalanced load the average value of v
N0
in equation (4) is not equal zero, therefore the control output d u
must increase to compensate this value.
G
PWM v
N0 i
Lu
1
Z u d u V
2 d
A d v u
1 sL+R i u
1 sC v
Cu
Fig.4: block diagram of the sine PWM inverter
This component is the main reason for the saturation of the PWM modulator and therefore it must stay within a certain region [9].
2

1 0
0
1 0
-2
1 0
0 k u
1 0
-2
1 0
0
The output filter has to be designed to provide a sinusoidal output voltage with low voltage ripple.
3.1 FILTER FREQUENCY f
0
The output voltage of the converter v u
consists of the fundamental harmonic which is proportional to the modulation function and high frequency harmonics. When the carrier function is a symmetrical sawtooth signal, the high frequency harmonics are odd multiples of the carrier frequency f s
(that is, f s
, 3f s
, 5f s
, and so on). The harmonics which are even multiples of the carrier frequency are zero. The waveform of the output voltage v u
also contains sidebands centred around multiples of f s
and given by f h
= n
⋅ f s
± m
⋅ f
1
(5) where f h
and f
1
are the frequencies of the sidebands and fundamental harmonics (reference signal), respectively, in Hz. The most dominate harmonics occur at the carrier frequency f s
and the first sideband harmonics f h
=f s
±
2f
1
. For this reason the resonance frequency f
0
=
1 /
(
2
π
LC
)
of the LC output filter must fulfill the following condition: f
1
< f
0
< f h
= f s
−
2 f
1
(6)
M = 0 . 0 0 1
M = 0 .5
M = 1
1 0
-2
0 2 4 6 8 1 0 f s
/ f
0
1 2 1 4 1 6 1 8 2 0
F ig.5: normalised voltage ripple versus the frequency ratio f s
/f
0
Figure 5 shows the normalised voltage ripple in dependence on the frequency ratio f s
/ f
0
where k u
=


γ
∞
∑
=
1 v
2 u ,
γ
− v u
2
, 1


γ
∞
∑
=
1 v
2 u ,
γ and v u , 1
=
M v d
2 and M is the modulation factor.
From the figure one can see that a low voltage ripple (k u
<5%) can be reached if the modulation factor is kept as high as possible and the ratio f s
/f
0
greater than 10.
Minimum ripple is reached at f s
/f
0
=14.5. The switching frequency of the inverter is 6kHz, that means the resonance frequency f
0
of the filter is
413.8Hz.
3.2 POWER LOSSES MINIMISATION
The second step in the design approach is to find an appropriate value of inductor L so that the power losses of the inverter at nominal load are minimised.
For this analysis it is enough to consider one phase of the inverter because all three phases are identical. Assuming that the major power losses corresponds to the conduction losses of the transistor, diode and the power losses in the inductor, caused by the resistance of the windings, the power losses of the three phase
VSI can be written as
P
=
6 P tr
+
6 P
D
+
3 P
L
(7) where
P conduction losses of a transistor tr
P conduction losses of diode
D
P
L
power losses of the inductive L due to the resistance of the windings
The objective function to be minimised is
P
→ min (8)
3.2.1 SWITCH CONDUCTION LOSSES
The phase current of a PWM VSI can be approximated by it’s first harmonic i u
≈ i
) u sin
(
ω
1 t
− ϕ
)
=
) i u sin
(
α − ϕ
)
(9)
The pulse period of the transistor can be written as
T on , tr
=
T s
2
(
1
+
M sin
( ) )
(10) where T s
=
1 / f s
the PWM period.
Assuming that the ratio between the carrier and fundamental frequency f s
/ f
1
is very high, the
3

voltage and current of the transistor during the pulse time T on , tr
can be considered as constant.
The energy losses within T on , tr
is given by
E on , tr
= v
CE
( i
C
( ) ) ( )
⋅
T on , tr
( )
(11)
Substituting (9) and (10) in (11) will result in
E on , tr
=
(
V
CE 0
+
R
BT
) i u sin
(
α − ϕ
) )
×
) i u sin
(
α − ϕ
) T s
2
(
1
+
M sin
( ) )
(12)
When the ratio f s
/ f
1
is very high, equation (12) can be considered as a differential equation by substituting T s with d
α
. The conduction losses of the transistor can be written as
P
Tr sin
) i u
π
[
+ ϕ
(
=
α
4
π
− ϕ
) ϕ
1
[
V
CE
+
M
0
+ sin
R
BT
) i u sin
]
⋅ d
α
(
α − ϕ
) ]
×
Solving equation (13) will yield
P tr
=
2
1
π
+
M
8 cos ϕ i
) u
V
CE 0
+
1
8
M
3
π cos ϕ
) i u
2
R
BT
(13)
(14) where V
CE 0
is the forward voltage drop of the
IGBT and R
BT
is the conduction resistant.
For a constant output voltage v
Cu
, constant frequency and nominal load R
L
the inverter current can be written as i u
( )
= v
Cu
( ) 1
+ j
ω
R
L
C
R
L
(15) and it’s magnitude as
) i u
=
) v
Cu
1
R
L
1
+
(
ω
1
R
L
C
)
2
(16)
The magnitude of the inverter output voltage is
) v u
=
) v
Cu

 1
− ω
2 LC
+
R
R
L


2
+ ω
2


L
R
L
+
CR


2
(17) and the modulation factor is
M
=
2
) v u v d
(18)
The angle ϕ
in equation (14) represents the angle between the inverter output voltage v u
and current i u
respectively. ϕ = arctan


ω
(
ω
R
2
+
LC
R
L
2
R
L
2
+ ω
+
2
L
C
2
−
R
2
L
R
L
2
C
R
)

 (19)
3.2.2 DIODE CONDUCTION LOSSES
The pulse time of the freewheeling diode is given by
T on , D
=
T s
2
(
1
−
M sin
( ) )
(20)
In the same manner as in (3.2.1) the conduction losses of the diode can be written as
P
D
=
2
1
π
−
M
8 cos ϕ i
) u
V
F 0
+
1
8
M
3
π cos ϕ 
) i u
2
R
BD
(21) where V is the forward voltage drop of the
F 0 diode and R
BD
is the conduction resistance.
3.2.3 INDUCTOR LOSSES
The inductance of a cylinder air inductor is given by
π 2
D
2
N
2
L
≈
(22) l and its resistance R
=
R
W
N (23) where
D inductor diameter l
N turns number
= dN inductor length d wire diameter
R resistance per turn
W
4

The ratio between two inductance is
L
≈
N
≈
R
L
1
N
1
R
1 and the power losses of the inductor is
P
L
=
1
2
) i u
2
R
=
1
2
) i u
2
L
R
L
1
1
(24)
(25) where R and
1
L are the parameter of a
1 reference inductor. Figur 6 illustrates the total power losses of equation (7) as a function of the inductance L. The power losses are normalised to the inverter output power.
1.3
P
P out
%
1.2
1.1
For experimental purpose a 1200V, 10A IGBT intelligent power module (IPM) from
MITSUBISHI of type PM10RSH120 was used.
The PWM signal was generated with a microcontroller of the type 80C166 from
SIEMENS. Figure 7 shows the frequency spectra of the inverter output voltage v u for a DC link voltage of 106V. The filter inductor was optimised as described in (3.2) where the IGBT and diode data are given in the manufacturer data sheet. The inductor parameters were directly measured. The filter inductance and capacitance were optimised to 4mH and 60
µ
F respectively.
The carrier frequency was set to f s
=6.25kHz and the filter resonance frequency to f
0
=324.8Hz. For the frequency ratio of f s
/f
0
≈
19 and the modulation factor of M
≈
0.5 the ripple factor can be red from figure 5 (k u
≈
2%). The measured ripple factor of the output voltage in figure 8 is
(k u
≈
2.5%).
30 v
Cu v
Cw v
Cv
1
0.9
0 4 8
L [mH]
12 16
Fig.6: power losses in dependence of the inductance L
20
3.3 EXPERIMENTAL RESULTS
The filter design approach was proved experimentally as illustrated in figure 7 and 8.
1
0.8
2 v u v d f
1 f s
=
=
50 Hz
6250 Hz
0.6
0.4
0.2
0
0 40 80 120
Fig.7: frequency spectra of the normalised inverter output voltage 2 v u v d
0
-30
0 4 8 t [ms]
12 16
Fig.8: inverter output voltages
20
The control proposed of the VSI is illustrated in
Figure 9. The output currents and voltages of the
VSI will be measured and then led to a sample and hold unit which is necessary to keep the measured quantities constant while the analogue to digital converter ( ADC ) is working. The ADC is integrated in the microcontroller and works in the proposed control in multiplex mode as it can be seen from the figure. The discrete values of the currents and the voltages behind the ADC will be stored in the microcontroller buffer. The stored values of the currents and voltages will be transformed in the synchronised dq0-frame which rotates with the electrical output
5

frequency of 50Hz. In this way, when the load is balanced, all AC quantities become DC quantities and thus the feedback control will not suffer from phase shifts. As the load currents act as disturbance on the plant, they will be fed forward to voltage and current control loop. The load current will be estimated by the observer and will not be measured directly.
To compensate the time delay caused by the multiplex operation of the ADC the voltages and currents at the instant k must be fed back instead of k-1. These are indicated by I o
( ) , V o
( ) and
I o
L
( ) in figure 9. The index o indicates observed quantities. v d
L
PWM
VSI
I C V
C
Multiplex
3
Φ dq0
S&H A/D
Buffer
Current
Control
I o
(k)
Î *
Voltage
Control
V
*
I
(k-1)
3
Φ dq0
V
C(k-1)
3
Φ dq0
I o
L(k)
V o
C(k)
Observer
&
Predictor
Fig.9: principle of the control method
4.1 PLANT MODEL
The currents and voltages equations in the time domain were combined to one sixth order matrix state equation. Thereafter, the resulting matrix was discretised and then transformed to the rotating dq0-frame as shown in (26).


 v
C i
+
1
+
1



=



A d 11
A d 21
A d 12
A d 22





 v
C
( ) i 


+



B d 11
B d 21
B d 12
B d 22





 d i
L



(26) y
=


 C d 11
0
0
C d 22





 v
C
( ) i
−
1



(27)
4.2 OBSERVER DESIGN
The observer is designed to estimate the load currents. That is why the load currents are handled as a space state quantities (28) and not as disturbance as in (26).




 v
C i i
L
+
1
+
1
+
1





=




A d 11
A d
0
21
A d 12
A d
0
22
B d 12
B d
C
22








 v
C
( ) i i
L





+




B d 11
B d 21
0



 d
(28) y
=



C d 11
0
0
C d 22
0
0 



 

 v
C
( ) i i
L
−
1
−
1





(29)
The state space model of the VSI can be expressed as: x
=
Ax
+
Bu (30) y
=
Cx
−
1
(31)
To predict the VSI currents and voltages v
C and i at the sampling instant k, the output y will be substituted in the observer equation (32) instead of y . x o
( )
=
Ax o
( )
+
Bu
+
H ( y
+
1
− y o
( ) ) (32) where H is 6x6 identity matrix of the observer.
Assuming that
?
+
1
= x o
( )
−
Hy
+
1
(33) and dissolving (32) and concerning (33), the observer equation will be
?
=
(
A
−
HC
) (
?
+
Hy
)
+
Bu (34) and the output x o
( )
=
?
+
Hy
Figure 10 illustrates the observer structure.
Plant
(35) x
(k+1)
= Ax
(k)
+ Bu
(k) y
(k)
= Cx
(k-1) u
(k)
Observer y
(k)
A-HC H
?
?
B 1/z
Fig.10: principle of the observer x o
( )
4.3 CURRENT CONTROL LOOP
From (26) the currents equation can be written as i
+
1
=
A d 21 v
C
( )
+
A d 22 i
+
B d 21 d
+
B d 22 i
L
(26)
6

where i d
=
=


 i






 i i d q
0
( ) d d d d q
( )
0










, i
L
= 



 i i
Ld i
Lq
L 0
( )





, v
C
= 



 v
Cd v
Cq v
C 0
( )





and
The first and second column of equation (26) express the relation of the inverter currents without the 0-component and can be written as


+ i i d q
( )
C
I
+
1
⋅




= d d
A d q
( )


I
⋅
+

 i i d q
( )
D
I
⋅




+ i
Ld
B i
Lq
( )
I


⋅

 v
Cd v
Cq


(27)
A ,
I
B
I
C and
I
D are 2x2 matrices which
I correspond to the first and second column in equation (25)
)
V
C
B
Id c
I
)
L
D
Idc
I
)
∗
G
IC
C
Idc
) d
C
I
D
I
B
I
1/z
I
)
A
Idc
A
I
Fig.11 principle of the current control loop with decouplings
Figure 11 illustrates the decoupled dead beat control of the inverter currents in the dq-frame.
From (37) one can see that the d and the q variables are coupled with each other. To enhance the performance of the control loop the capacitor voltage and the load currents are fed forward as seen from figure 11. To control i d and i q
separately the coupling elements in A
I and C
I
are decoupled by the matrices A
Idc
and
C
Idc
so that i d and i depend only on the q diagonal matrix elements A
I
. After removing the couplings, the dead beat controller G
IC
is provided.
4.4 VOLTAGE CONTROL LOOP
The voltage major loop is constructed in the same manner as the current minor loop. From
(26) the voltage equations can be written as v
C
+
1
=
A d 11 v
C
( )
+
A d 12 i
+
B d 11 d
+
B d 12 i
L
(38)
The first and second column of equation (38) express the relation of the inverter voltages without the 0-component and can be expressed as:

 v
Cd v
Cq
+
C
V
+
1
+
1

 =
⋅

 i d i q
( )


A
V
+
⋅

 v
Cd v
Cq
D
V
⋅

 i i
Ld
Lq

 +
B
V

 where A
V
, B
V
C
V
and
⋅

 d d d q
( )


(39)
D
V are 2x2 matrices which correspond to the first and second column in equation (38). The duty cycles and the load currents
[ i
Ld
( ) i
Lq
( )
[ d
]
T d
( ) d q
( )
T
] act as a disturbance on the voltage control loop in the rotating dq-frame. These disturbance quantities were compensated by feeding them forward through the decoupling matrices B
Vdc
, D
Vdc
.
Figure 12 illustrates the decoupled dead beat control of the inverter voltages in the dq-frame.
The matrices A
Vdc
and C
Vdc
are decoupling filter
)
V
C
depends only on the diagonal matrix elements of A
V
. After removing the couplings, the dead beat controller G
VC
is provided.
The same dead beat control is also applied to the
0 -sequence of currents and voltages except that, in the 0 control loop no decouplings are needed
[9].
B
Vd c
D
Vdc
I
)
L
)
V
∗
C
I
)
D
V
B
V
V
)
C
G
VC
C
Vdc
C
V
1/z
A
Vdc
A
V
Fig.12: principle of the voltage control loop with decouplings
The mathematical model of the DC/DC converter in the continuous conduction mode is established and linearised ([6], [7]). The digital control is implemented [8] so that the DC link voltage will follow a certain reference [9].
Figure 13-15 illustrates the simulation results of the decoupled dead beat control with an observer for the following load cycle:
7

Ø 0.00

0.02s balanced load
(I
Lu
=I
Lv
=I
Lw
=1A
∠
0)
Ø
0.02

0.04s balanced load
(I
Lu
=I
Lv
=I
Lw
=2A
∠
0)
Ø 0.12

0.2s unbalanced load
(I
Lu
=I
Lv
=10.4A
∠
0, I
Lw
=2A
∠
0)
Figure 13 shows the simulation results when an observer is used to estimate the load current and to predict the space states for the k+1 st
instant.
From the simulation results one can see the high dynamic performance of the introduced observer based control method as the disturbance of the output voltage is quickly compensated.
Figure 14 and 15 shows the original load currents and the load current estimated by the observer. From the figure it can be seen the high performance of the observer as the original load current almost the same as the estimated current.
4 0 0
3 0 0
2 0 0
1 0 0
0
- 1 0 0
- 2 0 0
- 3 0 0
- 4 0 0
0 . 0 0 0 . 0 1 0 . 0 2 0 . 0 3
T i m e [ s ]
0 . 0 4 0 . 0 5
Fig.13: voltages of the output filter
0 . 0 6
6
4
2
0
- 2
- 4
- 6 i o
Ld i
Ld
- 8
- 1 0 i o
Lq i
Lq
- 1 2
- 1 4
0 . 0 0 0 . 0 1 0 . 0 2 0 . 0 3 0 . 0 4 0 . 0 5 0 . 0 6
T i m e [ s ]
Fig.14: load current and estimated load current with the observer
3
2 i
L o
0 i
L 0
1
0
- 1
- 2
- 3
- 4
0 . 0 0 0 . 0 1 0 . 0 2 0 . 0 3 0 . 0 4 0 . 0 5 0 . 0 6
T i m e [ s ]
Fig.15: 0-sequence load current and estimated 0sequence load current with the observer
In this paper the observer based digital control method of the 3 phase four wire PWM inverter for stand alone photovoltaic systems with battery energy storage was presented. Using an observer, there is no need to measure the load currents directly as the load currents can be estimated by the observer and thus saving money because no additional measuring instruments
(LEM) are necessary. The output LC filter design for low ripple sinusoidal voltage and low power dissipation was described in detail in this paper. The resonance frequency of the output filter must be chosen for minimal ripple. The filter inductor value was chosen so that the whole system losses are minimised. The filter design approach was proved experimentally to illustrate the validity of the proposed design strategy. The measured and simulated ripple factor are almost the same.
References
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Yamamoto, "Digital Control of three-Phase
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8

[7] Francisco Guinjoan, Javier Calvente, Alberto
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