in
Digitally
Minimum Phase Response
Controlled Boost and Flyback
Converters
Vahid Yousefzadeh, Mariko Shirazi and Dragan Maksimovic
Colorado Power Electronics Center
ECE Department, University of Colorado, Boulder, CO 80309-0425
{ Vahid. Yousefzadeh, Mariko. Shirazi, maksimov I @ colorado. edu
Abstract- This paper addresses modeling and control issues
related to practical high-frequency digital PWM control of
constant-frequency boost, buck-boost and flyback converters.
Discrete-time models, including the effects of A/D sampling and
delays in the digital control loop, are derived for two cases:
output voltage A/D sampling during transistor off time in
combination with trailing-edge (TE) DPWM, and A/D sampling
during transistor on time in combination with leading-edge (LE)
DPWM. We show that off-time sampling with TE-DPWM, which
is a common approach in digital controller realizations, can
result in desirable minimum-phase responses, thus simplifying
compensator design in wide bandwidth closed-loop voltage
regulators based on boost or flyback converters. The results are
verified by simulation and experimental results on a boost
converter prototype.
I.
account A/D sampling, modulator sampling, and delays in the
digital control loop [5]. Discrete-time models are derived for
two cases: (a) A/D sampling during transistor off time in
combination with trailing-edge PWM, and (b) A/D sampling
during transistor on time in combination with leading-edge
PWM. Corresponding control to output frequency responses
are found in Section III and compared to predictions of the
averaged small signal models. Approximate closed-form
results are derived for the zero in the discrete-time control-tooutput transfer function, leading to conditions for minimumphase responses. Section IV presents experimental results that
illustrate validity of the modeling results for a digitally
controlled boost converter prototype.
INTRODUCTION
lL
Much of the work reported so far in the area of digital
control of high-frequency switching power converters has
been related to point-of-load synchronous buck converters,
while fewer references (e.g. [1, 2]) focused on boost and other
DC-DC converters. In this paper, we consider modeling and
control issues related to practical high-frequency digital
control of constant-frequency boost and flyback (including
buck-boost) converters shown in Fig. 1.
Based on averaged-switch or state-space averaging models,
it is well known that a constant-frequency trailing-edge (TE)
pulse-width modulated (PWM) boost or flyback converter
exhibits a right-half-plane (RHP) zero in the control-to-output
frequency response [3]. The presence of a RHP zero tends to
destabilize wide-bandwidth feedback loops, because during a
transient the output initially changes in a wrong direction.
With a non-minimum-phase control-to-output response, it is
difficult to obtain an adequate phase margin in conventional
single-loop voltage regulators having wide bandwidth. An
interesting result was reported in [4] where it was shown that
leading edge (LE) pulse-width modulation can lead to
minimum-phase responses of boost and flyback converters
with analog voltage-mode control.
The objective of this paper is to show how sampling and
modulation in a standard constant-frequency voltage-mode
digital PWM controller shown in Fig. l(c) can be arranged to
achieve desirable minimum-phase responses leading to
improved closed-loop performance of digitally controlled
boost or flyback voltage regulators. Section II summarizes a
small-signal discrete-time modeling approach that takes into
1-4244-0714-1/07/$20.00 C 2007 IEEE.
(a) Boost converter
(b) Flyback converter
_IFV0
H
H v0
compensator
'M
d
.4-
Gc()
IFtVole AIDre
e
-4
(c) Digital PWM controller
Figure 1. Digital voltage mode PWM control of boost and flyback
converters.
865
II. DISCRETE-TIME MODELING OF DIGITALLY CONTROLLED
DC-DC CONVERTERS
*x(t)+x~(t)
This section summarizes small-signal discrete-time models
for constant-frequency digitally controlled PWM converters
operating in continuous conduction mode where A/D
sampling of the output voltage occurs once per switching
period [5]. The models in [5] take into account A/D sampling,
modulator sampling and a delay td in the digital control loop,
which is an extension of discrete-time modeling described in
[6] and elsewhere (e.g. [7-9]). It should be noted that the
modeling approach described in [10], which makes use of the
modified Z-transform, also correctly accounts for sampling
instants and delays. The derivation, however, is
straightforwardly applicable only to buck-type converters.
To examine the effects of A/D and modulation sampling
instants in the responses of boost and flyback converters, we
consider two cases: (a) A/D sampling of the output voltage
during transistor off time ("off-time sampling") in
combination with trailing-edge (TE) DPWM, and (b) A/D
sampling of the output voltage during transistor on time ("ontime sampling") in combination with leading-edge (LE)
DPWM.
xi[n- l]
2
(n -)T +tdl
(1)
^
=[C2^[n]
PO)
L[
VC +
where:
'D
DTo0
~
~~~
ST,
dnTs-50)
RIIR
Rload
Rload +esr
= e A2 (T, -td )e
*Qposition
o
nTs
coincide with the modulated edge of g(t) [6, 7]. The total
delay td in the digital control loop is the time between the A/D
sampling and the modulated edge of the DPWM. It consists of
a delay tdl (indicative of A/D conversion time and
computation delays) between the sampling point nTs, and the
start point of the PWM saw-tooth ramp signal, and the
modulator delay DTs. The total delay td = tdl + DTs is less than
the switching period TS.
Figure 3 illustrates how perturbations in a state variable
propagate over a switching period. The resulting small-signal
discrete-time model is [5]:
x[n] = a24ln-1] + Yad[n - 1]
(2)
a=
j
i
(n -I)T, +DT + tdl
changes in the pulsating switch control signal g(t) in response
to changes in the duty-cycle command d affect the converter
waveforms as a stream of delta functions -p. This means that
the PWM operates as a sampler with sampling instants that
where q = 1 corresponds to transistor on time, q = 2
corresponds to transistor off time, and the states x include the
capacitor voltage v, and the inductor current iL.
V
-1l]Ts
Figure 3. Evolution of a state perturbation during a switching period for a
digital controller with TE-DPWM and off-time A/D sampling.
q are:
v0 (t) = CqX(t) + EqVg
~-dd[n
2
(n-I)Ts
i[n]
lxl
'dtdl±DT
Consider a constant-frequency PWM switching converter
operating in continuous conduction mode. The state-space
equations for the switching converter in the switching position
Aqx(t) + BqVgI
ydn1
~~~~X
i
A. Discrete-time modeling for trailing-edge DPWM with
AID sampling during transistor off time
dt
dlt~~
ResrII
load
II
-L
(3)
esriL
A1DT, e A2 (td -DTs)
(4)
A2(T -td)aT
(5)
(A1 A2)XP + (b1 b2)Vg
-
-
(6)
and Xp is the vector of steady-state state variables at the end of
transistor on time. It is important to note how the delay td
affects the model parameters in (2), (4) and (5), and how (3)
takes into account A/D sampling of the output voltage during
during transistor off time (position 2).
B. Discrete-time model for leading-edge DPWM with AID
sampling during transistor on time
Figure 4 shows a timing diagram of the saw-tooth ramp in a
leading-edge DPWM. The A/D converter of the digital
controller samples the output voltage at times ts = nTs, during
transistor on time (position 1). The resulting small-signal
discrete-time model is [5]:
X[n] = Dbx[n-l] + ybd[n l]
(7)
_
(n+I)T,
t
nTs + td + £'
(nz-I)Ts + td + 6'
Figure 2. Timing diagram for a digital controller having a trailing-edge
digital pulse-width modulator (TE-DPWM) and A/D sampling of the
output voltage during transistor off time.
Figure 2 shows a timing diagram of the saw-tooth ramp in a
trailing-edge DPWM. The A/D converter of the digital
controller samples the output voltage at times ts = nTs, during
transistor off time (position 2). In the small-signal limit,
-
ol
866
~~~~Rload +Resr [0lviLLicv
L
load
(8)
where:
= e Al (T, -td) eA2D T, e Al (td
transfer function GVd (s) = vo2d having a RHP zero at the
frequency
-DiT )
(9)
'D
(10)
yb= e Al ( T -td )aT,
and a can be again found from (6) where Xp is the vector of
steady-state state variables at the end of transistor off time.
D2
f,
PO-
-
2
(11)
D'Rload
2zL
It should be noted that the averaged model also predicts a lefthalf-plane zero at 11(22tCResr) due to the capacitor ESR.
Vm i 0X
*: position (.)
g(t)
Rload I
i dI,
niT
dnTsg('()
Figure 5. Small-signal averaged equivalent circuit model of the boost
converter in Fig. 1(a).
(n+1)T,
From (2)-(3), the discrete-time control-to-output transfer
function for off-time sampling with TE-DPWM can be found
t
(n-1)T, + td + £
lnTs + [d±+ 6
Figure 4. Timing diagram for a digital controller having a leading-edge
digital pulse-width modulator (LE-DPWM) and A/D sampling of the
output voltage during transistor on time.
as:
(12)
GVd-a(z)=C2(zI -a)YIa
Similarly, from (7)-(8), the discrete-time control-to-output
transfer function for on-time sampling with LE-DPWM is
given by
It is of interest to compare the small-signal model for offtime sampling with TE-DPWM (2)-(5) to the model for ontime sampling with LE-DPWM (7)-(10). The key differences
are in how the duty-cycle perturbations affect the state
perturbations (Eq. (5) versus Eq. (10)) and when the output
voltage is sampled (Eq. (3) versus Eq. (8)). In particular,
notice that off-time sampling (3) results in output voltage
samples that depend on capacitor voltage and inductor current.
In contrast, on-time sampling (8) results in output voltage
samples approximately equal to capacitor voltage samples
only. As discussed further in the next section, these
differences can result in dramatically different zero locations
in the control-to-output responses. Finally, we again note that
the models (2)-(5) and (7)-(10) include the effects of A/D and
modulator sampling instants, as well as the delay td in the
digital control loop. These effects, which are not taken into
account in standard averaged converter models, are important
for understanding control-to-output responses of digitally
controlled boost or flyback converters even at relatively low
frequencies.
Gvd b (Z) =
C1
(ZI -b
)
Yb
(13)
As an example, let us consider a boost converter with the
following parameters: f, = 1/T, = 100 kHz, L =40 gH,
Vg= 10V,
C=240gF,
Resr=50 mfQ,
RL= 10 mQ,
Rload = 10 Q, D = D'= 0.5, and tdi 0. Since D = D'= 0.5, the
total delay in both considered cases is the same, td = tdl+0.5Ts
0.5Ts.
Figure 6 compares numerically computed magnitude and
=
phase responses of: (1) GVd(s), (2) G,d a(Z), and (3) Gvd b(Z). In
the response (1) from the averaged model, the contributions of
the RHP zero and the ESR zero nearly cancel out in the phase
response. Interestingly, however, the response of GVd for offtime sampling with TE-DPWM in the digitally controlled
boost converter shows even less phase lag than the response
obtained from the averaged model, even though the discretetime model includes effects of the delay td in the digital
control loop. On the other hand, the phase lag in the response
of GVd b for on-time sampling with LE-DPWM is significantly
a
III. CONTROL-TO-OUTPUT RESPONSES
worse.
To explain the magnitude and phase plots observed in Fig. 6,
and to examine conditions for minimum-phase responses, we
In this section, control-to-output frequency responses based on
discrete-time models described in Section II are evaluated and
compared to frequency responses obtained from the converter
apply the linear-ripple approximation ( eAt
I + At ) to the
matrix exponentials in (4)-(5) and (9)-(10), and further
standard continuous-time averaged small-signal model.
A. Boost converter
Figure 5 shows a small-signal averaged model for the boost
converter of Fig. 1(a), including the effects of inductor series
resistance RL and the capacitor equivalent series resistance Resr.
The averaged model predicts a second-order control-to-output
simplify the results assuming RL << Rload, and Resr << Rload.
The poles of the control-to-output transfer functions are the
same in all cases, but the zeros can differ dramatically.
We focus on finding expressions for the location of the zero
in the discrete-time control-to-output response: a zero outside
the unit circle corresponds to a non-minimum phase response
(equivalent to a RHP zero in a continuous-time model); a zero
867
minimum-phase response facilitated by off-time sampling
with trailing edge DPWM in a digital controller.
Let us now examine the zero location in the case of on-time
sampling with LE-DPWM. An approximate closed-form
expression for the zero in the discrete-time model is:
4C
-e
2CI
C.
D'2Rload16)
L
(16)
L
As expected, on-time sampling results in a zero that is always
on the positive axes outside the unit circle, corresponding to
non-minimum phase response (i.e. a RHP zero in s-domain).
zero b
-20
C
tce
0
B. Flyback converter
-go
For the flyback converter shown in Fig. 1(b), in the case of
off-time sampling and TE-DPWM, we get the following
approximate expression for the zero in the discrete-time model:
,- 18C
-270
-360
zero
Frequency (Hz)
Figure 6. Magnitude and phase responses of the control-to-output
transfer functions: (1) GVd(s) from the averaged model in Fig. 5, (2)
GVd a(z) from the discrete-time model for off-time sampling with TEDPWM, and (3) G,d b(Z) from the discrete-time model for on-time
sampling with LE-DPWM.
inside the unit circle
on
the positive
axes
RC-
results in desirable
ReSrC>
a
T~
1+
R C>
es
on
D
D
D'Rioad
In the case of a buck-boost
phase condition (18) becomes
on
the positive axis inside
n2
(18)
n
(Dn 2 + D')
converter, n
=
1, the minimum-
R es
C> DL
load
td
(19)
For the case of on-time sampling with LE-DPWM, it can be
shown that the zero in the discrete-time model of a flyback
converter is always outside the unit circle.
ResrC-DR
Since Ts - td> 0, the zero (14) is
the unit circle as long as
n2
DL
DRlad (Dn2 + D')
Since T, - td > 0, the zero (17) is
the unit circle as long as
For the case of off-time sampling with TE-DPWM we get
the following approximate closed-form result for the zero:
(14)
1
zero
T,-td
a
1+
minimum-phase response.
Z
(17)
1
IC
I
the positive axis inside
IV. EXPERIMENTAL RESULTS
L
DR
(15)
An experimental digitally controlled boost converter is
shown in Fig. 7. The converter parameters are the same as in
It is interesting to note that the minimum-phase condition (15)
obtained from the discrete-time model for off-time sampling
with trailing-edge DPWM agrees with the result in [4], which
discussed leading-edge pulse-width modulation in an analog
controller as a way to achieve minimum-phase response. In
light of the discrete-time modeling approach of Section II, we
can offer the following explanation: a leading-edge modulator
in the analog controller simply facilitates off-time sampling of
the analog control signal, which in turn (for a sufficiently
large voltage drop across the capacitor ESR) leads to
minimum-phase response observed by the controller. A step
up in duty-cycle command still results in a temporary drop in
the capacitor voltage. However, as long as the output voltage
is sampled during transistor off time, the contribution of the
voltage drop across the capacitor ESR proportional to inductor
current obscures the drop in capacitor voltage (see Eq. (3)). As
a result, the change in the wrong direction is simply not "seen"
by the controller. Essentially the same explanation holds for
onverter
oard
Figure 7. Experimental digitally controlled boost converter:
f = lTS = 100lkHz, L = 40 uH, C = 240 uF, Resr = 50 mQ,
RL lOmQ, Vg= 1OV,Rload= 1OQ,D =D'= 0.5,andtdl 0.
868
the example discussed in Section lIIIA. Digital controller is
implemented on a Xilinx Virtex II development board.
Exactly the same hardware is used to test open-loop and
closed-loop responses for two cases: (a) off-time A/D
sampling with TE-DPWM, and (b) on-time A/D sampling
with LE-DPWM.
Figure 8 shows open-loop output voltage response to a step
increase in duty-cycle command d. The effects of sampling the
output voltage are clearly visible: a dip, i.e. a temporary
change in the wrong direction can be observed if the output
voltage is sampled during transistor on time. In contrast, no
such dip can be observed if the output voltage waveform is
sampled during transistor off time.
Closed-loop operation includes a discrete-time PID
TeK Run' 2.SOMS/S
Hi Res
compensator,
653z2
6.35(z
1.985z +0.987
(0
i )(z -0.8008)
The magnitude and phase responses of the loop gains for offtime sampling with TE-PWM, and for on-time sampling with
LE-PWM are shown in Fig. 9 based on discrete-time models
derived in Section II. Exactly the same compensator (20) is
applied in both cases, and the cross-over frequencies are
nearly the same, f. 4 kHz. However, there is a dramatic
difference in phase margins: off-time sampling with TE-PWM
results in 0 Trail = 450, while on-time sampling with LE-PWM
results in a much lower phase margin 0 lead of only 80. The
corresponding step-reference transient responses shown in
Fig. 10 are in good agreement with the modeling predictions.
G~(z)
Gcz)
(0
.....1... --1
Tek Run. 2SOkS/s;
Step d' command
i.
Hi Res
..-
Step command,
---j
m
In
itl
.I
500m.-iwv -2
5.00V
M 20.01Rps C 6 2
lv
Figure 8. Open-ioop output voltage response to a step increase in dutycycle command.
am00OMV)
TeK Run: 250kS/S
3C
z
10
=
Hi Res
(a)
.-.Ti..
Step. command
kHIz
10
-2C
-3C
I-
C~ .9c
2 27
.36
1o~
Chl
I
Frequency
10IC
(Hz'
Figure
9.
Magnitude
sampling
time sampling
and
phase
with TE-DPWM
responses of the
loop gain
(phase margin
(phase margin
with LE-DPWM
M
200OIS ChiI
~
-240MV
(b)
Figure
with
time
200 V
SOOMVNv
450),
05
led
for
(1) off-
and
(2)
Closed-loop step
TE-DPWM,
and
reference responses for
step reference command indicator. Lower
on-
voltage
=80).
869
(a) off-time sampling
(b) on-time sampling with LE-DPWM. Upper
v,(t).
trace: ac
trace:
coupled output
The digital controller implementation and experimental
results reconfirm the conclusion that the presence or absence
of a non-minimum phase zero (RHP zero in s-domain, or zero
outside the unit circle in z-domain) depends on the output
voltage sampling instant rather than the type of modulation
(trailing edge or leading edge). Sampling during transistor off
time in combination with standard trailing-edge modulation,
which is the most common situation in digital controller
realizations, can result in desirable minimum-phase responses
(provided that conditions (15) or (18) are met), and simplifies
compensator design for wide bandwidth feedback loops
around boost or flyback converters.
by simulation and experimental results on a boost converter
prototype.
ACKNOWLEDGMENT
This work was supported by industrial sponsors of the
Colorado Power Electronics Center.
REFERENCES
[1]
[2]
[3]
[4]
V. CONCLUSIONS
The paper presents discrete-time models of boost and
flyback switching converters with digital control, including
the effects of A/D and modulator sampling and delays in the
control loop, for two cases: trailing-edge DPWM with A/D
sampling of the output voltage during transistor off time, and
leading-edge DPWM with A/D sampling during transistor on
time. We show that the sampling instant rather than the type of
modulation is the key to achieving desirable minimum-phase
responses in boost or flyback converters. Off-time sampling
with trailing-edge DPWM, which is a common approach in
digital controller realizations, can result in desirable
minimum-phase responses, thus simplifying compensator
design in wide bandwidth closed-loop voltage regulators
based on boost or flyback converters. The results are verified
[5]
[6]
[7]
[8]
[9]
[10]
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