Isolation Technology Dr. Lynn Fuller - RIT
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Isolation Technology ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Isolation Technology Dr. Lynn Fuller Motorola Professor Microelectronic Engineering Rochester Institute of Technology 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Fax (585) 475-5041 LFFEEE@rit.edu http://www.microe.rit.edu Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor 4-2-03 Isolation.ppt Page 1 Isolation Technology OUTLINE ISOLATION TECHNOLOGIES FOR BIPOLAR INTEGRATED CIRCUITS STANDARD BURIED COLLECTOR TRIPLE DIFFUSED PROCESS COLLECTOR DIFFUSED MESA ISOLATION TECHNOLOGIES FOR MOS INTEGRATED CIRCUITS GROW OXIDE AND ETCH SEMI RECESSED LOCOS SPOT FULLY RECESSED LOCOS FUROX BIRDS BEAK ENCROCHMENT BURIED-OXIDE ISOLATION PROBLEMS SHALLOW TRENCH ETCHED BACK LOCOS DEEP TRENCH POLY BUFFERED LOCOS FIELD SHIELD SILO SILICON ON INSULATOR POP-SILO WAFER BONDING SWAMI SILICON ON SAPPHIRE Rochester Institute of Technology SIMOX Microelectronic Engineering MESA © Dr. Lynn Fuller, Motorola Professor Page 2 Isolation Technology INTRODUCTION The main idea is to build transistors on the same substrate, that are electrically isolated from each other. To do this the transistors are usually surrounded by a reverse biased pn junction or surrounded by an insulator or in the case of MOS devices “ringed” by a thick oxide layer. Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 3 Isolation Technology JUNCTION ISOLATION IN STANDARD BURIED COLLECTOR PROCESS N-Type Epi P+ P N+ N+ P+ N+ P-Type silicon N-type active area is surrounded on four sides and bottom by a reverse biased pn junction - isolating one active area from another Lateral Diffusion equals Epi Thickness Disadvantage is size (area used) for Isolation Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 4 Isolation Technology COLLECTOR DIFFUSED ISOLATION P-Type Epi N+ P N+ N+ N+ P-Type silicon Improved Packing Density Lower Breakdown Voltage (space charge layer is on the lighter doped side - the base side) Higher parasitic junction capacitance Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 5 Isolation Technology TRIPLE DIFFUSED ISOLATION P N+ N P P N P-Type silicon Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 6 Isolation Technology GROW OXIDE AND ETCH N N P N+ P p-well Step Height ~ 1 µm N-Type silicon Thick Oxide and Channel Stop (in p-well) keeps parasitic transistor off. For n-well CMOS channel stop is in p-substrate. Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 7 Isolation Technology SEMIRECESSED LOCOS N N P N+ P P Step Height ~ 0.5 µm N-Type silicon Local Oxidation of Oxide (LOCOS) gives a step height about 1/2 of the “grow oxide and etch isolation” approach Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 8 Isolation Technology SEMIRECESSED LOCOS This is what we use at RIT in the p-well CMOS process Nitride Pad Oxide Pad oxide should be at least 1/3 nitride thickness to work as a stress relief layer Etch nitride and pad oxide, implant channel stop if needed Grow field oxide Lateral oxide growth can be 0.5 µm to 0.1 µm, formation of “bird’s beak” Field Oxide Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 9 Isolation Technology SEMIRECESSED LOCOS DETAILS Pad oxide should be at least 1/3 nitride thickness to work as a stress relief layer. Nitride thickness needs to be thick enough to not be consumed during field oxide growth. Etching off nitride and pad oxide after field oxide is often done wet. Top of nitride is oxidized so it needs an HF etch followed by Hot (200 C) Phosphoric Acid etch or plasma etch. Kooi oxide growth is a sacrificial oxide to clean up any silicon nitride formed under the pad oxide by diffusion of NH3 (from water nitride reaction) through pad oxide. Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 10 Isolation Technology KOOI (SACRIFICIAL) OXIDE White ribbon problem Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 11 Isolation Technology BIRDS BEAK ENCROCHMENT Original Mask Field Oxide Birds Final Beak Active Device Field Oxide Birds Beak Bird’s beak encroachment limits the scaling of channel widths to ~1.5 µm Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 12 Isolation Technology LOCOS BIRDS’ BEAK Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 13 Isolation Technology 0 0.1 0.2 0.3 0.4 0.5 Oxidation Rate (µm/hr) BIRDS BEAK ENCROCHMENT nitride pad ox y Pad ox=500Å Pad ox=100Å 0 0.05 0.10 0.15 0.20 y 0.25 µm Note: at y= 0.2 µm in from the edge the oxidation rate is ~0.1 µm/hr for 500 Å pad oxide, so for a 2 hr oxide growth the pad oxide will grow ~ 0.2 µm compared to a 100 Å pad oxide with growth rate of almost zero. Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 14 Isolation Technology LOCOS PROBLEMS Boron channel stop implant encroachment in addition to oxide encroachment into the active region Stress induced damage Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 15 Isolation Technology SIMULATIONS OF STRESS The yield strength of silicon is 7E9 Pascals Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 16 Isolation Technology STRESS DAMAGE The stress can be large enough to cause damage in the silicon at the edge of the LOCOS. The D/S junctions are also located at the edge of the LOCOS. The result is that the junctions are leaky. Stress increases with increased nitride thickness, increased field oxide thickness and decreased pad oxide thickness. In the RIT Pwell CMOS process pad oxide is 500 Å, nitride is 1500 Å and field oxide is 11,000 Å. We may get more reliable results by decreasing the nitride to 1000 Å and decreasing the field oxide to 8000 Å Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 17 Isolation Technology ETCHED BACK LOCOS The etch back reduces topology and birds beak but eventually exposes the channel stop implant in the p-type substrate or well field areas. (important for width) Nitride Field Oxide Field Oxide Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 18 Isolation Technology FULLY RECESSED OXIDE LOCOS Nitride Pad Oxide Etch Silicon Birds Head Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Field Oxide Page 19 Isolation Technology FULLY RECESSED LOCOS – BIRD’S HEAD Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 20 Isolation Technology POLY BUFFERED LOCOS Nitride ~2400 Å Poly ~500 Å Pad oxide ~100 Å Poly layer reduces stress and produces birds beak of only 0.1 to 0.2 µm Field Oxide Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 21 Isolation Technology POLY BUFFERED LOCOS Crab Eyes Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 22 Isolation Technology SILO Sealed Interface Local Oxidation - SILO Thin Nitride directly on Silicon, then Low Temp Oxide, then 2nd Nitride, then etch the silicon a little before FOX 2nd Nitride Etched Silicon LTO 1st Nitride Need to etch silicon to reduce the surface topology. This process gives a steeper step than normal LOCOS Field Oxide Field Oxide Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 23 Isolation Technology PROTECTIVE OXIDE PAD - SILO (POP-SILO) 2nd Nitride layer Low Temperature Oxide ~1500 Å 1st Nitride Layer ~800 Å Pad oxide ~125 Å Second nitride layer thickness chosen to give spacer of 0.25 µm 0.25µm Field Oxide Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 24 Isolation Technology SWAMI - Hewlett-Packard Stress relief pad oxide,1st nitride layer silicon etch and field implant 2nd Nitride and LTO RIE etch of LTO Nitride Etch Final Result Grow Field Oxide Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 25 Isolation Technology SWAMI Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 26 Isolation Technology SPOT 1st FOX LPCVD 2nd nitride Etch 1st FOX RIE nitride and oxide FOX Grow 2nd Pad Ox Grow final FOX Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 27 Isolation Technology FUROX LTO 1000 Å Nitride 800 Å Pad Oxide 200 Å RIE FOX 4500 Å FOX 7700 Å Nitride 400 Å Oxide 100 Å Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 28 Isolation Technology NON-LOCOS ISOLATION Trench Etch and Refill Replace LOCOS Replace Deep Diffusion Isolation Used to prevent latchup in CMOS Used to combine Isolation and Capacitor formation in DRAM structures Shallow Trench and Refill (0.5-0.8 µm) BOX Moderate Depth Trench (~2 µm) U Groove Deep Trench (>3 µm) Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 29 Isolation Technology BOX (BURIED-OXIDE) ISOLATION Oxide 4000Å 1st Photoresist, flowed 2nd Photoresist layer Etch Shallow Trench LTO Deposition Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Planarizing RIE etches resist and LTO at same rate Page 30 Isolation Technology MODIFICATIONS TO IMPROVE BOX Improvements: Void formation can occur if trenches are narrower than 2 um. High Temperature LPCVD of SiO2 helps. Inversion of silicon sidewalls of p type active areas is possible so angled Boron Ion Implant or Spin on Dopant source is used to dope side walls with Boron. Uniformity is hard to control. Since it is non uniform the SiO2 must be over etched leaving downward step in active area causing other problems. Stress induced damage Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 31 Isolation Technology BURIED OXIDE WITH ETCH STOP BOXES Mo 2500 Å Nitride 250 Å Pad Oxide 150 Å Etch Shallow Trench Thin Thermal Oxide and LTO Deposition RIE Etch, Stop on Mo Remove Mo, Nitride and Pad Ox This process avoids exposed downward step at edge of the active areas Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 32 Isolation Technology U-GROOVE AND TOSHIBA MODERATE DEPTH TRENCH ISOLATION 2.5 µm p+ n- epi n- epi p- well n+ BL p+ p-sub n-sub U-grove if made with anisotropic wet etch (KOH/Isopropylalcohol) followed by dry anisotropic etch. The trench is filled with thermally grown oxide 0.4 um, nitride and polysilicon. Toshiba is all dry etch and refill thermal oxide and poly. note: poly refill can not be used for trenches of different width Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 33 Isolation Technology DEEP TRENCH ISOLATION 2.5 µm oxide poly n- epi p+ p-sub Deep trench Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 34 Isolation Technology FIELD SHIELD ISOLATION Field Plates Useful in high voltage devices because the substrate dopings are not increased to make a channel stop. (Increased doping reduces breakdown voltage) Instead a poly layer over the field region is connected to a negative voltage to keep the surface from inverting. Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 35 Isolation Technology SILICON ON INSULATOR Dielectric Isolation Wafer Bonding SOI Silicon on Saphire SIMOX Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 36 Isolation Technology DIELECTRIC ISOLATION n-type Silicon Grow Oxide Open Windows Etch Silicon and Strip Oxide Grow Oxide Deposit Thick Poly Layer P Flip and Polish down to Insulator Rochester Institute of Technology N+ N+ Build Devices Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 37 Isolation Technology WAFER BONDING SOI Starting Wafer Form V-grooves Deposit Poly Planarize N+ Flip and Bond Wafer Thin and Polish Starting Wafer Grow Oxide P Build Devices Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor N+ N+ Page 38 Isolation Technology WAFER BONDED SOI Silicon Oxide Silicon Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 39 Isolation Technology WAFER BONDING Two oxidized-silicon wafers pressed together and subjected to an oxidizing ambient of 700 C (requires applied pressure) With an applied Voltage and temperatures of 1100 to 1200 C One oxidized wafer and one bare wafer are cleaned in H2O2 + H2SO4, rinsed and dried, After drying the wafers are placed faceto-face at room temperature. A self-adhesive contact is formed. Bonding is completed by a 4 hour 1100 C heat treatment in nitrogen. Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 40 Isolation Technology SOS - SILICON ON SAPPHIRE Thin layer of single crystal silicon, combined with trench isolation, to make isolated devices Starting Saphire wafer, Al2O3, Single crystal and a Silicon epitaxial layer can be grown on it. Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 41 Isolation Technology SIMOX -SEPARATION BY ION IMPLANTED OXYGEN Implanted Oxygen or Nitrogen Ions Thin layer of single crystal silicon, combined with trench isolation, to make isolated devices 1 Million Electron Volt, High Dose (2E18) Implant, to Make a Buried Dielectric Layer of SiO2 or Si3 N4 , Also 200KeV, High Dose Implant followed by anneal and Epi Growth Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 42 Isolation Technology REFERENCES 1. Silicon Processing for the VLSI Era, Vol. 2&3., Stanley Wolf, Lattice Press, 1995. 2. The Science and Engineering of Microelectronic Fabrication, Stephen A. Campbell, Oxford University Press, 1996. 3. The Invention of LOCOS, Else Kooi, Institute of Electrical and Electronic Engineers, Inc., NY, NY 1991 Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 43 Isolation Technology HOMEWORK - ISOLATION 1. Discuss the problems with isolation by the standard LOCOS process. 2. In reference to the RIT p-well CMOS process sketch the crossection of the active area of a 1.0 micrometer transistor showing bird’s beak encrochment. Scale the sketch using the appropriate figures from the lecture. 3. What is the advantage of poly buffered LOCOS? 4. What is the difference between Sealed-Interface-Local-Oxidation (SILO) and Protective-Oxide-Pad SILO? 5. What is the advantage of the SWAM, SPOT and FUROX processes? 6. Describe trench isolation. What is the main advantage of trench isolation over local oxidation approaches? 7. Describe four approaches to silicon on insulator isolation technologies. Rochester Institute of Technology Microelectronic Engineering © Dr. Lynn Fuller, Motorola Professor Page 44
