International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) - 2016
Common-Mode Voltage Eliminated 2-level PWM
Inverter Based on a Cascaded 3-level Inverter
Chandini G S., Shiny G., M.R.Baiju
Power Electronics Research Laboratory
Dept. of Electronics and Communication
College of Engineering Trivandrum, Kerala, India
mrbaiju@cet.ac.in
Abstract— Conventional Pulse Width Modulated (PWM)
inverters create common mode voltage with high frequency
anddv⁄dt. Common-mode voltage causes motor shaft voltage,
bearing current and electromagnetic interference (EMI) in the
induction motor drive system. In this paper, a common-mode
voltage eliminated 2-level space vector pulse width modulation
scheme based on a cascaded 3-level inverter is presented. When
the inverter is controlled by PWM, the common-mode voltage
dropped between the neutral point of the motor and the negative
terminal of the inverter supply is of alternating nature. In the
proposed scheme, inverter voltage vectors having the same
common mode voltage are used to generate the PWM signal. This
eliminates alternating common-mode voltage and its adverse
effects. The scheme is experimentally verified using a 3-level
inverter realized by connecting two 2-level inverters in cascade
configuration and experimental results are presented to validate
the scheme.
Keywords— Common-mode voltage elimination, Cascade
inverter, Bearing current, Shaft voltage
I. INTRODUCTION
Multilevel inverter technology has developed as a solution
for high power medium voltage industrial applications because
of its inherent advantages offered [1]. Conventional PWM
inverters produce alternating common-mode voltage (CMV)
in the induction motor drive system [2,3]. This CMV builds up
through capacitive coupling between stator and rotor frame
results in current flow through motor bearings [2-5]. Frequent
occurrence of bearing current causes premature failure of
motor bearings, due to electric discharge machining.
Electrostatic methods to reduce voltage build up by weakening
the capacitive coupling can result in low CMV [2-4]. The
PWM inverters with modulators resulting in low or zero CMV
are suggested as solution with the help of additional hardware
[5]. These inverters also generate both conducted and radiated
EMI. When multilevel inverters are used, the EMI effect can
be reduced due to the low frequency, low voltage switching
which results in low ⁄ [2-4]. PWM inverters which do
not produce common-mode voltage are recommended as
solution to eradicate these adverse effects [6-11].
A modulation scheme for elimination of CMV in neutral
point clamped 3-level inverter using exclusive voltage space
vectors which do not cause common-mode voltage is
978-1-4673-9939-5/16/$31.00 ©2016 IEEE
presented in [7]. In [8] a 3-level PWM scheme using an
H-bridge 5-level inverter is proposed to reduce common-mode
voltage. But this method requires six isolated power supplies.
A space vector PWM scheme for the complete elimination of
alternating common-mode voltage in a dual inverter fed open
end winding induction motor drive is proposed in [9]. Vectors
of individual inverters are selected so as to avoid alternating
common-mode voltage in the drive system and 2-level space
vector is deduced from 3-level space vector diagram.
A 3- level inverter scheme from 5-level inverter scheme with
complete elimination of alternating CMV is proposed in [10]
for open end winding configuration. A hybrid 5-level inverter
topology for the elimination of CMV using space vector PWM
based switching scheme is suggested in [11]. This topology
uses single dc source and different voltage levels are generated
by means of floating capacitors.
This paper presents a scheme based on 3-level inverter
realized by cascading two 2-level inverters [12], for the
elimination of alternating CMV using space vector PWM.
This topology does not experience neutral point fluctuations
and no need of clamping diodes [12]. This scheme uses
inverter voltage vectors having same common-mode voltage,
to generate PWM signal. Two groups of space vector
combinations are identified for the 2-level common-mode
eliminated structure from 3-level structure. From this one
group of space vector combinations having minimum
common-mode voltage is selected for PWM generation. The
proposed method is experimentally verified on a 2HP, 3-phase
induction motor drive in open loop v/f control for different
modulation indices.
II. PRINCIPLE AND MECHANISM OF COMMON-MODE VOLTAGE
Common-mode voltage generated by 2-level and multi
level PWM inverters results in motor and drive application
problems [2]. Due to common-mode voltage, motor shaft
voltage will build up through electro static couplings between
rotor and stator windings and between the rotor and the frame.
This results in extreme bearing current due to large shaft
voltage. This bearing current results in untimely motor bearing
failures. The bearing damage can be observed as the pits in the
bearing race. In the three phase PWM inverter-motor system
shown in Fig.1, the pole voltages with respect to negative DC
bus O are VAO, VBO and VCO. These pole voltages can be
decomposed into
V
V
V
V
V
V
III. PROPOSED CMV ELIMINATION SCHEME FOR CASCADED
INVERTER TOPOLOGY
(1)
Where VAN, VBN and VCN are phase voltages and VNO is the
common-mode voltage of the system, given by
(2)
At lower switching frequency of the inverter, induction
machine will experience the differential mode voltage only
i.e., phase voltage or line to line voltage. Once the switching
frequency of an inverter is increased to higher levels, the
homogeneous allocation of windings along with the stator
surface enhances parasitic capacitive coupling effect. Thus
machine windings begin to behave capacitive [3].
From the experimental measurement of bearing currents,
two types of bearing currents, namely conduction mode
bearing current and discharge mode bearing current are found
to exist in PWM inverters [4]. Conduction mode bearing
current is the current flowing in bearings during their peak
conductivity period of time. With low inverter output
frequency and low motor speed, there is only conduction
mode bearing current. Discharge mode bearing current is the
large bearing current spike due to the loss of conductivity of
bearings for a short period of time [4].
Fig.2 shows the 3-level inverter topology realized by
connecting two 2-level inverters in cascade, where inverter-1
and inverter-2 are conventional 2-level inverters [12]. In this
configuration, the points A1, B1 and C1 (Fig. 2) of inverter-1
are connected to the positive DC rail of corresponding phase
of inverter-2. The pole voltages of inverter-1 are VA1O, VB1O
and VC1O and that of inverter-2 are VA2O, VB2O and VC2O.The
terminals A2, B2 and C2 of inverter-2 are connected to the
phase windings of induction motor. The pole voltage of
inverter-2 can assume any one of the three possible values 0,
Vdc/2 and Vdc, which are the characteristics of 3-level
inverter. In terms of pole voltages, the space vector Vs can be
represented by
/
/
(3)
Fig.3 shows space vector diagram of a 3-level inverter. It
can be viewed as a hexagonal structure having 24 sectors.
There are 64 space vector combinations for a 3-level cascaded
inverter, which are located at 19 space vector locations as
shown in Fig.4.
The common-mode voltage generated in the pole voltage
of cascade inverter is expressed as
In summary the main causes of bearing current are
parasitic coupling capacitances and common- mode voltages.
Solution for the reduction of common- mode voltages reported
in the literature involves additional hardware [5]. Complete
elimination of CMV is reported in [9-11]. In this paper a
2-level PWM inverter based on a cascaded 3-level inverter is
proposed to eliminate alternating CMV.
Fig. 1. Three phase 2-level PWM inverter-motor system
Fig. 2. Cascaded 3-level inverter fed induction motor drive
(4)
Some space vector combinations of the 3- level inverter
generate same common-mode voltage in the phase voltage of
the induction motor. Space vector locations such as
201,210,120,021,012 and 102 of 3-level space vector diagram
(Fig.3) are all having same common-mode voltage. For
example take the space vector combination 201, where vector
2 represents voltage Vdc, 0 represents voltage zero and 1
represents voltage Vdc/2.Then common-mode voltage VNO is
given by
0
VNO (201) =
/2 /3
/2
Similarly for space vector combination 210,
/2
VNO (210) =
0 /3
/2
From space vector diagram of cascade inverter (Fig.4) it
can be seen that combinations 16’ and 26’ are located in 201,
12’ and 62’ are located in 210 and so on. The combination 16’
means inverter-1 is in switching position 1(100) and inverter-2
is in switching position 6’ (101).Similarly for combination 26’
means inverter-1 is in switching position 2(110) and inverter-2
is in switching position 6’ (101).
Fig. 3. Voltage space vector representation of a 3-level
inverter
Common-mode voltage for 1(100),
/2
VNO (100) =
0
0 /3
/6,
for 6’(101),
/2
VNO (101) =
0
/2 /3
/3
Then for combination 16’, VNO (16’) =Vdc/2
Similarly for combination 26’
VNO (110) =
/2
VNO (101) =
/2
/2
0
0 /3
/3
/2 /3
/3
VNO (26’) = 2Vdc/3
Table 1 represents two groups of phasor combinations. Each
group is having same CMV. From which, group 1 with
minimum CMV is selected for PWM generation. If only these
space vector combinations are used for inverter switching, the
alternating common-mode voltage is eliminated, thereby
removing the adverse effects of ⁄ switching.
There are seven such vector combinations which can be
realized by using the combinations 16’, 12’, 32’, 34’, 54’, 56’
and 87’. These space vector combinations represent a 2-level
structure, as shown in Fig.5. The individual inverters assume
four states 1(100), 3(010), 5(001) and 8(000) for inverter-1
and 2’ (110), 4’ (011), 6’ (101) and 7’ (111) for inverter-2.
In the proposed topology, the active voltage space vectors
are generated by switching the individual voltage space
vectors, which are located at 60o apart. The maximum
amplitude of the reference space vector that can be
synthesized by the drive with the proposed PWM scheme is
given by (Fig. 5)
| | max =
√
√
(Vdc) =
Vdc ------------------- (5)
Fig. 4. Voltage space vector combinations of cascaded
inverter
It can be seen from Fig. 5 that the space vector diagram of
the proposed 2-level structure is leading by an angle 30o,
compared to that of conventional 2-level space vector
diagram.
The switching vectors of the proposed PWM strategy is
generated from the instantaneous amplitude of the three phase
reference sinusoid [13]. The dwell time calculations are
determined from conventional equations for 2-level inverter
[14].
IV. EXPERIMENTAL RESULTS AND DISCUSSION
The proposed modulation strategy is experimentally
verified on a 2HP, 3 phase induction motor drive in open loop
configuration with v/f control for different modulation indices.
To generate the driving signals for the inverters, dSPACE DS
1104 RTI platform is used. The driving signals are captured
using TLA 5201B logic analyzer.
TABLE 1: Two groups
common- mode voltage
of
phasor
combinations
Group1
Vector
Phasor
combination
201
having
same
Group2
CMV
Phasor
combination
CMV
16’
Vdc/2
26’
2Vdc/3
210
12’
Vdc/2
62’
2Vdc/3
120
32’
Vdc/2
42’
2Vdc/3
021
34’
Vdc/2
24’
2Vdc/3
012
54’
Vdc/2
64’
2Vdc/3
102
56’
Vdc/2
46’
2Vdc/3
The driving signals for modulation index, m=0.3 are
shown in Fig.6. The pole voltage, phase voltage and commonmode voltage of cascade inverter for m=0.3 are shown in top
trace, middle trace and bottom trace of Fig.7 respectively. The
shape of pole voltage waveform and phase voltage waveform
are same because common-mode voltage is absent in the pole
voltage.
Fig. 6. Driving signals of inverter-1(top three traces),
inverter-2 (bottom three traces) for m=0.3
The driving signals for m =0.85 are shown in Fig.8 and the
pole voltage, phase voltage and common-mode voltage of
proposed scheme are shown in top trace, middle trace and
bottom trace of Fig.9.
The motor is run under over modulation region (m =1.1)
and the driving signals are shown in Fig.10. The pole voltage,
phase voltage and common-mode voltage for over modulation
operation are shown in top trace, middle trace and bottom
trace of Fig.11.
As the pole voltage do not have common-mode voltage
component, the difference between the pole voltages (line to
line voltage) is equal to the motor phase voltage, which is a six
step waveform as shown in Fig.12, for m =0.85.
Fig.13 and Fig.14 show motor phase current waveforms
for m =0.85 and m =1.1 respectively.
Fig. 7. Pole voltage (top trace), phase voltage (middle trace) and
common-mode voltage (bottom trace) for m=0.3
Scale : X axis: 1 div =10ms, Y axis: 1 div =100V
Fig. 8. Driving signals of inverter-1(top three traces),
inverter-2 (bottom three traces) for m =0.85
Fig. 5. Space vector combinations for active vectors and zero
vector used in the proposed work.
Fig. 9. Pole voltage (top trace), phase voltage (middle trace) and
common-mode voltage (bottom trace) for m =0.85
Scale : X axis: 1 div =10ms, Y axis: 1 div =100V
Fig. 10. Driving signals of inverter-1 (top three traces),
inverter-2 (bottom three traces) for m =1.1
Fig. 11. Pole voltage (top trace), phase voltage (middle trace),
common-mode voltage (bottom trace) for m=1.1
Scale: X axis: 1 div =10ms, Y axis: 1 div =100V
Fig. 12. Line to line voltage for m=0.85
Scale: X axis: 1 div =10ms, Y axis: 1 div =50V
Fig. 13. Motor Phase Current for m=0.85
Scale: X axis: 1 div =20ms, Y axis: 1 div =1A
Fig. 14. Motor phase current for modulation index=1.1
Scale: X axis: 1 div =10ms, Y axis: 1 div =1A
V. CONCLUSION
A scheme for the elimination of alternating common-mode
voltage for a 3-level inverter is proposed. The elimination of
common mode voltage reduces neutral point fluctuations in
the topology. With the absence of the common-mode voltage
in the drive, the problems related to the motor such as shaft
voltage, electro static coupling, bearing current, fluting and
conducted EMI etc are eliminated. The proposed scheme can
be applied to higher levels of multilevel inverters. The scheme
is developed and experimentally tested with a 2-HP induction
motor drive. The experimental results are presented including
operation in over modulation region for a 3-level inverter in
cascaded configuration.
[6]
[7]
[8]
[9]
[10]
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