A NEW ARCHITECTURE OF CONSTANT-gm RAIL-TORAIL INPUT STAGE FOR LOW VOLTAGE LOW POWER
CMOS OP AMP
THESIS
Presented in Partial Fulfillment of the Requirements for the Degree Master of Science in
the Graduate School of The Ohio State University
By
Yiqiao Lin, B.S.
Graduate Program in Electrical and Computer Engineering
The Ohio State University
2010
Master's Examination Committee:
Professor Mohammed Ismail, Advisor
Professor Waleed Khalil
Copyright by
Yiqiao Lin
2010
ABSTRACT
A new architecture of rail-to-rail input stage for CMOS low voltage low power op
amps is presented in this paper. Based on the current-mode design, the new architecture
simply implements two additional transistors to realize the constant-gm requirement for
the rail-to-rail input stage. Analysis is conducted for both transistor operation regions:
strong inversion and weak inversion and proves that the constant-gm design is universal.
Simulations including constant gm performance over the entire common-mode input
range, worst case simulation, and Monte Carlo simulation are done in Cadence using
TSMC 0.18 µm technology with the supply voltages of +0.6 V. A maximum gm variation
of 2.5% is achieved under strong inversion operation and 3.7% under weak inversion
operation. The total transconductance of the complementary input pairs is almost constant.
After implementing the input stage into a unit gain buffer, the frequency response, DC
response and step response are done. The main advantage of the new architecture of railto-rail input stage is its largely reduced complexity in the design. Important parameters
were summarized and compared with the previous literatures in a table.
A comparative study between several typical types of constant-gm techniques in
the previous literatures and recent literatures is done. Advantages and disadvantages
analysis of the each single type are given in the comparative study which shows a look in
ii
the trend of simple, robust and universal constant-gm rail-to-rail input stage design for
low voltage low power op amps.
A summary of the applications of low voltage low power op amp is given. An
expected application of the author design is also made. Prospects of the future work are
given, specifying the next research step after current work.
iii
Dedication
This is dedicated to my parents.
iv
ACKNOWLEDGMENTS
I would like to give my appreciation to my advisor, Prof. Mohammed Ismail for
his guidance throughout my whole MS study. I want to especially thank him for allowing
me to be free to think in my research and to pursue the topics that interested me. He was
always there to meet with me and talk about my ideas, giving good advice to my papers,
and helping me to think through my problems. I realize that the experience and advice he
has given me in my MS study will be invaluable to my career.
I would also like to thank Prof. Waleed Khalil, for being on my MS committee
and for guiding me on various projects. He was always patient to listen to my confusion
and encouraged me to challenge through my research. Working with him has allowed me
to gain insight on projects outside analog design, which I know will benefit me greatly as
an aspiring engineer.
I would like to thank my friends at the Analog VLSI lab. In addition to the help
they have given me during my thesis, they make the lab such a good working place and
home to me. They always provide very good candies and drinks for the lab.
I would like to thank my best friend Hui Zheng, for her love, support, and being
by my side since middle school.
v
I would especially like to thank Jeff Chalas, who supports me at any time and who
is always there listen and give advice.
I would finally like to express my thanks to my parents, who have encouraged me
to work towards my best throughout my whole life. I know none of this would be
possible without them
vi
VITA
May 1986 .......................................................Born-Xiamen, China
June 2008 .......................................................B.S. Electronic Engineering
September 2008 - March 2010 ......................The Analog VLSI Lab, Department of
Electrical and Computer Engineering, The
Ohio State University
PUBLICATIONS
Li, Biao and Lin, Yiqiao. “Effects of bridge parameters on sensitivity of AC Bridge”
Physics Experimentation: Vol. 26, Supp., Sept. 2006.
FIELDS OF STUDY
Major Field: Electrical and Computer Engineering
vii
TABLE OF CONTENTS
Abstract ............................................................................................................................... ii
Dedication .......................................................................................................................... iv
Acknowledgments............................................................................................................... v
Vita.................................................................................................................................... vii
List of Tables ...................................................................................................................... x
List of Figures .................................................................................................................... xi
Chapter 1: Introduction ...................................................................................................... 1
1.1 Motivation ................................................................................................................. 1
1.2 Rail to Rail input stage .............................................................................................. 2
1.3 Organization of this Thesis ....................................................................................... 6
Chapter 2: Comparative study with previous approaches................................................... 7
2.1 Maximum and minimum circuits .............................................................................. 7
2.2 Constant-gm with independence of transconductance factor ................................... 10
2.3 Overlap transition regions ....................................................................................... 16
2.4 Constant reference gm .............................................................................................. 19
2.5 Native transistor ...................................................................................................... 21
2.6 Weak inversion operation maintaining constant sum current ................................. 22
viii
Chapter 3: A new constant-gm rail-to-rail input stage design ........................................... 24
3.1 Strong inversion operation ...................................................................................... 25
3.2 Weak inversion operation........................................................................................ 29
3.3 Advantages and disadvantages ................................................................................ 30
3.4 Simulation result and discussion ............................................................................. 31
3.4.1 Strong inversion simulation results .................................................................. 32
3.4.2 Weak inversion simulation results .................................................................... 37
3.5 Summary ................................................................................................................. 38
Chapter 4: Applications of low voltage low power rail-to-rail op amps .......................... 39
4.1 Instrumentation amplifiers ...................................................................................... 39
4.2 Bio-medical applications ......................................................................................... 41
4.3 Portable devices....................................................................................................... 41
Chapter 5: Conclusion and future work ............................................................................ 43
5.1 Conclusion............................................................................................................... 43
5.2 Future work –a self biased cascode stage................................................................ 46
Bibliography ..................................................................................................................... 48
ix
LIST OF TABLES
Table 1 Summary Table .................................................................................................... 38
x
LIST OF FIGURES
Figure 1. Rail-to-rail complementary input stage ............................................................... 2
Figure 2. gm variation over rail-to-rail common-mode input voltage ................................. 4
Figure 3. Maximum gm selection ........................................................................................ 7
Figure 4. Rail-to-rail input stage with max gm selecting circuits ........................................ 8
Figure 5. Transconductance overlapping in transition region .......................................... 10
Figure 6. Constant summing of VSGP+VGSN ..................................................................... 11
Figure 7. VC biased constant gm biasing circuits............................................................... 12
Figure 8. Current biased constant-gm biasing circuits ....................................................... 13
Figure 9. Constant gm biasing circuit with voltage drops in loop ..................................... 15
Figure 10. Constant gm technique with overlapping in transition region .......................... 17
Figure 11. Constant gm technique with transition region shifting ..................................... 18
Figure 12. Constant gm circuits implementing with DC shifter ........................................ 19
Figure 13. Constant gm technique with reference value .................................................... 21
Figure 14. Native input pair implementation for rail-to-rail input stage .......................... 22
Figure 15. Rail-to-rail constant-gm input stage operating in weak inversion with constant
sum of current for differential pair.................................................................................... 23
Figure 16. gm versus common-mode input voltage for complementary input stage ......... 25
xi
Figure 17. Rail-to-rail input stage with gm control by current division ............................ 26
Figure 18. gm control by the implementation of a push-pull inverter which drives 3/4
current from the tail current of the complementary input pairs operating in strong(S)
inversion and 1/2 current from the tail current of the input pairs operating in weak(W)
inversion............................................................................................................................ 27
Figure 19. The transconductance of the CMOS input stage in strong inversion using the
input sine waves of frequency 1MHz, 100MHz and 1GHz .............................................. 32
Figure 20. gm performance simulated at corners at room temperature ................................. 33
Figure 21. Monte Carlo simulation of gmtotal under 100 runs on process and mismatch ....... 34
Figure 22. Frequency response with Vp = 2mV differential sine wave input ...................... 35
Figure 23. Unit gain transfer curve for the op amp ............................................................. 36
Figure 24. Step response of unit gain buffer ....................................................................... 36
Figure 25. The transconductance of the CMOS input stage in weak inversion ................ 37
Figure 26. Two amplifier instrumentation amplifier ........................................................ 39
Figure 27. Three amplifier instrumentation amplifier ...................................................... 42
Figure 28. Cascode current mirror .................................................................................... 46
Figure 29. Wide Swing Cascode current mirror ............................................................... 46
Figure 30. Proposed self-biased folded cascode stage ...................................................... 47
xii
CHAPTER 1
INTRODUCTION
1.1 Motivation
The down scaling process and the demand for power efficiency call for low power
low voltage VLSI design [1]. The minimum channel length has reduced from 10 µm in
1970s to 45nm and even 32nm today. The voltage supply is reduced simultaneously in
order to ensure adequate performance. At the same time, greater density of the transistors
on the chip requires lower power consumption for each device unit in order to avoid
excess heating of the chip. Portable devices and the possibility of using circuits for the
bio-medical applications take another big portion for the growth of the low voltage low
power design.
As a result, low-voltage low-power (LVLP) VLSI design, especially the design of
LVLP op amps is in great demand. In order to get the maximum Signal to Noise ratio at
the output, the op amp is required to achieve a rail-to-rail output swing which could
easily be realized by Class AB design [1, 2]. Inverting op amp does not necessarily need
a rail-to-rail input stage since its common mode input is biased at a reference voltage
level. For non-inverting op amps such as a voltage follower, a rail-to-rail input stage is
1
required [1]. This is often realized by implementing a complementary input pair with
differential NMOS and PMOS input pairs in parallel.
1.2 Rail to Rail input stage
The complementary input stage with differential NMOS and PMOS input pairs is
shown in Figure 1.
VDD
|VDS|
R1
R2
+
- Voutn Vin M1
M2
-
VCM
Ibiasp
|VGS|
M3
|VGS|
|VDS|
+
Vin
-
- Voutp -
VCM
Ibiasn
M4
R3
R4
VSS
Figure 1. Rail-to-rail complementary input stage
As we can see from the figure, NMOS pair operates for the common mode range:
𝑉𝐶𝑀,𝑁𝑀𝑂𝑆 > 𝑉𝑆𝑆 + 𝑉𝐷𝑆,𝐼𝑏𝑖𝑎𝑠𝑛 + 𝑉𝐺𝑆,𝑀1
And PMOS for the common mode range:
2
(1)
𝑉𝐶𝑀,𝑃𝑀𝑂𝑆 < 𝑉𝐷𝐷 − |𝑉𝐷𝑆,𝐼𝑏𝑖𝑎𝑠𝑝 | + |𝑉𝐺𝑆,𝑀3 |
(2)
Therefore, the minimum power supply required is:
𝑉𝐷𝐷 − 𝑉𝑆𝑆 > 2|𝑉𝐺𝑆 | + 2|𝑉𝐷𝑆 |
(3)
From (1), (2), and (3), we can see that, the complementary pair extends the
common-mode input voltage range to rail-to-rail by including the common-mode input
voltage range of both NMOS and PMOS pairs.
However, the complementary input pairs lead to an obvious drawback: the
variation of the input stage transconductance gm with the change of the common mode
input voltage from rail to rail. To understand this, let us assume
𝑔𝑚𝑛 = 𝑔𝑚𝑝 = 𝑔𝑚
(4)
where gmn and gmp represent the tranconductance of the N-channel and P-channel input
differential pair in their saturation region. Figure 2 shows the variation of the
transconductance as a function of common-mode input voltage.
3
Figure 2. gm variation over rail-to-rail common-mode input voltage
The variation of the transconductance of the input stage shown above is a
consequence of the complementary input pairs operating in the intermediate region, as
both the NMOS and PMOS contribute to the transconductance in this region. The total
transconductance of the input stage in this region is:
𝑔𝑚 ,𝑡𝑜𝑡𝑎𝑙 = 𝑔𝑚𝑛 + 𝑔𝑚𝑝 = 2𝑔𝑚
(5)
The change in gm,total as a function of common mode input voltage results in
additional nonlinear distortion of the amplifier. It directly leads to the variation of the
gain and concurrently the variation in the unity gain bandwidth 𝑤𝑢 as shown in (6),
preventing the optimal frequency compensation [2].
4
𝑤𝑢 =
𝑔𝑚
𝐶𝑐
(6)
where CC is the compensation capacitor. To keep a constant 𝑤𝑢 , when the
transconductance is doubled, the compensation capacitor has to be doubled at the same
time which is not feasible.
Various topologies have been used to achieve a constant gm of the input stage
while maintaining rail-to-rail operation [1]–[16]. Some of the past methods include a
three-times current mirror [1], square root current control [2], gm control using multiple
input pairs [2], max and min circuits [3], robust constant-gm independent of
transconductance ratio [4], transition region overlapping constant-gm technique [6], and
reference gm constant-gm techniques [7]. Modern papers have achieved lower voltage
supply and lower power consumption while also developing rail-to-rail ideas on a
different process, for example, the application of native transistors whose VTH is smaller
than 0 [8, 9]. Ramirez-Angulo used the floating gate input transistors to the
complementary input stage [12], Lu proposed dual complementary differential pairs railto-rail input stage with offset cancellation [14], and Lu also presented a 1-V rail-to-rail
constant gm op amp by regulating the sum of tail currents for input pairs to be constant
[16]. Some detailed design approaches introduced will be analyzed in detail in Chapter 2.
5
1.3 Organization of this Thesis
In this paper, a new rail-to-rail constant gm input stage for a +0.6 V CMOS op
amp will be presented, which is much reduced in complexity when compared to the stateof-the-art literature. The constant gm input stage is based on the implementation of current
division and is realized by a simple and commonly used circuit block: the push-pull
inverter. The input stage is then be implemented in a unit-gain buffer.
Chapter 2 details previous approaches to the constant-gm problem, and analyzes
the advantages and disadvantages of each design for rail-to-rail input stages.
Chapter 3 gives the new architecture of rail-to-rail, constant-gm input stage for low
voltage low power CMOS op amps. Principles of operation are explained for the new
architecture of input stage. The simulation results are shown in Cadence using TSMC
0.18um technology and the summary of performance is made with some important
parameters.
Chapter 4 describes the application of low voltage low power op amps. This
chapter specifies several common applications for low voltage low power op amps and
also the expected applications by the author.
Chapter 5 concludes the thesis and outlines future work.
6
CHAPTER 2
COMPARATIVE STUDY WITH PREVIOUS APPROACHES
In this section, several typical constant-gm techniques which were published in the
past and were highly cited are described as an introduction of previous work.
2.1 Maximum and minimum circuits
Hwang, Motamed, and Ismail [3] presented a constant-gm technique by basing the
design on processing currents instead of the tail current. The basic idea is to choose the
maximum gm to be the nominal constant gm of the input stage as shown in Figure 3.
Figure 3. Maximum gm selection
7
Two cases were realized and simulated. The first one is the AC signal processing
case. The maximum circuits were used to choose the maximum AC current out of each
differential pair, NMOS or PMOS, and then send the signal to the output stage:
𝐼𝑜𝑢𝑡 = 𝑀𝑎𝑥 𝑖𝑑𝑛, 𝑖𝑑𝑝 = 𝑔𝑚 ,𝑚𝑎𝑥 ∙ 𝑉𝑑
(7)
where 𝑖𝑑𝑛 and 𝑖𝑑𝑝 represent the AC current from NMOS and PMOS pairs, and 𝑉𝑑 refers
to the differential input (Figure 4).
VDD
Ibiasp
Vin+
M1
M3
M4
Ibiasn
idn
Max gm
Selecting
M2
Vin- Circuits
idp
VSS
Figure 4. Rail-to-rail input stage with max gm selecting circuits
We divide the whole common mode input range into the lower region,
intermediate region and upper region corresponding to the part close to negative supply
8
rail, the part when VCM is around the middle rail and the part close to positive supply rail.
We can see from the authors’ simulation that the principle works for the whole range of
VCM by selecting the maximum AC signal.
The other case is to process the AC signal current with the DC bias current which
in [3] is referred to Total Instantaneous Current (TIC case). The minimum circuits instead
of the maximum circuits were used to feed the minimum current (DC+AC) of the
complementary pair into the output. By subtracting the DC current in the cascade stage,
the AC current containing the information of gm, max is extracted at the output stage.
In conclusion, the main advantage of the above constant gm design is the
continuous operation mode of the circuits compared to the switching circuits realization
published before [1]. The switching circuits, by turning on and off transistors, lead to the
distortion and higher variation of gm. One of the disadvantages of the max-min circuit is
the area penalty and higher power consumption in the AC case which implements 4
current mirrors in the input stage.
It is important to mention that the idea of circuits might only work when the
transition region of gmn and gmp is not overlapped. Consider the situation where gmn and
gmp look as shown in the Figure 5, even if the maximum gm is chosen, the value of it in
the transition region is still lower than the nominal constant gm value. The above situation
happens when the supply voltage is too low to supply 2VGS+2VDS,sat.
9
Figure 5. Transconductance overlapping in transition region
2.2 Constant-gm with independence of transconductance factor
Skurai and Ismail [4] introduced 3 kinds of current bias circuits to achieve the
constant gm. The total transconductance of the input stage, gmt is defined by gmn + gmp
where gmn stands for N-type transconductance while gmp stands for P-type
transconductance.
The 3 kinds of current bias circuits have a common unit cell shown in Figure 6
where the sum of Vsgp+Vgsn is designed to be constant and hence the sum of gmn+gmp.
In short, the constant gm is achieved by maintaining a constant sum of the voltages which
does not require gmn = gmp in the middle rail and which is independent of the ratio of
transconductance factors.
10
Vs
gp
V gs
n
Figure 6. Constant summing of VSGP+VGSN
The first bias circuit in Figure 7 directly provides a biasing voltage VC on the
source of PMOS transistor to maintain the following equation:
𝐼𝑀𝑝 1
𝑉𝐶 = 𝑉𝑠𝑔𝑝 + 𝑉𝑔𝑠𝑛 = 𝑉𝑇𝐻𝑝 +
𝐾𝑝
+ 𝑉𝑇𝐻𝑛 +
𝐼𝑀𝑛 1
𝐾𝑛
(8)
where
1
𝑊
2
𝐿
𝐾𝑛 = 𝜇𝑛 𝐶𝑜𝑥 ( )𝑛
(9)
and
1
𝑊
2
𝐿
𝐾𝑝 = 𝜇𝑝 𝐶𝑜𝑥 ( )𝑝
11
(10)
VC
Ip
Vs
gp
Mn1
Mp1
V gs
In
n
Mn2
Mn3
Figure 7. VC biased constant gm biasing circuits
Since IMn1 = Ip, which is the current source of PMOS differential pair, and IMp1 =
In the current sink of NMOS differential pair gives the result:
𝐾𝑛 𝐾𝑝 𝑉𝐶 − 𝑉𝑇𝐻𝑝 −𝑉𝑇𝐻𝑛 =
𝐾𝑛 𝐼𝑛 + 𝐾𝑝 𝐼𝑝
(11)
where the right side is constant without satisfying 𝐾𝑛 = 𝐾𝑝 , the transconductance factor
of each input pair.
The authors then proposed the second type of biasing circuits as shown in Figure
8 which were modified and used to prevent the current sink going into weak inversion
region in the authors’ simulation.
12
In+Id
Ip
Ic
V
Mn4
sg
p’
V
p
Mn1
Mp1
Mp2
n
V gs
sg
’
V gs
In
n
Id
Mn2
Mn3
Figure 8. Current biased constant-gm biasing circuits
From the symmetry, we can see that:
𝑉𝑔𝑠𝑛 + 𝑉𝑠𝑔𝑝 = 𝑉𝑔𝑠𝑛 ′ + 𝑉𝑠𝑔𝑝 ′
(12)
and
𝑉𝑇𝐻𝑝 +
𝐼𝑀𝑝 1
𝐾𝑝
+ 𝑉𝑇𝐻𝑛 +
𝐼𝑀𝑛 1
𝐾𝑛
= 𝑉𝑇𝐻𝑝 +
13
𝐼𝑀𝑝 2
𝐾𝑝
+ 𝑉𝑇𝐻𝑛 +
𝐼𝑀𝑛 4
𝐾𝑛
(13)
and hence
2𝐼𝐶 𝐾𝑝 + 2𝐼𝑑 𝐾𝑛 =
2𝐼𝑛 𝐾𝑛 + 2𝐼𝑝 𝐾𝑝
(14)
is satisfied by cancelling VT from the former equation and multiplying 2𝐾𝑝 𝐾𝑛 to both
sides.
In the third method, the authors make the transistors in a loop (see Figure 9).
Applying KVL to the loop, we get:
𝑉𝑔𝑠𝑛 + 𝑉𝑠𝑔𝑝 = 𝑉𝑔𝑠𝑛 ′ + 𝑉𝑠𝑔𝑝 ′
14
(15)
Ip
Ic
Id
In
Mn1
Mn2
Vs
n’
V gs
gp
g
Vs
’
V gs
p
n
Mp1
Mp2
Figure 9. Constant gm biasing circuit with voltage drops in loop
which is still satisfied and hence guarantees the constancy of gm in the same way as
method 2.
Above all, the advantage of the design is its special view into the independence of
the ratio of Kn and Kp where
1
𝑊
2
𝐿
𝐾𝑛,𝑝 = 𝜇𝑛,𝑝 𝐶𝑜𝑥 ( )𝑛,𝑝
which varies from run to run even in the same process.
15
(16)
2.3 Overlap transition regions
Wang [6] proposed a constant-gm technique for rail-to-rail op amp input stages by
overlapping the transition region of the tail current for both of the complementary pairs.
Two methods are used. The first method is to move the upper boundary of the
transition region, 𝑉𝑛 +, to the right to be the same as the upper boundary of the PMOS
transition region, 𝑉𝑝 +, while the lower boundary of PMOS transition region, 𝑉𝑝 − is
moved to overlap the lower boundary of the NMOS transition region, 𝑉𝑛 −. In the above
statement (see Figure 10), the transition region of the tail current is defined when the
transistor supply tail current is in linear region while the input pairs are in saturation
region. Under proper design, the transition regions of the complementary input pairs will
overlap each other. The variation of gm which was from the increment of
𝐼𝑛 can be
cancelled by the recession of 𝐼𝑝 and vice versa.
The boundary of the transition region mentioned above and the tail current in the
linear region is derived by the authors to be a function of only VG_MBN which is the bias
voltage of current sink for NMOS differential pair, VG_MBP which is the bias voltage of
the current source for PMOS differential pair, VCM, the supply voltages VDD and VSS, and
the process parameters such as the threshold voltage and the transconductance factor. The
former two parameters, VG_MBN and VG_MBP can be properly designed to achieve the
required overlapping.
16
Figure 10. Constant gm technique with overlapping in transition region
The method above looks very direct and easy to realize. However, the authors
find the disadvantage of it during the simulation. Given certain supply voltage and bias
current, the most constant gm is achieved when the transconductance factor, β , is equal to
9 µA/V which leads to a small aspect ratio smaller than one or close to one for NMOS
pair and PMOS pair respectively. Regardless of the good cancellation between 𝐼𝑛 and
𝐼𝑝 in the transition regions, the small aspect ratio obviously leads to two disadvantages.
One is the diminished noise performance. We know that the input referred noise is
inversely proportional to the input transcoductance which is determined by the square
root of the product of β and the tail current. Small β decreases the related
transconductance value and hence increase the input referred noise. The other
17
disadvantage is the sensitivity of the circuit to mismatch which increases under the design.
With a small β , even a small difference ∆β between βn and βp will make ∆β/β look large.
In this case, the authors proposed the other method by applying the DC shifter to
the input, to avoid reducing β which is proportional to the current slope in the transition
region. From Figure 11, we can see that the transition region of PMOS tail current is
shifted to the left to overlap the transition region of NMOS tail current.
Figure 11. Constant gm technique with transition region shifting
The cancellation happens by proper design of ∆𝑉𝑠𝑕𝑖𝑓𝑡, the value of the voltage
that the upper/lower boundary of PMOS transition region shifts, in order to make sure
that gm would not either exceeds the nominal constant value or being too small for the
constant value. We can see from Figure 12 that the DC shifter is realized by adding one
18
more PMOS transistor to each side of the pair and applying the input signal directly on
the shifter. In other words, the two more transistors from DC shifter added to each side of
PMOS differential pair consumes more head room which made it easier to drive the tail
current into transition region in certain voltage regions of lower VCM.
VDD
Ibiasp
M3
M1
M2
Vin+
M4
Output
stage
VinIbiasn
VSS
Figure 12. Constant gm circuits implementing with DC shifter
2.4 Constant reference gm
In Duque-Carrillo [7], a robust and universal constant-gm technique is proposed
by which the rail-to-rail amplifier presents a constant-gm performance over the entire
common-mode input range, -1.5 V to 1.5 V.
19
To realize the circuit, the paper introduced a reference transcoductance value,
gmp,ref, which is the nominal value of the sum of the transconductance of the input
complementary pairs. We then have:
𝑔𝑚𝑝 ,𝑟𝑒𝑓 = 𝑔𝑚𝑝 + 𝑔𝑚𝑛
(17)
The reference circuit has the same PMOS pair with the input PMOS pair and they
also share the same load. The bias voltages on the reference circuits, PMOS differential
pair, and NMOS differential pair were generated from a voltage division circuit on the
left side of the circuits. The actual input signal is applied to the current monitor circuits
which controls the tail current of the PMOS input pairs (Figure 13). Under such
conditions, a feedback loop is given where the sum of the signal currents from reference
circuits and complementary pairs are used to control the tail current of the NMOS input
pairs to maintain the constant gm. From (17), we can see that when IBP, the tail current of
PMOS input pair which changes as a function of VCM, is applied to the current monitor
circuit monitoring IBP, gmp changes at the same time. However, the summing signal
current will control the current sink of NMOS input pair to change gmn at the same time,
by which the feedback maintains the sum of gmp + gmn always equal to gmp,ref.
From the above comparison, we can see a general trend of the constant-gm design
is having the circuits robust and universal. Being robust refers to the quality of accuracy
that the circuit can maintain under any condition for matching the n-type and p-type
20
transistors [7]. Being universal refers to the design fitting any type of input transistors
(MOS or BJT) and the operation regions. [7]
Figure 13. Constant gm technique with reference value
2. 5 Native transistor
Lee [9] proposed realizing a rail-to-rail constant gm input stage for CMOS
amplifier using a new technology to eliminate the shunt effect brought by the native
transistors. The idea is to set a VCM threshold voltage, above which the normal
differential NMOS pair operates, and below which the native differential NMOS pair
operates. To eliminate the shunting effect brought by the native differential pair to the
21
normal pairs when the native one is in triode region, a technique is proposed by turning
off the cascade transistors to cut the current path off. Based on the cooperation between
the normal input pair and natural input pair, a very low supply voltage of 0.65V is
achieved in a conventional CMOS 0.18µm process (Figure 14).
VDD
M1, M2, Normal NMOS differential pair;
M3, M4, Native NMOS differential pair.
idn
Shunting
Effect
Elimination
M3
Vin-
M1
M4
M2
Vin-
Output
Stage
Vin+
Ibiasn2
Ibiasn1
VSS
Figure 14. Native input pair implementation for rail-to-rail input stage
2.6 Weak inversion operation maintaining constant sum current
Lu [16] achieved a constant-gm rail-to-rail input stage operating in weak inversion
by realizing a gm control circuit maintaining the sum of current in the complementary
differential pair to be constant. In Figure 15, we have
22
𝐼𝑇 = 𝐼𝑁 + 𝐼𝑃
(18)
gm Control
Circuit
Summing
circuits
IP
Vin-
Vin+
IN/2
IN/2
IT
Figure 15. Rail-to-rail constant-gm input stage operating in weak inversion with constant
sum of current for differential pair
23
CHAPTER 3
A NEW CONSTANT- gm RAIL-TO-RAIL INPUT STAGE
DESIGN
Instead of increasing the gm in the lower and upper parts of the input common
mode voltage by a factor of two as done by previous authors [1], in this thesis we choose
to decrease the gm by a factor of two in the intermediate part as shown in Figure 16.
Under such conditions, the tail current of the intermediate stage needs to be decreased by
a factor of 4 under strong inversion operation and a factor of 2 under weak inversion
operation in comparison to the current maintained in the lower and upper parts of the
common-mode input voltage.
24
Figure 16. gm versus common-mode input voltage for complementary input stage
3.1 Strong inversion operation
In strong inversion, we have
g m  KI tail for K  K N ,P   N ,P COX
W
L N ,P
(19)
where W/L is the aspect ratio of the function transistor,  N , P is the mobility, COX is the
gate oxide capacitance, and Itail corresponds to the tail current of the input pairs. In order
to make g mn  g mp , from (19) we can see
25
W
L N   P COX
W
 N COX
LP
(20)
In order to decrease the gm by a factor of 2, we need to decrease the intermediate
region tail current I tail by a factor of 4 in the square root of (19). An application of this
idea is shown in Figure 17. Assume that the tail current in the lower and upper regions of
the input common mode voltage is I. The current is then reduced to ¼I by taking ¾I of
the tail current from the source of PMOS pair and feed it into the sink of NMOS pair
when the common mode input is in the intermediate stage.
VDD
Vbias1
I
M7
1/4I
¾I
Current
Division
Circuit
(gm
control)
VCM
VCM
VCM
VCM
M1
M3
M4
¾I
M2
1/4I
I
Vbias2
M8
VSS
Figure 17. Rail-to-rail input stage with gm control by current division
26
Extending the principles of transistor current division [17], the current division
block in Figure 17 is then implemented in the circuit shown in Figure 18. The gm-control
is realized by means of the push-pull inverter M5 - M6 connected between the drain of
M7 and the drain of M8. The amplifier also consists of the complementary input stage
M1 - M4, the M11 – M18, and the output stage M19 – M20. Transistors M9 – M10 are
used to bias the circuit. Controlled by VCM, the PMOS transistor M5 of the inverter has
the same VGS as the PMOS differential input transistors M3 – M4, and the NMOS
transistor M6 of the inverter shares the same VGS with the NMOS differential input
transistor M1 - M2.
VDD
Vbias 3
I
Vbias1
M7
M9
3/4*I (S)
1/2*I (W)
VCM
M5
M11
M12
M13
M14
VCM
VCM
VCM
Vo
VCM
RZ
R
M1
Ibias
M19
1/4*I (S)
1/2*I (W)
M4
M3
CC
CL
M2
M6
GND
M15
M16
1/2*I (W)
3/4*I (S)
1/4*I (S)
1/2*I (W)
I
Vbias2
M10
Vbias4
M17
M8
M18
M20
VSS
Figure 18. gm control by the implementation of a push-pull inverter which drives 3/4
current from the tail current of the complementary input pairs operating in strong(S)
inversion and 1/2 current from the tail current of the input pairs operating in weak(W)
inversion.
27
In this case, when VCM is swept from rail to rail, the circuit works under the
following three parts:
Part 1: In the lower part of the VCM input range, i.e. when VCM is close to the
negative supply rail, the PMOS input is on while the NMOS input does not have enough
voltage drop on VGS to operate. For the inverter, the PMOS is on while the NMOS is off.
Hence, there is no current flow through the inverter. The currents and gm values can be
seen as
I tail, p  I
g m  g mp  KI
(21)
(22)
Part 2: In the intermediate part of the VCM input range, i.e. when VCM is in the
middle-rail, the PMOS input pair and the NMOS input pair are both on. To the inverter,
the operating PMOS and NMOS pair builds up a path for current division from the tail
current of the input pair. The W/L ratio of M5 is 6 times that of M3 and M4, and the W/L
ratio of M6 is 6 times that of M1 and M2. Since the inverter shares the same VGS, it drives
¾ I from the drain of M7 and feeds this ¾ I into the drain of M8. The resulting ¼ I left
from the drain current is used for the operation of the PMOS input pair while the same
amount is left for the NMOS input pair. The following equations describe the operation
of Part 2
28
3
1
I tail,n  I tail, p  I bias  I Inverter  I  I  I
4
4
gm 
1
1
1
1
g mp  g mn  K ( I )  K ( I )  KI
2
2
4
4
(23)
(24)
Part 3: In the upper part of the VCM input range, i.e. when VCM is close to the
positive supply rail, the NMOS input is on while the PMOS input does not have enough
voltage drop on VGS to operate. To the inverter, the NMOS is on while the PMOS is off.
Hence, there is no current flow through the inverter. The currents and gm values can be
seen as
I tail,n  I
(25)
g m  g mn  KI
(26)
3.2 Weak inversion operation
The above discussions are based on the strong inversion. However, the same
principle could be easily implemented in the weak inversion.
The transcondunctance gm in weak inversion is proportional to the tail current
gm 
I tail
2U T
29
(27)
where U T is the thermal voltage, and  is the weak inversion slope. Therefore,
g m  g mp  g mn 
I tail, p
2U T

I tail,n
2U T
(28)
To achieve a constant gm, we can simply adjust the W/L ratio of M5 to be 2 times
that of M3 and M4, and the W/L ratio of M6 as 2 times that of M1 and M2. Under such
conditions, the current driven from the drain current and fed into the source current
1
would be 𝐼 as shown in Figure 18, and constant gm will be achieved.
2
3.3 Advantages and disadvantages
In summary, the push-pull inverter simply works in the intermediate stage of VCM
input range where it drives ¾ current from the drain of current source transistor to force
the tail current of the PMOS and NMOS input pairs operating in strong inversion to be
reduced by a factor of 4, and drives ½ current if PMOS and NMOS input pairs operate in
weak inversion. The constant gm control is then achieved.
As we can see from Figure 18, the simplicity of our design is obvious compared
to the state-of-the-art literature. Only two transistors were used in the gm control circuits.
Besides with the simplicity in constant gm design, an advantage of the proposed
gm control by current division is its low power consumption. To reduce the power
30
consumption in a circuit, it is necessary to decrease the complexity of the design while
maintaining low supply voltages. The proposed gm control only introduces one additional
current path between the supply rails, which greatly reduces the power consumption
when compare to the previous literatures.
One disadvantage in this design is the degradation in noise performance as a
result of deceasing the input transconductance from 2gm to only gm. Considering that the
input referred noise is inversely proportional to the transconductance of the input
transistor, the design relatively increases the input referred noise.
3.4 Simulation result and discussion
Cadence simulation is carried out for the push-pull inverter gm-controlled rail-torail input op amp of Figure 18. TSMC 0.18 µm CMOS technology is used in the
simulation. In strong inversion, the complementary input pairs implement twice the
minimum channel length 0.18µm and have a W/L ratio of 0.9µm /0.36µm for NMOS
input transistors and 5µm /0.36µm for PMOS input transistors. 1MHz differential sine
waves are used as small input signals. The power supply is Vdd = 0.6V and Vss = -0.6V.
The value of the biasing current Ibias is 4 µA, whose value could be adjusted by the
resistor R shown in Figure 18. The power consumption is around 20.1 µW when VCM is
in the middle of the supply rails. The input stage is also implemented in a unit-gain buffer
application where the step response is done and a slew rate of 2.5V/µS is achieved by
feeding a 5MHz square wave. The constant-gm simulation over the entire common-mode
31
input range is also done for weak inversion operation. A nearly constant-gm with the
maximum variation of 3.7% is achieved
3.4.1 Strong inversion simulation result
Looking at Figure 19, VCM is swept from the negative rail to the positive rail and
the simulation of gm is also performed. The top curve gmtotal is the sum of the gmn and gmp.
We can see that the maximum variation of gm is less than 2.5%. Multiple input frequency
simulation is then conducted with the input frequency of 1MHz, 100MHz and 1GHz. The
results show that the transconductance performances are the same as shown in Figure 19,
which verifies that the design is suitable for high frequency applications.
Figure 19. The transconductance of the CMOS input stage in strong inversion using the
input sine waves of frequency 1MHz, 100MHz and 1GHz
32
Figure 20 presents the corner simulation of gm performance of the input stage as a
function of common-mode input stage.
Figure 20. gm performance simulated at corners at room temperature
Considering that the constant gm control circuit is heavily depending on the ratio
of the transconductance factors for the complementary pair, a mismatch analysis is done
by doing Monte Carlo simulation on the performance of gmtotal of the input stage on the
process and mismatch. The standard deviation is 19% from the average value by 100 runs
(see Figure 21).
33
Figure 21. Monte Carlo simulation of gmtotal under 100 runs on process and mismatch
Figure 22 shows that 85 dB of low frequency gain, 5.5MHz gain bandwidth
product, and 89.39ºphase margin is achieved after frequency compensation with a load
capacitor of 20pF.
34
Figure 22. Frequency response with Vp = 2mV differential sine wave input
Implementing the op amp as a unity gain buffer, we can see from the DC response
in Figure 23 that the op amp is highly linear, allowing both the input and output to swing
with minimal distortion.
Figure 24 shows the step response for the designed unit gain buffer. The subfigure
at the upper part shows the output step compared to the input of a + 0.6V amplitude and 5
MHz square wave shown in the lower part of the figure. The slew rate is 2.5 V/µs for
both rising and falling edges.
35
Figure 23. Unit gain transfer curve for the op amp
Figure 24. Step response of unit gain buffer
36
3.4.2 Weak inversion simulation result
Simulation of operation in weak inversion is also conducted. Figure 25 is the gm
performance of the input stage as a function of common-mode input voltage. The
corresponding maximum variation of gmtotal is 3.7%.
Figure 25. The transconductance of the CMOS input stage in weak inversion
37
3.5 Summary
Table 1. Summary Table with comparison of important parameters of op amp (This work
indicates the simulation in strong inversion)
38
CHAPTER 4
APPLICATIONS OF LOW VOLTAGE LOW POWER RAILTO-RAIL OP AMPS
4.1 Instrumentation amplifiers
An instrumentation amplifier is usually used for measurement which implements
input buffers to provide maximum input impedance. A two amplifier instrumentation
amplifier [18] is shown in Figure 26.
R2
R1
R4
Vin-
+
R3
Vout
+
Vin+
Figure 26. Two amplifier instrumentation amplifier
Assuming R1 = R3 and R2 = R4, we can see in Figure 27 that the gain of the
amplifier is:
39
𝐴𝑣 = 1 +
𝑅4
(29)
𝑅3
Very high matching ratio of R1/R3 and R2/R4 is required to achieve a high
CMRR [18].
Adding another amplifier, the classic three amplifier instrumentation amplifier is
shown in Figure 27. Except Rgain, the rest of the resistors are made to be the equal of R
value. We can see that with the feedback, the voltage drop across Rgain is made to be (Vin+
- Vin-) and the current caused by the drop is (Vin+ - Vin-)/ Rgain which does not follow into
the input due to high input impedance. Hence, the same current goes from node Vout1 to
Vout2 and results voltage drop:
𝑉𝑜𝑢𝑡 1 − 𝑉𝑜𝑢𝑡 2 =
𝑉𝑖𝑛 − −𝑉𝑖𝑛 +
𝑅𝑔𝑎𝑖𝑛
∙ (2𝑅 + 𝑅𝑔𝑎𝑖𝑛 )
(30)
and from the third amplifier:
𝑉𝑜𝑢𝑡 = 𝑉𝑜𝑢𝑡 2 − 𝑉𝑜𝑢𝑡 1 + 𝑉𝑅𝐸𝐹
(31)
The above results in the gain of the amplifier and the output expression to be:
𝐴𝑣 = (1 + 2
and
40
𝑅
𝑅𝑔𝑎𝑖𝑛
)
(32)
𝑉𝑜𝑢𝑡 = (𝑉𝑖𝑛 + − 𝑉𝑖𝑛 −) ∙ 𝐴𝑣 + 𝑉𝑅𝐸𝐹
(33)
4.2 Bio-medical Application
Rail-to-rail op amps are widely used in implantable biomedical devices which
require very low voltage supplies and very low power consumption. Recording biopotentials from microelectrode-arrays, the op amp has to have a low input referred noise
since the frequency range of the signal is usually just from a few Hz to kHz [9]. An
example is given in Lee [9] which is introduced in the section of comparative study.
4.3 Portable devices
Besides the above application types, generally, portable devices driven by
batteries, such as cell phones’ communication circuits, are also in a great demand of low
voltage low power design.
An expected application by the author is that instead of achieving constant-gm, the
variation by a factor of 2 in the transconductance of the input stage is utilized to have a
controllable transconductance amplifier. As an example, when a certain input VCM, the
transconductance looking into the output is gm while with another VCM input the
transcoductance presented is 2gm.
41
Vin-
Vout1
+
-
R
R
R
-
Rgain
Vout
+
Vin+
+
R
VREF
Vout2
R
R
Figure 27. Three amplifier instrumentation amplifier
42
CHAPTER 5
CONCLUSION AND FUTURE WORK
5.1 Conclusion
The thesis presents a new architecture of rail-to-rail input stage for a CMOS low
voltage low power op amp based on the current-mode design. The complexity of the
design is largely reduced compared to the state-of-art literature. Both strong inversion
and weak inversion operations analysis are given. Simulations on Cadence are done using
TSMC 0.18µm technology. The total transconductance of the input stage is almost
constant over the entire common mode range from rail-to-rail. The maximum variation of
gm in strong inversion is 2.5% and is 3.7% in weak inversion operation. With a load
capacitor of 20pF, the open loop gain is 85 with a GBW of 5.5MHz when simulating in
strong inversion operation.
To compare with the previous literature and to get an overview of the other work,
a comparative study with detailed analysis was done. We have discussed the advantages
and disadvantages of the maximum-minimum circuit constant-gm technique, constant-gm
independent of transconductance ratio technique, overlapping transition region constantgm technique, constant reference gm technique, native transistor application, and a
43
constant–gm technique achieving constant-gm in weak inversion operation. The common
aspects, the advantages and disadvantages of the designs are given in the comparative
study.
A look into the common applications of the low voltage low power design has
been given. Instrumentation amplifiers, biomedical implantable device applications and
portable device applications together with an expected application by the author are
presented.
One prospect of the future work will be the design of gain stage and the output
stage to complement the rail-to-rail input design presented in the thesis.
5.2 Future Work--a self-biased folded cascode stage
A self-biased folded cascode stage is proposed in this thesis as future work. In
Figure 28, two current mirrors are stacked where the minimum output is VT + 2VDS, SAT
where VT refers to the threshold voltage of the current mirror (assuming the same) while
VDS, SAT refers to the saturation voltage of the output transistors.
Figure 29 shows a wide swing cascade stage where the minimum output voltage
has been reduced to VT + VDS, SAT. VB provides the bias voltage for the current mirror.
The proposed wide swing self-biased folded cascade stage is shown in Figure 30.
MN_1, MP_1, MP_4 and MN_4 are diode connected. MN_1 and MP_1 share the same
drain and the same as MP_4 and MN_4. The design is such self-biased and only needs
two supply rails but no bias voltages. With this, the gates of MP_2 and MP_3 as well as
44
MN_2 and MN_3 are connected. Assuming the same W/L ratio, MP_2 and MP_3 can be
considered as one transistor where the channel length L is doubled, as can MN_2 and
MN_3. Let
2𝐼
𝑉𝐷𝑆,𝑆𝐴𝑇 =
𝜇 𝐶𝑂𝑋 𝑊
(34)
𝐿
The minimum output voltage will be
∆𝑉 =
2𝐼
𝜇 𝐶𝑂𝑋 𝑊
= 2𝑉𝐷𝑆,𝑆𝐴𝑇
(2𝐿)
which is smaller than 2VDS, SAT provided in Figure 29 by (2 - 2) VDS, SAT.
45
(35)
Iin
Iout
MN_1
MN_2
VT+2VDS, SAT
MN_4
MN_3
Figure 28. Cascode current mirror
Iin
Iout
MN_1
MN_2
VB
VT+VDS, SAT
MN_4
MN_3
Figure 29. Wide Swing Cascode current mirror
46
VS
G
VDD
idn
Ibiasp
Vin+
M1
M3
M4
M2
MP_1
MP2
MN_1
MP_3
V GS
Vin-
+
MP_4
MN_2
√2VDS, SAT
Ibiasn
idp
MN_4
VSS
Figure 30. Proposed self-biased folded cascode stage
47
MN_3
_
BIBLIOGRAPHY
1. R. Hogervorst, J. P. Tero, R. G. H. Eschauzier, J. H. Huising. A Compact PowerEfficient 3V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell
Libraries. IEEE Journal of Solid-State Circuits 1994; 29(12): 1505 – 1513.
2. R. Hogervorst, J. H. Huijsing. Design of Low-Voltage Low-Power Operational
Amplifier Cells. Boston: Kluwer Academic Publishers, 1996.
3. C. Hwang, A. Motamed, M. Ismail. Universal constant-gm input-stage architectures
for low-voltage op amps. IEEE Transactions on Circuits and Systems I: Fundamental
Theory and Applications 1995; 42(11): 800 – 811.
4. S. Skurai, M. Ismail. Robust Design of Rail-to-Rail CMOS Operational Amplifiers
for a Low Power Supply Voltage. IEEE Journal of Solid-State Circuits 1996; 31(2):
146-156.
5. G. Ferri, W. Sansen. A Rail-to-Rail Constant-gm Low Voltage CMOS Operational
Transconductance Amplifier. IEEE Journal of Solid-State Circuits 1997; 32
(10):1563 – 1567.
6. M. Wang, T. L. Mayhugh Jr, S. H. K. Embabi, E. Sanchez-Sinencio. Constant-gm
Rail-to-Rail CMOS Op-Amp Input Stage with Overlapped Transition Regions. IEEE
Journal of Solid-State Circuits 1999; 34(2): 148 – 156.
48
7. J.F. Duque-Carrillo, J.M. Carrillo, J.L. Ausin, E. Sanchez-Sinencio. Robust and
Universal constant-gm circuit technique. Electronics Letters 2002; 38(9): 396—397.
8. E. K. F. Lee, E. Matei, R. Ananth. A 0.9 V Rail-to-Rail Constant gm Amplifier for
Implantable Biomedical Applications. Proceedings of 2006, IEEE International
Symposium on Circuits and Systems, Island of Kos, Greece, September 2006; 653656.
9. E. K. F. Lee, A. Lam, T. Li. A 0.65V Rail-to-Rail Constant gm Opamp for Biomedical
Applications. IEEE International Symposium on Circuits and Systems, Seattle,
Washington, U.S.A., May 2008; 2721 – 2724.
10. S. Yan, J. Hu, T. Song, E. Sanchez-Sinencio. A Constant-gm Rail-to-Rail Op Amp
Input Stage Using Dynamic Current Scaling Technique. IEEE International
Symposium on Circuits and Systems, Kobe, Japan, May 2005; 2567 - 2570.
11. T. Song, S. Yan. A Robust Rail-to-Rail Input Stage with Constant-gm and Constant
Slew Rate Using a Novel Level Shifter. IEEE International Symposium on Circuits
and Systems, New Orleans, U.S.A., May 2007; 477 – 480.
12. T. Stockstad, H. Yoshizawa. A 0.9-V 0.5-µA Rail-to-Rail CMOS Operational
Amplifier. IEEE Journal of Solid-State Circuits 2002; 37 (3): 286 - 292.
13. J. Ramirez-Angulo, S. Balasubramanian, A. J. Lopez-Martin, R. G. Carvajal. Low
Voltage Differential Input Stage With Imporved CMRR and True Rail-to-Rail
Common Mode Input Range. IEEE Transactions on Circuits and Systems – II:
Express Briefs 2008; 55(12): 1229- 1233.
14. C.-W. Lu. A Rail-to-Rail Class-AB Amplifier With an Offset Cancellation for LCD
49
Drivers. IEEE Journal of Solid-State Circuits 2009; 44(2): 525-537.
15. T. Song, J. Hu, X. Li, E. Sanchez-Sinencio, S. Yan. A Robust and Scalable Constantgm Rail-to-Rail CMOS Input Stage With Dynamic Feedback for VLSI Cell Libraries.
IEEE Transactions on Circuits and Systems – I: Regular Papers 2008; 55 (3): 804816.
16. C.-W. Lu, C.–M. Hsiao. 1 V rail-to-rail constant-gm CMOS op amp. Electronics
Letters 2009; 45(11): 529 - 530.
17. K. Bult, G. J. G. M. Geelen. An Inherently Linear and Compact MOST-Only Current
Division Technique. IEEE Journal of Solid-State Circuits 1992; 27(6): 1730 - 1735.
18. Intersil. Appl. Note 1298.
50