International Journal of VLSI Design, 2(2), 2011, pp. 103-106
DESIGN OF A LOW POWER LOW VOLTAGE FULL ADDER
Swapnadip De1*, Angsuman Sarkar2 & C.K. Sarkar3
1*
Meghnad Saha Institute of Technology/ ECE Department, Kolkata, India E-mail: swapnadipde26@yahoo.co.in
2
Kalyani Govt Engg. College/ECE Department, Kolkata, India E-mail: angsuman_sarkar@hotmail.com
3
Jadavpur University/ETCE Department, Kolkata, India E-mail: phy_hod@yahoo.co.in
Abstract: In this paper, 1 bit full adder is built under a new hybrid logic (combination of PTL and CMOS
logic) style, using 14 MOSFETs. Here we use 6transistor XOR-XNOR circuit to implement the full adder.
This full adder offers full voltage swing at every nodes, higher density and high speed than the conventional
CMOS design style. TSPICE is the simulator used for the simulation and bsim3v32 technology is used with
supply voltage=1V and 10MHz frequency. Dual threshold model file (version 49) is used to observe the
o1utput.
Index Terms: XOR-XNOR, full adder, PTL, BSIM32, CMOS
1. INTRODUCTION
Full Adder is a basic block in all digital circuits. A
small change in transistor count, power and delay
will cause a drastic change in the performance of a
large VLSI circuit. The performance of multipliers
depends on the full adder used. The important
parameters to be considered while designing a full
adder are power consumption, delay, area, full
swing operation and performance while cascading
adders in a multiplier structure. The one bit Full
Adder is one of the most widely used building
blocks in all data processing (arithmetic) and DSP
units. With the growing trend for reducing the
power dissipation in VLSI systems and especially
in portable applications, reduction (or scaling) of the
power supply voltage emerges as one of the most
widely practiced measures for low power design.
At lower supply voltages, 1 bit full adder circuit
with low power dissipation, full voltage swing and
high speed becomes important issues. In this paper,
a low power and high speed full adder, based on
pass transistor logic (PTL) and static CMOS logic
style, is proposed for the embedded system.
implemented with 28 Transistors in CMOS
technology. Conventional adder circuits do not
function well below 1V supply [1]. Figure 2 shows
the Complementary Pass-transistor Logic (CPL)
adder. Among the pass transistor logic styles, CPL
has the best performance and the lowest power
delay product [2]. The Transmission Function full
Adder (TFA), which is shown in Figure 3, uses 16
transistors. Pull-up and pull-down logic is used to
drive the load the same as the complementary pass
logic [3]. Figure 4 shows the Transmission Gate full
adder (TG). TG adder includes 20 transistors, and
generates a+b and its complement to produce the
sum and carry signals. It uses complementary input
signals (a, b, c) as the complementary CMOS full
adder [4],[5].
2. LITERATURE REVIEW
Some designs of adder cells can be found in the
Figures 1 to 4. These four different adder cells are
simulated in 0.18 µm CMOS technology and tested
separately. All these cells are optimum in power
dissipation and Power delay product (PDP).
The conventional adder shown in Figure 1 is
Figure 1: Conventional CMOS Full Adder
104
International Journal of VLSI Design
3. DESIGN IMPLEMENTATION
The truth table for the full adder circuit is shown
below,
Table. I
Truth Table of Full Adder
Figure 2: Complementary Pass-Transistor Logic (CPL) Adder
A
(i/p)
B
(i/p)
C
(i/p)
SUM
(o/p)
CARRY
(o/p)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
From this truth table we can implement the
conventional Full Adder circuit, by using CMOS
logic style,where
SUM = (A) XOR (B) XOR (C)
CARRY = (AB) + (BC) + (CA)
Hence we have used total 28 MOSFET (14 PMOS
and 14 NMOS)to implement the conventional
circuit. Another design of Full Adder is based on
pass transistor logic (PTL) style.The conventional
and PTL based design of full adder circuits are
shown in Figures 5 and 6.
Figure 3: Transmission Function Adder (TFA)
Figure 5: Conventional Full Adder Circuit with 28 MOSFET
Figure 4: Transmission Gate (TG) CMOS adder
Figure 6: 16 MOSFET Pass Transistor Logic Style
105
Design of a Low Power Low Voltage full Adder
A more efficient design of Full Adder involves
the use of CMOS logic and transmission Gate logic.
If we observe the above truth table carefully, then
we can write;
If
CARRY = B
and
If
and
(A XNOR B) = 1 then SUM = C
(1)
To implement SUM we have to use the equation
(1) and (2). If (A XNOR B) = 1 then SUM = C since
M1 and M2 will behave like a buffer and the TG
pair (M3 and M4) will pass the C to the output node
SUM. If (A XNOR B) = 1 and (A XOR B) = 0 then M1
and M2 will behave like an inverter and pass the
complement of C at the output node SUM.
(A XNOR B) = 0 then SUM = NOT(C)
CARRY = C
(2)
To implement the Full Adder first we have to
implement the XNOR function with minimum
possible number of transistors.The implementation
is shown in Figure 7.
Figure 8. Implementation of Proposed CARRY and SUM
Module
(a)
(b)
Figure 7 (a, b): 6-Transistors XOR & XNOR Gate
For CARRY circuit we can use the same
equations. Hence when (A XNOR B) = 1 and
(A XOR B) = 0 then M1 and M2 both will be ON to
pass the signal from node B to the output node
CARRY. When (A XNOR B) = 0 and (A XOR B) = 1
then M3 and M4 both will be ON to pass the signal
from the node C to the output node CARRY.
4. RESULTS AND OBSERVATIONS
Figure 7 (c): 6-Ttransistor XOR-XNOR(from TSPICE)
Here we use a 6 transistor XOR-XNOR circuit
to implement the Adder. The proposed XOR-XNOR
circuit is shown above. Hence considering XOR
output node first,when A = 0/1 and B = 1/0 then
any one of the PMOS(M1 or M2 ) will be ON to pass
the logic 1 (Vdd) to the output port. When A = B = 1
then both the NMOS (M3 and M4) will be ON to
pass the logic 0 (ground) to the output node. When
A = B = 0, then both PMOS (M1 and M2)will be ON
to pass logic 0 to the output node. As PMOS is
unable to pass logic 0 smoothly, there may be small
logic degradation in XOR node for the A = B = 0 input
combination. But in XNOR output node, as XOR is
inverted we will not get any logic degradation.
Figure 9: Output Waveform of XOR, XNOR, SUM, CARRY
with three Voltage Sources
106
International Journal of VLSI Design
CONCLUSIONS
Figure 10: Power Dissipation Curve with Respect to Time
A new full adder circuit is proposed by using 14
transistors only, possible only due to the use of
6T XOR-XNOR. Though the device count is very
low, yet every node offers full voltage swing.
Another main advantage is very low power
dissipation. So the power delay product is also very
low and of the order of 10-20. However the
limitation is design time since to implement
6 transistor XOR-XNOR circuits we have to use
proper radioed MOSFET. The dual threshold model
file is used for obtaining the results.
The measured power-delay table for every bit
pattern is also shown in Table II.
REFERENCES
Table II
Rise Time Delay and Power Measurement
i/p
Rise time
delay(s) (sum)
Rise time
delay(s)(carry)
P(watt) with
Vdd = 1V
000
not found
not found
5.16E-10
001
1.45E-09
not found
2.78E-10
010
8.68E-09
1.44E-09
1.63E-10
011
1.93E-09
1.52E-09
1.62E-10
100
9.85E-09
not found
6.44E-10
101
1.78E-09
6.92E-09
2.74E-10
110
not found
9.56E-10
5.01E-10
111
1.43E-09
9.90E-10
2.50E-10
Table III
Fall Time Delay and Power Measurement
(Sum and Carry as O/P)
i/p
Fall Time
delay(s) (sum)
Fall time
delay(s) (carry)
Power (watt)
with Vdd = 1V
000
1.17E-09
9.89E-10
1.40E-09
001
not found
not found
2.24E-10
010
1.22E-09
4.34E-09
1.63E-10
011
6.77E-09
not found
1.62E-10
100
1.20E-09
1.04E-09
6.43E-10
101
7.74E-09
1.03E-09
2.76E-10
110
1.16E-09
not found
5.01E-10
111
not found
not found
2.50E-10
[1]
Zimmermann, R. and W. Fichtner, 1997, “LowPower Logic Styles: CMOS Versus Pass-Transistor
Logic”. IEEE Journal of Solid-State Circuits, 32,
pp. 1079-1090.
[2]
Issam, S., A. Khater, “A. Bellaouar and M. I.
Elmasry, 1996 Circuit Techniques for CMOS Low
Power High Performance Multipliers”. IEEE Journal
of Solid-State Circuits, 31, pp. 1535-1546.
[3]
Zhuang, N. and H. Wu, 1992, “A New Design of
the CMOS full Adder”. IEEE Journal of Solid- State
Circuits, 27, pp. 840-844.
[4]
Weste, N. and K. Eshragian, 1993. Principles of
CMOS VLSI Design: A System Perspective, pp. 531.
[5]
Abu-Shama, E. and M. Bayoumi, 1996. A New Cell
for Low Power Adders, In: Proceedings of IEEE
International Symposium on Circuits and Systems,
Atlanta, GA, USA, pp. 49-52.
[6]
U.Ko, P. Balasara and W. Lee, “Low-Power Design
Techniques for High-Performance CMOS Adders”,
IEEE Trans on VLSI Syst, 3, No 2, pp. 327-333, Jun
1995.
[7]
A.M.Shams and M. Bayoumi, “Performance
Evaluation of 1-bit CMOS Adder Cells”, Proceedings
of the IEEE ISCAS '99, Orlando, Florida, USA, May
1999, 1, pp. 27-30.
[8]
A.T.M. Khalid, “A Fast Optimal CMOS Full
Adder”, Proc 39th Midwest Symp on Circuits and
Systems, 1, pp. 91-93, 1996.
[9]
D.Radhakrishnan, “Low-Voltage Low-Power
CMOS Full Adder”, IEE Procd of Circ Dev Sys, 148,
No 1, Feb 2001.