HANA Semiconductor (Ayutthaya) Co. Ltd.
Die Design Rule For Assembly Of Plastic Devices
1.0
1.1
1.2
set up
PURPOSE :
To define the rules to be observed to facilitate review of process ability of devices prior to
production loading.
To provide the recommended and minimum/maximum requirements for die design and
layout of integrated circuit devices and corresponding packages. This design will be
compatible with existing assembly equipment to achieve high reliability and high assembly
yields.
Recommended: Represents normal capability, which is widely available with standard set,
ups and process control.
Minimum/Maximum : Represents leading edge technology with very limited capacity and
requires engineering support on first time build
For minimum/maximum: A price adder may be required since the total cost is higher (longer
time, etc.)
2.0
2.1
SCOPE:
This specification shall be applicable to all packages assembled at Hana Semiconductor
Ayutthaya Co., Ltd.
3.0
3.1
3.2
REFERENCE DOCUMENTS:
Mil-STD-883
PEN003 “ Design Control Procedure ”
4.0
4.1
MATERIALS / EQUIPMENTS / TOOLS NEEDED:
N/A
5.0 REQUIREMENTS / INFORMATION:
5.1 Safety Requirements / Information:
5.1.1 N/A
5.2. Process Requirements / Information:
5.2.1 N/A
5.3
QC Requirements / Information:
5.3.1 N/A
5.4 Environmental Management System Requirements / Information:
5.4.1 N/A
5.5
5.5.1
5.6.
5.6.1
5.6.1.1
Maintenance Requirements / Information:
N/A
Other Requirements / Information:
Responsibilities.
Process engineers are responsible to determine and define Hana machine and process
capability, which shall be the basis for establishing the design, rules as stated in this
specification.
5.6.1.2
Marketing is responsible to ensure that all customers are aware of Hana design rule and
responsible to notify customers on possible assembly yield losses and reliability risks for
products that are out of Hana design rule.
6.0
6.1
PREPARATION / SET UP:
N/A
7.0 PROCEDURES:
7.1 Die/Wafer related design rules
7.1.1 Wafer diameter and wafer thickness
7.1.1.1
Wafer diameter:
Wafer diameter shall be 3”, 4”, 5”, 6” and 8”(76, 102, 127, 152 and 203 mm)
7.1.1.2
Wafer thickness
Wafer thickness is very important to meet the existing assembly equipment capability and to
maintain balanced flow of mold compound between top and bottom cavities at mold process,
and to maintain defined loop height as specified in wire bond specification. The thickness
must be within the design rule. Violation of design rule will cause loss of yield, quality, and
reliability problems. Wafer thickness requirements shall be classified into 2 categories:
A) Wafer thickness per wafer diameter.
Wafer thickness on this category is important for wafer handling at wafer mount , wafer saw
and wafer back grinding process to prevent yield loss and quality/reliability related problems.
Wafer diameter
4
Inch
MM
76 - 102
Wafer thickness(min – max)
Mil
Micron
5 - 30
127 – 762
5- 6
8
127 - 152
203
6 – 30
6 - 30
152 – 762
152 – 762
B)
Wafer thickness per package type.
Wafer thickness per package type is required to obtain a balanced flow of mold compound in
top/bottom mold cavities in conjunction to wire bond material and/or die coat material.
Package type
PDIP 300
PDIP 600
SOIC 150
SOIC 208
SOIC 300
TSOP
TSOT23
SOT23, SC70
MSOP (Standard)
MSOP U (Power pad)
QSOP 150
PLCC
QFP (10x10/14x14)
QFP (14x20)
VSOP
SOT223
LGAB , LGAC (package
thickness 0.55 mm)
SOT89
Min. thickness
See item 7.1.1.2
Section A.
Max. Thickness
Mil
Micron
30
762
30
762
16
406
16
406
25
615
12
305
8
203
9
229
9
229
15
381
16
406
30
762
22
559
29
737
6.5
165
12
305
6.5
165
16
406
Recommended thickness
Mil
15
15
12
12
15
10
7
8
8
12
12
15
15
15
6
10
6
Micron
381
381
305
305
381
254
178
203
203
305
305
381
381
381
152
254
152
13
330
16
8
TO92
QFN / DFN / LGAB
(uDFN : package thickness
0.75 mm)
C.
406
203
13
7
330
178
Maximum thickness with die coat
Wafer thickness of device, which requires die coat is very important to meet the existing
equipment capability and to maintain gap between top of package and coating material at
mold process. The design must be within the wafer thickness design rule. Violation of design
rule will cause yield loss. Wafer thickness with die coat shall be classified by die size.
Die size (mils)
< 100
101-200
> 200
Max. Wafer thickness(mils)
Per thickness in section 7.1.1.2 B
Minus 3 from Max wafer thickness in section 7.1.1.2 B
Minus 5 from Max. wafer thickness in section 7.1.1.2 B
7.1.2 Wafer configuration
7.1.2.1 Scribe Street Geometry
A
Street with
Scribe street
Device
Street without
pattern
Figure 1: Scribe street width (A)
The scribe street opening is defined as the glass free area between the edges of product die
scribe ring. The opening should not contain active circuit elements.
7.1.2.2. Scribe street width
Wafer thickness
Mils
< 16
16 – 25
>25
Micron
< 432
432 – 635
635
Mini mum saw street width
Without test pattern
Mils
2.3
2.5
2.8
Micron
58
64
71
With test pattern
Mils
2.5
2.7
3.0
Micron
64
69
76
Note. For 8L-VSOP of Phillips wafer the scribe street width are not less than 50 micron or
2.0 mils.
7.1.2.3 Scribe street edge
Recommend scribe street edge shall be overlap from active metal: 1.2 mils minimum.
7.1.2.4 Wafer back lap preparation:
Wafer back lap shall be grind in In-Feed pattern and wafer backside preparation can be with
or without gold deposition
Note: Back lapped wafers are preferred as they provide better conductive epoxy die attach
and tape mounting adhesive.
7.1.3 Reject Die Identification
7.1.3.1 Indicator for all of reject die (ink die, test die, mirror die) is ink or laser. Black color for ink
dot is recommended and its position should be accurate.
7.1.3.2. Ink dot size and thickness requirements.
Die size
Mil
Micron
<508
533 - 1524
1550 – 2540
2565 – 5080
> 5000
< 20
21 - 60
61 – 100
101 - 200
> 200
Min ink dot size
Diameter
Mil
>5
>8
> 10
> 15
> 20
Thickness
Micron
> 127
> 203
> 254
> 381
> 508
Reject any transparent ink, translucent ink
(not opaque) and metallization under the
Ink can be seen at 100X magnification on
Microscope inspection. Reject ink dot thickness
more than 0.8 mils ( 20.32 Micron )
7.1.4 Die attach related
7.1.4.1 Maximum die size is governed by die pad size. See Item 7.1.4.2 for minimum gap between
die edge and die attach pad edge.
7.1.4.2 Minimum gap between die edge and die pad edge by die length (see Figure 2 for illustration).
Die Length
(C)
< 33 mils
34 - 60 mils
61-100 mils
101 – 160 mils
161 – 200 mils
201 – 300 mils
301 – 400 mils
401 – 500
> 500 mils
Min. gap between die edge to die attach pad edge(mils)
Without
With Down Bond
With Down Bond
Ground Bond
(DAP TO LD)
(BDP TO DAP)
(A)
(B)
(B1)
2
15
15
3.5
18
25
4
20
25
5
20
25
8
20
25
10
20
25
15
25
30
20
30
35
25
35
40
Figure 2 : Gap Between Die Edge and Die Pad Edge
7.1.5 Wire bond related opening
7.1.5.1 Minimum bond pad opening “A” (Figure 3)
Wire size
Mil
0.80-1.00
1.20-1.25
1.30
1.50
2.00
Single bond
Micron
23 – 25
30 – 32
33
38
50
Mil
3.0 x 3.0
3.7 x 3.7
4.0 x 4.0
4.5 x 4.5
6.5 x 6.5
Double bond
Micron
76 x 76
94 x 94
102 x 102
114 x 114
165 x 165
Mil
3.0 x 6.7
3.7 x 8.2
4.0 x 9.5
4.5 x 12.0
6.5 x 16.5
Triple bond
Micron
76 x 170
94 x 208
102 x 241
114 x 305
165 x 419
Figure 3 Bond Pad Opening ( A ) and Bond Pad Pitch ( P )
Mil
3.0 x 10.4
3.7 x 12.7
4.0 x 15
4.5 x 19.5
6.5 x 26.5
Micron
76 x 264
94 x 322
102 x 381
114 x 495
165 x 673
7.1.5.2. Min. bond pad pitch “P” (Figure 2)
Wire diameter
Mil
0.80 – 1.00
1.20, 1.25
1.30
1.50
2.00
Pad pitch
Mil
3.7
4.5
5.5
7.5
10
Micron
94
114
140
190
254
7.1.5.3. Wire length and loop height per package type.
Package type
Lead count
Wire size
Mil
PDIP 300
PDIP 600
PLCC
SOIC 150,
SOIC 208
SOIC 300
16, 20, 24, 28
TSOP
32, 40
MSOP
8, 10
QSOP 150
16, 20, 24, 28
QFP
44, 52, 64
80, 100
3, 5, 6, 8
3, 5, 6, 8
1.0
1.25
1.25
1.25
1.0
1.25, 1.5, 2.0
1.0
1.25
1.0
1.25
1.00
1.25 , 1.30
1.00
1.25
1.2, 1.25
1.2, 1.25
0.8, 1.0, 1.25
0.8, 1.0, 1.25
4, 5
5, 6,8
1.0, 2.0
0.8
TSOT23
SC70, SOT23,
VSOP
SOT223
LGAB, LGAC
8, 14, 16, 18, 20,
22, 24
24, 28, 32, 40
32, 44, 68
8, 14, 16
Wire length
Min
Mil/Micron
25/635
25/635
25/635
25/635
25/635
25/635
25/635
25/635
25/635
25/635
25/635
25/635
25/635
25/635
25/635
25/635
25/635
25/635
Max
Mil/Micron
80/2032
100/2540
120/3048
150/3840
80/2032
100/2540
80/2032
120/3048
80/2032
120/3048
60/1524
60/1524
80/2032
100/2540
200/5080
200/5080
60/1524
60/1524
Loop height
Min-Max
Nominal
Mil/Micron
Mil/Micron
8-15/203-381
12 / 305
8-15/203-381
12 / 305
8-15/203-381
12 / 305
8-15/203-381
12/305
6-13/203-330
12 / 305
6-13/203-330
12 / 305
8-15/203-381
12/305
8-15/203-381
12/305
4-7 /102-178
6/152
4-7 /102-178
6/152
4-7/102-178
6/152
4-7/102-178
6/152
6-13/152-330
12/305
6-13/152-330
12/305
8-12/203-305
10/254
8-15/203-381
12/305
4-7/102-178
6/152
4-7/102-178
6/152
35/889
6/152
100/2540
21/533
8-12/203-305
8-11/203-279
10/254
10/254
(Package thickness
0.55 mm)
SOT89 , TO92
2, 3
QFN, DFN, LGAB All
(uDFN : Package
thickness 0.75 mm)
1.0 , 1.25
1.0, 1.25
25/635
25/635
60/1524
80/2032
8-11/203-279
4-8 / 101.6-203
7.1.5.4 Bonding pads shall ideally be located on the perimeter of die and shall be located within an
area defined by lines extending inward from the package post to the center of the die (Figure 4)
Figure 4: Pad Location
7.1.5.5 Weld placement from lead tip: 10 mil (254 microns) typical.
7.1.5.6 Maximum distance from bond pad to die edge: 25 mil (635 microns)
10/254
6/152.4
7.1.5.7. Maximum wires per lead by package type.
PACKAGE
LEAD
COUNT
PDIP 300
8, 14, 16, 18,
20, 22, 24
PDIP 600
24, 28, 32, 40
SOIC 150
8, 14, 16
WIRE SIZE
NO OF WIRE
(Mil)
PER LEAD (MAX.)
1.0
5
1.25
5
1.25
5
1.0
5
1.25
5
SOIC 208
8
1.0
5
1.25
5
SOIC 300
16, 20, 24, 28
1.0
5
1.25
5
TSOP
32, 40, 44
1.25
3
STP
22, 40
1.25
5
TSOT23
3, 4, 5, 6
0.8, 1.0
3
1.25
2
SC70, SOT 23 3, 4, 5, 6
0.8, 1.0
3
1.25
2
& VSOP
SOT144 /
8, 10
1.0
3
1.25, 1.30
3
MSOP
QSOP 150
16, 20, 24, 28
1.0
3
1.25
3
QFP
44, 52, 64,
1.2
3
80, 100
1.25
3
SOT223
4, 5
1.0
5
2.0
3
QFN
All
1.0
2
7.1.5.8 An equal number of pads on each side of die, equally or symmetrically arranged is
recommended (Figure 4).
7.1.5.9 Special case of corner bond pad arrangement: careful consideration should be given to die
size, bond pad size and lead widths such that wire lengths and wire angles are optimized
(Figure 5).
Minimum wire angle: 40 degrees
7.2
8.0
Figure 5: Corner Bond Layout
Special design/guideline requirements for very small packages (packages with body width of
less than 0.150 inches)
Determining maximum pad size:
Code: (A) Package body to edge of lead = 0.005 inch min.
(B) Lead tip length
= 0.005 inch min.
(C) Lead tip to pad
= 0.005 inch min. (based on leadframe thickness)
(D) Package body to edge of pad = 0.006 inch min.
(E) Coined area of lead shoulder = 0.010 inch min.
Max. Pad width = Pkg. Width - 2(A+B+C)*
Max. Pad length = Pkg. Length - 2D
*Max pad calculation may not be applicable for fused pin to DAP option.
FORMS / APPENDICES:
8.1 Table 1:
Wafer thickness per package type (IR)
Package type
SO-JM 150 8
Min.
thickness
See item
7.1.1.2
Using leadframe Section A.
without
Downset.
MSOP
SOT23
Max. Thickness Recommended
thickness
Mil
11
Micron
279
Mil
9 - 10
Micron
229 254
11
279
9 - 10
11
279
9 - 10
229 254
229 254