HCF4013B
■
■
■
■
■
■
■
■
■
SET - RESET CAPABILITY
STATIC FLIP-FLOP OPERATION - RETAINS
STATE INDEFINITELY WITH CLOCK LEVEL
EITHER ”HIGH” OR ”LOW”
MEDIUM SPEED OPERATION 16MHz (TYP.)
CLOCK TOGGLE RATE AT 10V
STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
QUIESCENT CURRENT SPECIFIED UP TO
20V
5V, 10V AND 15V PARAMETRIC RATINGS
I
INPUT LEAKAGE CURRENT
I
= 100nA (MAX) AT V
DD
= 18V T
A
= 25
°
C
100% TESTED FOR QUIESCENT CURRENT
MEETS ALL REQUIREMENTS OF JEDEC
JESD13B ” STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES”
DESCRIPTION
The HCF4013B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages.
The HCF4013B consists of two identical, independent data type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and
DIP
ORDER CODES
PACKAGE
DIP
SOP
TUBE
HCF4013BEY
HCF4013BM1
SOP
T & R
HCF4013M013TR
Q and Q outputs. This device can be used for shift register applications, and, by connecting Q output to the data input, for counter and toggle applications. The logic level present at the D input is transferred to the Q output during the positive-going transition of the clock pulse. Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line, respectively
PIN CONNECTION
September 2001 1/9

HCF4013B
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No
3, 11
4, 10
6, 8
5, 9
1, 13
2, 12
7
14
SYMBOL NAME AND FUNCTION
CLOCK1
CLOCK2
RESET1
RESET2
Clock Inputs
Reset Inputs
SET1, SET2 Set Inputs
D1, D2 Data Inputs
Q1, Q2
Q1, Q2
V
SS
V
DD
Data Outputs
Data Outputs
Negative Supply Voltage
Positive Supply Voltage
LOGIC DIAGRAM
TRUTH TABLE
CLOCK
∆
X
X
X
D
L
H
X
X
X
X
RESET SET
L
L
L
H
L
H
L
L
L
L
H
H
Low Level
Q
L
H
Q
L
H
H
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DD
V
I
I
I
Supply Voltage
DC Input Voltage
DC Input Current
-0.5 to +22
-0.5 to V
DD
±
10
+ 0.5
V
V mA
P
D
Power Dissipation per Package 200 mW
T op
Power Dissipation per Output Transistor
Operating Temperature
100
-55 to +125 mW
°
C
°
C T stg
Storage Temperature -65 to +150
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
All voltage values are referred to V
SS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
DD
V
I
T op
Supply Voltage
Input Voltage
Operating Temperature
Parameter Value
3 to 20
0 to V
DD
-55 to 125
Unit
V
V
°
C
Q
H
L
Q
H
L
H
2/9

HCF4013B
DC SPECIFICATIONS
Test Condition Value
Symbol
V
V
I
I
V
V
I
L
OH
OL
IH
IL
OH
OL
I
I
C
I
Parameter
Low Level Input
Voltage
Output Drive
Current
Output Sink
Current
Input Leakage
Current
Input Capacitance
V
I
(V)
Quiescent Current 0/5
0/10
0/15
0/20
High Level Output
Voltage
Low Level Output
Voltage
0/5
0/10
0/15
5/0
10/0
15/0
High Level Input
Voltage
0.5/4.5
1/9
1.5/13.5
<1 5 4.95
<1 10 9.95
<1 15 14.95
<1 5
<1 10
<1 15
<1
<1
<1
5
10
15
20
5
10
15
4.5/0.5
<1
9/1 <1
5
10
3.5
7
11
0.02
0.02
0.02
0.04
0.05
0.05
0.05
0/5
0/5
13.5/1.5
<1 15
2.5
4.6
0/10 9.5
0/15 13.5
0/5 0.4
<1
<1
<1
<1
<1
5
5
10
15
5
-1.36
-0.44
-1.1
-3.0
0.44
-3.2
-1
-2.6
-6.8
1
0/10
0/15
0.5
1.5
<1 10
<1 15
1.1
3.0
2.6
6.8
0/18
V
O
(V)
|I
O
|
(
µ
A)
Any Input
Any Input
V
DD
(V)
18
T
A
= 25
°
C -40 to 85
°
C -55 to 125
1.5
3
4
°
C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
±
10
5
-5 ±
1
2
4
20
1.5
3
4
0.1
7.5
4.95
9.95
14.95
3.5
7
11
-1.15
-0.36
-0.9
-2.4
0.36
0.9
2.4
30
60
120
600
0.05
0.05
0.05
1.5
±
3
4
1
4.95
9.95
14.95
3.5
7
11
-1.1
-0.36
-0.9
-2.4
0.36
0.9
2.4
The Noise Margin for both ”1” and ”0” level is: 1V min. with V
DD
=5V, 2V min. with V
DD
=10V, 2.5V min. with V
DD
=15V
30
60
120
600
0.05
0.05
0.05
±
1
Unit
µ mA mA
µ
A
V
V
V
V
A pF
3/9

HCF4013B
DYNAMIC ELECTRICAL CHARACTERISTICS (T amb
= 25
°
C, C
L
= 50pF, R
L
= 200K
Ω
, t r
= t f
= 20 ns)
Test Condition Value (*) Unit
Symbol Parameter
V
DD
(V) Min.
Typ.
Max.
t t
TLH
PLH
PHL
THL t r f t t
CL t t t
(1)
W
, t f
THL
TLH
(2)
Propagation Delay Time
(CLOCK to Q or Q outputs)
Propagation Delay Time
(SET to Q or RESET to Q)
Propagation Delay
Time(SET to Q or RESET to Q)
Transition Time
Maximum Clock Input
Frequency
Clock Pulse Width
Clock Input Rise or Fall
Time
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
3.5
8
12
140
60
40
150 300
65 130
45 90
150 300
65 130
45 90
200 400
85 170
24
70
30
20
60 120
100 200
50
40
7
16
100
80
15
4
1 ns ns ns ns
MHz ns
µ s t
W
Set or Reset Pulse Width 5
10
15
180
80
50
90
40
25 ns t setup
Data Setup Time 5 40 20
10 20 10 ns
15 15 7
(*) Typical temperature coefficient for all V
DD
(1) Input tr, tf = 5ns value is 0.3 %/
°
C.
(2) If more than unit is cascaded in a parallel clocked application, tr should be made less than or equal to the sum of the fixed propagation delay time at 15pF and the transition time of the carry output driving stage for the estimated capacitive load.
4/9

HCF4013B
TEST CIRCUIT
C
L
R
L
R
T
= 50pF or equivalent (includes jig and probe capacitance)
= 200K
Ω
= Z
OUT of pulse generator (typically 50
Ω
)
WAVEFORM 1 : CLOCK TO Qn, Qn PROPAGATION DELAY TIMES, Dn TO CLOCK SETUP AND
HOLD TIMES, CLOCK MINIMUM PULSE WITDH, MAXIMUM CLOCK FREQUENCY
(f=1MHz; 50% duty cycle)
5/9

HCF4013B
WAVEFORM 2 : PROPAGATION DELAY TIMES (Qn, Qn TO SET, RESET), MINIMUM PULSE WIDTH
(SET AND RESET) (f=1MHz; 50% duty cycle)
6/9

DIM.
F
I
L
Z e e3
D
E a1
B b b1
HCF4013B
MIN.
0.51
1.39
1.27
mm.
TYP MAX.
1.65
MIN.
0.020
0.055
inch
TYP.
0.5
0.25
0.020
0.010
20
8.5
2.54
15.24
0.335
0.100
0.600
7.1
5.1
3.3
0.130
2.54
0.050
MAX.
0.065
0.787
0.280
0.201
0.100
P001A
7/9

HCF4013B
DIM.
C c1
D
E e e3
F
G
L
M
S
A a1 a2 b b1
MIN.
0.1
0.35
0.19
8.55
5.8
3.8
4.6
0.5
mm.
TYP MIN.
MAX.
1.75
0.2
1.65
0.46
0.25
0.003
0.013
0.007
0.5
8.75
6.2
45
°
(typ.)
0.336
0.228
1.27
7.62
4.0
5.3
1.27
0.68
8
°
(max.)
0.149
0.181
0.019
inch
TYP.
0.019
0.050
0.300
MAX.
0.068
0.007
0.064
0.018
0.010
0.344
0.244
0.157
0.208
0.050
0.026
PO13G
8/9

HCF4013B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such inform ation nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. STMicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

2001 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco
Singapore - Spain - Sweden - Swit zerland - United Kingdom
 http://w ww.st.com
9/9