HCF4520B DUAL BINARY UP COUNTER ■ ■ MEDIUM SPEED OPERATION : 6MHz (Typ.) at 10V POSITIVE -OR NEGATIVE- EDGE TRIGGERING SYNCHRONOUS INTERNAL CARRY PROPAGATION QUIESCENT CURRENT SPECIF. UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O ■ ■ ■ ■ ■ ■ DESCRIPTION HCF4520B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4520B, a Dual Binary Up Counter, consists of two identical, internal 4-stage counters. The counter stages are D-type Flip-Flops having interchangeable Clock and Enable lines for DIP SOP ORDER CODES PACKAGE TUBE T&R DIP SOP HCF4520BEY HCF4520BM1 HCF4520M013TR incrementing on either the positive-going or negative going transitions. For single-unit operations the Enable input is maintained High and the counter advances on each positive going transition of the Clock. The counters are cleared by high levels on their Reset lines. The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the clock input of the latter is held low. PIN CONNECTION October 2002 1/12 HCF4520B IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1 2 7 3, 4, 5, 6 9 10 15 11,12,13,14 8 CLOCK A ENABLE A RESET A Q1A to Q4A CLOCK B ENABLE B RESET B Q1B to Q4B VSS 16 VDD Clock A input Enable A Input Reset A Input Data Outputs Clock B input Enable B Input Reset B Input Data Outputs ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Negative Supply Voltage Positive Supply Voltage FUNCTIONAL DIAGRAM TRUTH TABLE CLOCK ENABLE RESET ACTION H L INCREMENT COUNTER L INCREMENT COUNTER L NO CHANGE L NO CHANGE L NO CHANGE L NO CHANGE H Q1 THRU Q4 = 0 L X X L H X X : Don’t Care 2/12 X HCF4520B LOGIC DIAGRAM ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O TIMING CHART 3/12 HCF4520B ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter Supply Voltage VI DC Input Voltage II DC Input Current PD Value Unit -0.5 to +22 V -0.5 to VDD + 0.5 ± 10 V mA 200 100 mW mW Top Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature -55 to +125 °C Tstg Storage Temperature -65 to +150 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O RECOMMENDED OPERATING CONDITIONS Symbol VDD 4/12 Parameter Supply Voltage VI Input Voltage Top Operating Temperature Value Unit 3 to 20 V 0 to VDD V -55 to 125 °C HCF4520B DC SPECIFICATIONS Test Condition Symbol IL VOH Parameter Quiescent Current High Level Output Voltage VI (V) VO (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 Value |IO| VDD (µA) (V) <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 TA = 25°C Min. Typ. Max. 0.04 0.04 0.04 0.08 5 10 20 100 4.95 9.95 14.95 -40 to 85°C -55 to 125°C Min. Min. Max. 150 300 600 3000 4.95 9.95 14.95 Unit Max. 150 300 600 3000 4.95 9.95 14.95 µA ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O VOL VIH VIL IOH IOL II CI Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current Output Sink Current Input Leakage Current Input Capacitance 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 Any Input Any Input 18 0.05 0.05 0.05 0.05 0.05 0.05 3.5 7 11 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 ±10-5 ±0.1 5 7.5 0.05 0.05 0.05 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 ±1 V V V V mA mA ±1 µA pF The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V 5/12 HCF4520B DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns) Test Condition Symbol Parameter VDD (V) tPLH tPHL Propagation Delay Time Clock or Enable to Output tPLH tPHL Propagation Delay Time Reset to Output tTLH tTHL Transition Time Clock Pulse Width tW Reset Pulse Width tW Enable Pulse Width tW tr , tf Clock or Enable Rise and Fall Time fMAX Maximum Clock Frequency tr , tf 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 ) s ( t c u d Clock or Enable Rise and Fall Time o r P t c u (s) l o s b O s b O t e l o 6/12 d o r P e P e let o s b -O b O - so e t le Unit Min. Typ. Max. 560 230 160 650 225 170 200 100 80 200 100 70 250 110 80 400 200 140 280 115 80 330 130 90 100 50 40 100 50 35 125 55 40 200 100 70 c u d o r P 1.5 3 4 ns ns (s) t c u d o r (*) Typical temperature coefficient for all VDD value is 0.3 %/°C. ete Value (*) ns ns ) s t( ns ns 15 15 5 3 6 8 µs MHz 15 5 5 µs HCF4520B TEST CIRCUIT ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200KΩ RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1 : MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle) 7/12 HCF4520B WAVEFORM 2 : PROPAGATION DELAY TIME, MINIMUM PULSE WIDTH (f=1MHz; 50% duty cycle) ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O TYPICAL APPLICATION RIPPLE CASCADING OF FOUR COUNTERS WITH POSITIVE-EDGE TRIGGERING 8/12 HCF4520B TYPICAL APPLICATION SYNCHRONOUS CASCADING OF 4 BINARY COUNTERS WITH NEGATIVE-EDGE TRIGGERING ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O 9/12 HCF4520B Plastic DIP-16 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 0.77 b TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.5 0.030 0.065 0.020 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O b1 0.25 D 0.010 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 P001C 10/12 HCF4520B SO-16 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O C 0.5 0.019 c1 45˚ (typ.) D 9.8 E 5.8 10 0.385 6.2 0.228 0.393 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.62 0.024 8 ˚ (max.) PO13H 11/12 HCF4520B ) s ( t c u d o ) r s ( P t c e t u e d l o o r s P b e O t e l ) o s ( s t b c u O d o ) r s P ( t c e t u e l d o o r s P b O e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 12/12