D
Journal of Energy and Power Engineering 6 (2012) 1335-1342
DAVID
PUBLISHING
Realization of a Nine-Level Cascaded NPC/H-Bridge
PWM Inverter Using Phase-Shifted Carrier PWM
Technique
Tom Wanjekeche, Dan Valentin Nicolae and Adisa Abdul Jimoh
Department of Electrical Engineering, Tshwane University of Technology, Pretoria, Private Bag X680, South Africa
Received: January 12, 2011 / Accepted: April 11, 2011 / Published: August 31, 2012.
Abstract: Cascaded H-Bridge inverter has been researched for the past two decades, but there are no explicit guidelines on how one
can realize a cascaded NPC (neutral-point-clamped)/H-Bridge inverter. Past research has also concentrated on realizing a five-level
NPC/H-Bridge inverter. This fails to address the principle of realizing a general cascaded N-level NPC/H-Bridge PWM inverter. This
paper proposes an improved topology for achieving a nine-level cascaded NPC (neutral-point-clamped) H-Bridge inverter with reduced
harmonic content. This new proposed topology requires a lesser number of separate dc sources as compared to conventional cascaded
H-Bridge inverter. The whole system is considered as having four three level legs having two positive and two negative legs. By
properly phase shifting the modulating wave and carriers, a nine-level output is achieved. A theoretical harmonic analysis of the
proposed inverter is carried out based on double Fourier principle. The theoretical results are verified through MATLAB simulation.
Key words: Harmonic content, NPC/H-Bridge PWM inverter, phase shifted carrier PWM technique, three level inverter.
1. Introduction.
Multilevel VSI (voltage source inverter) has been
recognized to be very attractive in high voltage DC to
AC conversion [1]. It offers several advantages
compared to the conventional two level inverter,
namely reduced switching losses and better harmonic
performance. Three different major multilevel
converter structures have been reported in the literature:
cascaded H-Bridges converter with separate dc sources,
diode clamped (NPC (neutral-point-clamped)), and
flying capacitors (capacitor clamped) [2, 3]. A cascade
multilevel inverter is a special kind of multilevel
inverter built to synthesize a desired AC voltage from
several levels of DC voltages [4]. Such inverters have
been the subject of research in the last several years,
where the DC levels were considered to be identical in
Corresponding author: Tom Wanjekeche, Ph.D. student,
research fields: power electronics modeling and control, power
electronics application in renewable energy. E-mail:
wanjekeche@yahoo.com.
that all of them were batteries, solar cells.
Past research has put more emphasize on single
phase H-Bridge inverter where each inverter level
generate three different voltage outputs, +Vdc, 0, and
-Vdc by connecting the DC source to the AC output
using different combinations of the four switches of the
bridge [5]. Past research has also concentrated on
realizing a five-level NPC/H-Bridge inverter without
cascading the bridge [6]; this fails to address the
principle of realizing a general cascaded N-level
NPC/H-Bridge.
If a higher output voltage is required, one of the
viable methods is to increase the number of inverter
voltage levels. For NPC inverter voltage can only be
increased up to five-level beyond which DC voltage
balancing becomes impossible. For single phase
H-Bridge inverter an increase in the number levels leads
to increase in the number of separate DC sources, thus by
combining the NPC and H-Bridge topologies, a five-level
NPC/H-Bridge with reduced number of separate DC
1336
Realization of a Nine-Level Cascaded NPC/H-Bridge PWM Inverter Using
Phase-Shifted Carrier PWM Technique
sources and a controlled DC voltage for NPC inverter
is achieved [7]. For higher voltage applications, this
structure can be easily extended to an N-level by
cascaded NPC/H-Bridge PWM inverters. It is on this
basis that this paper proposes an improved topology for
realizing a nine-level cascaded NPC/H-Bridge PWM
inverter with reduced harmonic content.
2. A Nine-Level Cascaded NPC/H-Bridge
Inverter
Van
2.1 Circuit Configuration
Fig. 1 shows the circuit configuration of the
proposed nine-level cascaded NPC/H-Bridge PWM
inverter which consists of two legs for each cell
connected to a common bus. Four active switches, four
freewheeling diodes and two diodes clamped to neutral
are adopted in each leg. The voltage stress of all the
eight power switches is equal to half of DC bus voltage.
The power switches in each leg are operated in high
frequency using phase shifted PWM control technique
to generate the three voltage levels on the ac terminal to
neutral voltage point.
The building block of the whole topology consists of
two identical NPC cascaded cells. The inverter phase
voltage Van is the sum of the two cascaded cells, i.e.:
Van  V01  V02
(1)
Assuming that the two capacitor voltages on the DC
bus voltage are equal, five different voltage levels
+2Vdc, +Vdc, 0, -Vdc and -2Vdc, are generated on the AC
terminal V01 which consist of two legs. Similarly V02
gives the same five different voltage levels. Fig. 2
shows the switching model for a nine-level output [6].
This implies that by cascading two NPC/H-Bridge
inverters (V01 and V02) and properly phase shifting the
modulating wave and carriers, a nine-level PWM
output is achieved. The number of output voltage levels
is given by:
(2)
m  4N 1
where N is the number of series connected
NPC/H-Bridges. The topology is made up of four three
level legs and each leg has four active switches and
four freewheeling diodes.
Fig. 1
The schematic diagram of the proposed cascaded
NPC/H-Bridge inverter model.
2.2 Principle of Operation
To prevent the top and bottom power switched in
each inverter leg from conducting at the same time, the
constraints of power switches can be expressed as:
Si1  Si3  1 

and
(3)


Si 2  Si 4  1

where i = 1, 2.
Let T1 = S11 & S12, T2= S13 & S14, T3= S21 & S22,
T4 = S23 & S24:
1 If both S11 & S12 are ON
(4)
T1  
0 Otherwise
1 If both S13 & S14 are ON
(5)
T2  
0 Otherwise
1 If both S21 & S22 are ON
T3  
0 Otherwise
1 If both S23 & S24 are ON
T4  
0 Otherwise
(6)
(7)
The equivalent switching function in each NPC -leg
1337
Realization of a Nine-Level Cascaded NPC/H-Bridge PWM Inverter Using
Phase-Shifted Carrier PWM Technique
is given by:
Table 1 Switching states and corresponding.
1 if T1  1

(8)
K a   0 if S12  1
  1 if T  1

2
1
if
T

3 1

(9)
K b   0 if S 22  1
  1 if T  1
4

Using Eqs. (3)-(7), a switching state and
corresponding voltage output of one cell (five-level
inverter) can be generated as shown in Table 1. From
Table 1, the voltage V01 generated by the inverter can
be expressed as:
Van  V01  V02
(10)
For the control technique stated above, the voltage
level for one leg of the cell is give as:
 K 1
 K 1
Va  K b  b
(11)
V1  K b  b
V 2
 2 
 2 
Similarly for the second leg the expression is given
by:
 K 1
 K 1 
Vb  K b  b
V1  K b  b V2
 2 
 2 
(12)
Using Eq. (10), the voltage V12 is given by:
V01 
2
2
Ka  Kb
V1  V2   K a  K b V1  V2  (13)
2
2
Table 1 clearly indicates that they are eight valid
switching states for a five level NPC/H-Bridge inverter.
Assuming that V1 = V2 = V3 = V4 = V, the switching
states are shown in Table 2.
2.3 Phase Shifted Carrier PWM Technique
An improved strategy for realizing nine-level output
is proposed in this paper. The paper uses the principle
of decomposition where each leg is treated
independently and gives a three level output [8].
Positive and negative legs are connected together
back to back and they share the same voltage source E.
PD modulation is used for achieving three level output
[9]. To achieve a five-level PWM output two triangular
carriers Vcr1 and Vcr2 in phase but vertically disposed
and modulating wave phase shifted by π are used. The
multilevel converter model is modulated using phase
Ka Kb T1
T2
S12 T3
T4
S22 Va
Vb
V01
M
1
0
-1
1
0
1
-1
-1
-1
0
0
1
1
-1
1
0
0
1
0
1
0
0
0
1
0
0
0
1
1
1
0
1
1
1
1
0
0
0
0
1
1
0
1
1
0
0
0
0
1
0
0
1
1
1
1
1
V1
0
0
V1
-V1
V1
V2
-V2
-V2
V2
0
0
V1
V2
1
2
3
4
5
6
7
-1
1
0
1
0
1
0
1
V2
V1
V1 + V2
V2
-V2
V1
-V1
0
0
-V1 −
V2
8
M = Mode.
Table 2 Switching scheme for one phase leg of a nine-level
cascaded NPC/H-Bridge inverter.
S11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
S12
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
S21
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
S22
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
S31
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
S32
0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
1
S41
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
S42
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
1
V01
0
-V
-V
-V
-V
-V
-2V
-2V
-2V
-2V
-2V
V
V
V
V
V
2V
2V
2V
2V
2V
0
V02
0
0
-V
-2V
V
2V
0
-V
-2V
V
2V
0
-V
-2V
V
2V
0
-V
-2V
V
2V
0
Van
0
-V
-2V
-3V
0
V
-2V
-3V
-4V
-V
0
V
0
-V
2V
3V
2V
V
0
3V
4V
0
shifted PWM technique as illustrated in Figs. 2 and 3
for the two NPC/H-Bridge cells. Finally a nine-level
PWM output is achieved by using the same two carriers
but phase shifted by π/4 and modulating wave phase
shifted by π as shown in Fig. 4. This is a simple control
strategy that can be easily implemented in a digital
signal processor. The switching states for one phase leg
of a nine-level NPC/H-Bridge inverter are shown in
Table 2. The table has several redundant states that can
be utilized in DC voltage balance.
1338
Realization of a Nine-Level Cascaded NPC/H-Bridge PWM Inverter Using
Phase-Shifted Carrier PWM Technique
1
Vcr1
0.8
1
0.6
0.8
0.4
0.6
0.2
0.4
0
0.2
0
-0.2
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1
-1
0.005
Vcr2
0.01
0.015
0.02
0.025
0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
0.018
0.02
(a)
(a)
(b)
Fig. 4 (a) PWM scheme and (b) output voltage waveform
for a nine-level cascaded NPC/H-Bridge inverter.
(b)
Fig. 2 (a) PWM scheme and (b) output voltage waveform
for one cell of NPC/H-Bridge inverter.
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0.005
0.01
0.015
0.02
0.025
(a)
The control strategy has two advantages as
compared to multicarrier PWM approach [10]. First
for a N-level cascaded NPC/H-Bridge PWM inverter,
we can use a switching frequency of 4N times less to
achieve the same spectrum as multicarrier approach.
This has an advantage of reducing the switching
losses, which is an important feature in high power
application. Secondly the multicarrier PWM
approach requires eight carriers to achieve
nine-level output, but the proposed control strategy
requires only one carrier phase shifted by (N - 1)π / 4,
where N is the number of series connected
NPC/H-Bridge inverter.
3. Mathematical Analysis of a Nine-Level
Cascaded NPC/H-Bridge Inverter
(b)
Fig. 3 (a) Phase shifted PWM scheme and (b) output
voltage waveform for the second cell of cascaded
NPC/H-Bridge inverter.
Having realized a nine-level output from the “3-5-9”
hybrid topology, it is important to theoretically
investigate its harmonic structure and show how
harmonic suppression is achieved. Based on the
principle of double Fourier integral [11], the harmonic
component form can be developed for a double
variable controlled waveform f(x, y) as:
Realization of a Nine-Level Cascaded NPC/H-Bridge PWM Inverter Using
Phase-Shifted Carrier PWM Technique

 A00 
 An0  cosnx  Bn0 sinnx 

 2 n1


(14)
f (x, y)   Am0  cosmx Bm0 sinmx 
m1
 

Amn0  cos(mx ny)  Bmn sin(mx ny)

m
n



1
 n0




where:
Amn 
Bmn 
1
2 2
1
2 2
 
  f ( x, y) cos(mx  ny)dxdy
(15)
  f ( x, y) sin(mx  ny)dxdy
(16)
 
 
  
Adopting Eq. (14), the first modulation between
triangular carrier Vcr1, and the positive sinusoidal
waveform a naturally sampled PMW output Vp+(t) of
Eq. (17):
V
V M
2V
1

 dc1  dc1 cosst  dc1
J (m M )
2
 m1 m 0 2
 2

 
2V

1


Vp (t)  sin m coss t  dc1
Jn
(17)
2
 m1 n m

n0

 

(m M ) sin(m  n) cos(nct  nst )
2
 2



where M is the modulation index, Vdc is the DC link
voltage of the PWM inverter and Jn is the nth order
Bessel function of the first kind. Using Vcr2 which is the
same carrier but displaced by minus unity, the naturally
sampled PWM output VP- can be:

V
V M
2V

1
 dc1  dc1 cosst  dc1
J 0 (m M )
 m1 m
2
2
 2

 
2V

1

(18)
Vp  (t )  sin m cosst  dc1
Jn

m
2

m1 n
n0

 

(m M ) sin(m  n) cos(nct  nst )
2
 2
The output of leg “a” is given by Va (t) = Vp+(t) －
Vp- (t) which is:





4Vdc1
1
V
cos(

t
)
Jn

 dc1
s
 m2,4,6 n135 m

(19)
Va (t )  
 
(m M ) cos(mc t  n s t )
 2
 
1339
The output of leg “b” is realized by replacing ωs with
ωs + π and using Vcr2 which is the same as phase
displacing Vcr1 by minus unity which gives:



4V
(1)mn
Jn
Vdc1 cos(st)  dc1
 m2,4,6 n135 m

(20)
Vb (t)  
 
(m M) cos(mct  nst)
 2
 
From Eqs. (19) and (20), it can be clearly deduced
that odd carrier harmonics and even sideband
harmonics around even carrier harmonic orders are
completely eliminated. Five-level obtained by taking
the differential output between the two legs and is
given by Eq. (21). Similarly the output between the
other two legs of the second cell of the hybrid model is
achieved by replacing ωs with ωs + π and ωc with ωc +
π/4 which gives another five-level inverter for equation
given by Eq. (22):



8V
1
Jn
2Vdc1 cos( s t )  dc1
 m4,8,12 n135 m

(21)
V01 (t )  
 
(m M ) cos(mc t  n s t )
 2
 
m

n



8Vdc1
(1) 4

2
V
cos(

t
)

Jn
dc1
s

 m4,8,12 n135 m
V02 (t )  
 
(m M ) cos(mc t  n s t )
 2
 
(22)
Eqs. (21) and (22) clearly show that for five-level
inverter, the proposed control strategy has achieved
reduction in carrier harmonics. It is clearly shown that
even sideband harmonics around multiples of four
carrier harmonics are completely eliminated. Finally,
the output for a nine-level is achieved differentiating the
output voltage between the two cells of the five-level
cells and this is given by Eq. (23). It can be concluded
that for a cascaded N-level inverter the carrier harmonic
order is pushed up by factor of 4N where N is the
number of cascaded hybrid inverters. The output
voltages and spectral waveforms to confirm the
validation of the control strategy using this approach of
double Fourier transform will be discussed later.



8V
1
J
4Vdc1 cos(s t )  dc1
 m8,16,24 n135 m n (23)

Van (t )  
 
(m M ) cos(mct  nst )
 2
 
1340
Realization of a Nine-Level Cascaded NPC/H-Bridge PWM Inverter Using
Phase-Shifted Carrier PWM Technique
4. Simulation
4.1 Simulation Model
In order to verify that a nine-level output is achieved
by cascading two NPC/H-Bridge PWM inverter and
properly phase shifting the carrier and the modulating
wave. Fig. 5 was developed and simulated in
MATLAB. The control strategy to minimize
harmonics was designed and developed in MATLAB
as shown in Fig. 6. It is assumed that the DC voltage
input for each module is Vdc = 100 V. The inverter
(a)
(b)
Fig. 6 (a) Waveform and (b) spectrum for a five-level
NPC/H-Bridge inverter phase voltage (fm = 50 HZ, fsw,dev =
500 HZ, mf = 20, ma = 0.9).
operates under the condition of fm = 50 Hz, mf = 20 for
a five level output and ma = 0.9. The device switching
frequency is found from fsw,dev = (mf/2) × fm = 500 Hz.
4.1 Simulation Results
(a)
(b)
Fig. 5 (a) Four legs of a nine-level cascaded NPC/H-Bridge
inverter; (b) control strategy for a nine-level cascaded
NPC/H-Bridge inverter.
Five-level inverter output is shown in Figs. 6-8 for
various switching frequency. Fig. 6 shows the
simulated waveform for the phase voltage V01 of the
NPC/H-Bridge PWM inverter and its harmonic content.
The waveform V01 is a five voltage levels, whose
harmonics appear as sidebands centered on 2mf and its
multiples such as 4mf, 6mf. This simulation verifies
analytical Eq. (21) which shows that the phase voltage
does not contain harmonics lower than the 31st, but has
odd order harmonics (i.e. n = ±1, ±3, ±5) centered on m
= 4, 8, 12. Figs. 7 and 8 show five-level NPC/H-Bridge
inverter output for device inverter switching frequency
of 1,000 Hz and 200 Hz respectively.
Fig. 9 shows the waveform of the phase voltage of a
nine-level NPC/H-Bridge PWM inverter. It has
sidebands around 4mf and its multiples, this shows
further suppression in harmonic content. This topology
operates under the condition of fm = 50 HZ, mf = 40
and ma = 0.9. The device switching frequency is found
Realization of a Nine-Level Cascaded NPC/H-Bridge PWM Inverter Using
Phase-Shifted Carrier PWM Technique
1341
(a)
(a)
(b)
Fig. 7 (a) Waveform and (b) spectrum for a five-level
NPC/H-Bridge inverter phase voltage (fm = 50 HZ, fsw,dev =
1,000 HZ, mf = 40, ma = 0.9).
(b)
Fig. 9 (a) Waveform and (b) spectrum for a nine-level
cascaded NPC/H-Bridge inverter phase voltage (fm = 50 HZ,
fsw,dev = 500 HZ, mf = 40, ma = 0.9).
(a)
(a)
(b)
Fig. 8 (a) Waveform and (b) spectrum for a five-level
NPC/H-Bridge inverter phase voltage (fm = 50 HZ, fsw,dev =
2,000 HZ, mf = 80, ma = 0.9).
(b)
Fig. 10 (a) Waveform and (b) spectrum for a nine-level
cascaded NPC/H-Bridge inverter phase voltage (fm = 50 HZ,
fsw,dev = 1,000 HZ, mf = 80, ma = 0.9).
from fsw,dev = (mf/4) × fm = 500 Hz. This simulation
verifies analytical Eq. (23) which shows that the phase
voltage does not contain harmonics lower than the 67th,
but has odd order harmonics (i.e. n = ±1, ±3, ±5)
centered on m = 8, 16, 32.
As seen in Fig. 10, a switching frequency of 1 kHz
which fits most of high power switching devices has a
THD of 0.18%, this makes the topology a perfect fit for
most high power application such as utility interface
power quality control and medium voltage drives.
1342
Realization of a Nine-Level Cascaded NPC/H-Bridge PWM Inverter Using
Phase-Shifted Carrier PWM Technique
5. Conclusions
An improved topology that can be used to achieve a
nine-level NPC/H-Bridge PWM inverter has been
presented. A five-level NPC/H-Bridge inverter that has
been proposed by many researchers gives a higher
THD which is not acceptable in most high and medium
power application unless a filter is used. By properly
phase shifting both the modulating wave and the carrier,
it has been shown that nine-level voltage output can be
achieved with a reduced harmonic content that can be
readily applied in high power application. The
simulation results obtained clearly verify the analytical
equations showing that a nine-level output has
multiples of eighth order cross modulated harmonics.
From the mathematical analysis it has been shown that
cross modulated harmonics for a generalized N-level
cascaded NPC/H-Bridge inverter is a multiple of 4N
where N is the number of series connected
NPC/H-Bridge inverter.
References
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