ELE 2110A Electronic Circuits
Week 7: Common-Collector Amplifier,
MOS Field Effect Transistor
ELE2110A © 2008
Lecture 07 - 1
Topics to cover …
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Common-Collector Amplifier
MOS Field Effect Transistor
– Physical Operation and I-V Characteristics of
n-channel devices
– Non-ideal effects
– P-channel devices and other types
z
Reading Assignment:
Chap 14.1 – 14.5 of Jaeger and Blalock , or
Chap 5.7 of Sedra & Smith
And
Chap 4.1 – 4.4 of Jaeger and Blalock or
Chap 5.1-5.2 of Sedra & Smith
ELE2110A © 2008
Lecture 07 - 2
Common-Collector Amplifier
Input
AC ground
Output
Source
Load
AC/Small signal equivalent
RL = R4 || R7
Also called “Emitter follower”
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RB = R1 || R2
Lecture 07 - 3
Terminal Voltage Gain
(β +1)R
CC = vo =
L
Avt
v rπ + (β +1)R
L
b
gm R
CC ≅
L
∴A
for
vt
1+ g m R
L
ELE2110A © 2008
In most C-C amplifiers, gm RL >> 1
∴ ACC
vt ≅ 1
β >>1
Output voltage at emitter follows
input voltage, hence the circuit is
named Emitter Followers.
Lecture 07 - 4
Input Resistance and
Overall Voltage Gain
Input resistance looking into the
base terminal is given by
v
CC
Rin = b = rπ + (β +1)RL
i
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Overall voltage gain is
⎛
⎜
⎜
⎜
⎜
⎜
⎝
⎞⎛
⎟⎜
⎟⎜
⎟⎜
⎟⎜
⎟⎜
⎠⎝
⎞
⎛
⎞
⎜v ⎟
vo vb ⎟⎟
⎜ b⎟
⎟ = Avt ⎜
⎟
⎜ v ⎟
v v ⎟⎟
⎜
⎟
⎝ i ⎠
b i⎠
⎡
⎤
CC
⎢
⎥
R
R
⎢
⎥
B in
= ACC
⎢
⎥
vt ⎢
⎛
⎞⎥
CC ⎟ ⎥
⎜
⎢ R +⎜R
R
in ⎟⎠ ⎦⎥
⎝ B
⎣⎢ I
CC = vo =
Av
v
i
Lecture 07 - 5
Example 1
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Problem: Find overall voltage gain.
Given data: β=100, Q-point values: IC=245uA,
VCE=3.64V, gm=9.8mΩ−1, rπ=10.2kΩ.
Assumptions: Small-signal operating conditions.
Analysis:
AC ground
R = R R =104kΩ
B 1 2
R = R R =11.5kΩ
L 4 7
R = rπ + (β +1 )R =10.2kΩ +101(10.2kΩ) =1.17MΩ
in
L
Avt =
gm R
L = 0.991
1+ g m R
L
ELE2110A © 2008
⎡
⎢
⎢
⎢
⎢
⎢
⎢⎣
⎤
CC
⎥
R R
⎥
in
B
Av = Avt
⎥ = 0.956
⎞
⎛
R + ⎜⎜ R R CC ⎟⎟ ⎥⎥
I ⎝ B in ⎠ ⎥⎦
Lecture 07 - 6
Input Signal Range
For small-signal operation, magnitude of vbe < 5 mV.
v rπ
v
b
b
v = irπ =
=
be
R
rπ + (β +1 )R
L 1+ g m R + L
L r
π
⎛
⎜
⎜
⎜
⎜
⎝
⎛
⎜
⎜
⎜
⎜
⎝
R
v ≤ 0.005 1+ g m R + L
L β
b
≅ 0.005(1+ gm R )V
L
⎞⎞
⎟⎟
⎟⎟
⎟⎟
⎟⎟
⎠⎠
If gm R >> 1 , vb can be increased beyond 5 mV limit.
L
Emitter followers can be used with relatively large input signals!
ELE2110A © 2008
Lecture 07 - 7
Output Resistance
ix = −i − βi =
vx
⎛
⎜
⎜
⎜
⎜
⎜
⎝
−β −
vx
R + rπ
R + rπ
th
th
R + rπ r
R
CC
π
th
∴Rout ≅
=
+ th
β +1
β +1 β +1
⎞
⎟
⎟
⎟
⎟
⎟
⎠
R
R
α
1
th
th
RCC
out = g + β +1 ≅ g + β +1
m
m
CC 1 + R connected to base
Rout ≅
g
β +1
m
Rth = RI || RB
ELE2110A © 2008
Small output resistance!
Lecture 07 - 8
Example 2
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Problem: Find output resistance.
Given data: β=100, Q-point values: IC=245uA,
VCE=3.64V, gm=9.8mS, rπ=10.2kΩ, rο=219kΩ.
Assumptions: Small-signal operating conditions.
Analysis:
R
α
th = 0.990 + 1.96kΩ =120Ω
=
+
RCC
out g
m β +1 9.80mS 101
ELE2110A © 2008
Lecture 07 - 9
Current Gain
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Terminal current gain
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i
CC = 1 = β +1
Ait
i
Lecture 07 - 10
Summary of Emitter Follower
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Voltage gain: Close to unity.
Input resistance: Large
Output resistance: Small
Input signal range: relatively large
Terminal current gain: Large (β+1)
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Excellent for use as a voltage buffer
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ELE2110A © 2008
Lecture 07 - 11
Voltage Buffer
Without buffer:
Rs
Vs
RL
Vo
vo =
RL
vs << vs if
Rs + RL
RL << Rs
With buffer:
⎛ Ri
⎞
RL
vo = ⎜⎜
vs ⎟⎟ A
⎝ RS + Ri ⎠ RL + RO
≅ Avs = vs for Ri >> RS and RO << RL
Requirement of voltage buffer:
- High input resistance
- Low output resistance
- Unity voltage gain
ELE2110A © 2008
Lecture 07 - 12
Summary of Single Stage BJT Amplifiers
C-E
(RE=0)
Emitter Degenerated
C-E
C-C
C-B
Terminal
Voltage Gain
Inverting
& large
Inverting &
moderate
1
Non-inverting &
Large
Input
Resistance
Moderate
Large
Large
Low
Output
Resistance
Moderate
Large
Low
Large
Input Voltage
Range
Small
Moderate
Large
Moderate
Terminal
Current Gain
Inverting
& Large
Inverting & Large
Noninverting &
Large
1
ELE2110A © 2008
Lecture 07 - 13
More Complicated Amplifier …
?
?
?
741 Op-amp - Built from single stage amplifiers
ELE2110A © 2008
Lecture 07 - 14
Topics to cover …
z
z
Common-Collector Amplifier
MOS Field Effect Transistor
– Physical Operation and I-V Characteristics of
n-channel devices
– Non-ideal effects
– P-channel devices and other types
ELE2110A © 2008
Lecture 07 - 15
Introduction
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Metal-Oxide Semiconductor Field-Effect Transistor
(MOSFET) is the primary component in high-density chips
such as memories and microprocessors
z
Compared with BJT, MOSFET has
–
–
–
–
z
Higher integration scale
Lower manufacturing cost
Simpler circuitry for digital logic and memory
Inferior analog circuit performance in general
Recent trend: more and more analog circuits are
implemented in MOS technology for
– lower cost
– integration with digital circuits in a same chip (mixed-signal IC)
ELE2110A © 2008
Lecture 07 - 16
Microphotograph of
a state-of-the-art CPU chip
ELE2110A © 2008
Lecture 07 - 17
Structure of MOSFET
z
Four terminals:
– Gate, Source, Drain and
body
z
Two types
– n-Channel (NMOS)
– p-Channel (PMOS)
z
The minimum value of L is
referred as the feature size of
the fabrication technology.
– E.g., 45nm is used for Intel’s
Core 2 processors.
symbol
ELE2110A © 2008
Lecture 07 - 18
Low Gate Voltage
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Body is commonly tied to ground
When the gate is at a low voltage (VGS ~ 0):
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF (reverse bias)
– iG=0 (always), iDS = 0
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Depletion region between n+ and p-type bulk
– No current can flow, transistor is said in “Cutoff” mode
ELE2110A © 2008
Lecture 07 - 19
Increase Gate Voltage
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Vertical electric field established
Under the gate-oxide:
– Holes (positive charges) repelled
– Depletion region under gate oxide formed
ELE2110A © 2008
Lecture 07 - 20
Further Increase Gate Voltage
z
z
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Electrons (minorities in the p region) attracted by the electric field
towards the gate, and stopped by the gate oxide
A n-type inversion layer formed underneath the gate oxide when VGS
reaches a certain value, called threshold voltage (Vt, or VTN for
NMOS)
The channel connects the S and D and now currents can flow
between them
ELE2110A © 2008
Lecture 07 - 21
Linear (Triode) Mode of Operation
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When vGS > Vt and a small vDS is applied
– Current flows from D to S (Electrons flow from S to D)
– iDS ∝ vDS
z
z
z
Increasing vGS above Vt increases the electron density in the
channel, and in turn increases the conductivity between D & S
Such devices are called enhancement-type MOSFET
In this mode, transistor = a voltage controlled resistor
ELE2110A © 2008
Lecture 07 - 22
Increase Drain Voltage: Channel Pinch-Off
vG
vD
vS
z
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Increase vDS Æ Decrease vGD Æ less electrons at the drain side of
the channel
When vDS ≥ vGS – Vt
Æ VGD ≤ Vt
Æ no channel exists at the drain side. The channel “pinches-off”
ELE2110A © 2008
Lecture 07 - 23
Saturation Mode of Operation
vG
vD
vS
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When channel pinches off, electrons still flows from S to D
– Electrons are diffused from the channel to the depletion region near D,
where they are drifted by the lateral E-field to the D
– Similar to a reverse-biased B-C junction in a BJT
z
z
Further increase of vDS Æ no effect on the channel Æ current is
“saturated” and the transistor is in “Saturation Mode”
In this mode, transistor = a voltage controlled current source
ELE2110A © 2008
Lecture 07 - 24
Qualitative I-V Characteristic
Pinch Off
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Lecture 07 - 25
I-V Characteristics
z
In the Linear region, drain current depends on
– How much charge is in the channel
– How fast the charge is moving
dQ
amount of charge in the channel
=
I≡
dt
time it takes the carriers to get across the channel
ELE2110A © 2008
Lecture 07 - 26
Amount of Channel Charge
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MOS structure looks like a
parallel plate capacitor
VGC is composed of two
components
– Vt to form the channel
– (VGC-Vt) to accumulate negative
charges in the channel
Qchannel = CV
C = ε ox
WL
= CoxWL where Cox = ε ox / tox
tox
V = VGC − Vt = (vGS − vDS / 2 ) − Vt
142
4 43
4
Average gate-channel voltage
Ref: G.-Y. Wei, notes ES154, Harvard University
ELE2110A © 2008
Lecture 07 - 27
Carrier Velocity
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Charge is carried by electrons.
Carrier velocity v is proportional to the lateral E-field between source
and drain
v = µ n E where µ n is the mobility
E = vDS / L
z
Time for carriers to cross the channel is
L
L2
=
t = L/v =
µ n E µ n vDS
ELE2110A © 2008
Lecture 07 - 28
I-V Behavior: Linear Mode
z
Combine the channel charge and velocity to find the current flow
– Current = amount of charge in the channel / time it takes the carriers to
get across the channel
Qchannel
µv
= C oxWL(vGS − Vt − v DS / 2) n 2DS
t
L
W
= µ n C ox (vGS − Vt − v DS / 2)v DS
L
iD =
= K n (vGS − Vt − v DS / 2)v DS where K n = µ n C ox
iD = ( µ n Cox )
z
z
W
L
W
L
1 2 ⎤
⎡
(
)
−
−
v
V
v
v DS ⎥
t
DS
⎢ GS
2 ⎦
⎣
( µ n Cox ) is a constant determined by the processing technology, and is
denoted by K’n
W/L is a main design parameter in integrated circuit design.
ELE2110A © 2008
Lecture 07 - 29
I-V Behavior: Saturation Mode
z
If vGD ≤ Vt, channel pinches off near the drain
– When vDS ≥ Vdsat = vGS – Vt
z
z
Now, drain voltage no longer increases with vDS
Putting vDS = vGS – Vt to the equation:
iD = ( µ n Cox )
W
L
1 2 ⎤
⎡
(
)
v
V
v
v DS ⎥
−
−
GS
t
DS
⎢
2 ⎦
⎣
1
W
iD = (µnCox) (vGS −Vt )2
2
L
z
for VGS > Vt and
VDS ≥ vGS - Vt
iD independent of vDS.
ELE2110A © 2008
Lecture 07 - 30
Summary of NMOS I-V Characteristics
Region
Cutoff
Conditions
I-V relation
Triode
Saturation
vGS ≥ Vt
v GS < V t
v DS < v GS − V t
iD = 0
Cutoff region
W
iD = K 'n
L
vGS < Vt
v DS ≥ v GS − V t
1
W
1 2 ⎤
⎡
2
i
=
K
'
(
v
−
V
)
(
)
v
V
v
v
−
−
D
n
GS
t
t
DS
DS ⎥
⎢ GS
2
L
2
⎣
⎦
K n ' = µ nCox
Triode region
v GS ≥ V t
and
v DS < v GS − V t
Saturation region
v GS ≥ V t
and
v DS ≥ v GS − V t
ELE2110A © 2008
Lecture 07 - 31
Ideal Square Law Model: ID vs VGS
In saturation mode:
1
W
iD = (µnCox) (vGS −Vt )2
2
L
z
MOS vs. BJT
– Current is quadratic with voltage in MOS vs.
– exponential relationship in BJT
z
Saturation mode of MOS corresponds to active mode of BJT
ELE2110A © 2008
Lecture 07 - 32
Ideal Square-Law Model: ID vs VDS
NMOS
ELE2110A © 2008
Lecture 07 - 33
Topics to cover …
z
z
Common-Collector Amplifier
MOS Field Effect Transistor
– Physical Operation and I-V Characteristics of
n-channel devices
– Non-ideal effects
– P-channel devices and other types
ELE2110A © 2008
Lecture 07 - 34
Non-ideal Effects
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Channel length modulation
Body effect
Temperature influence
Breakdown
ELE2110A © 2008
Lecture 07 - 35
Channel-Length Modulation
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At vDS=vGS-VTN=VDSsat,
– Channel pinch-off
z
where gate-to-channel voltage = VTN
i =
D
'
Kn W ⎛
ELE2110A © 2008
v −V
TN
2 L GS
⎜⎜
⎝
⎞
⎟⎟
⎠
As vDS increases beyond vDSsat,
the pinch off point moves away
from D towards S
– The effective channel length L
is reduced by ∆L
– ID increases
– An effect similar to Early effect
in BJT
2
Lecture 07 - 36
Channel-Length Modulation
z
This effect is modeled by adding
a term (1+λvDS) to the I-V
equation:
i =
D
'
Kn W ⎛
2 L
⎜⎜
⎝
v −V
GS TN
⎞
⎟⎟
⎠
2⎛
⎜1+ λv
⎜
⎝
DS
⎞
⎟
⎟
⎠
λ = channel length
modulation parameter
ELE2110A © 2008
Lecture 07 - 37
Body Effect
z
z
Channel-body can be regarded as a pn junction
If channel-body junction is reverse-biased,
– Depletion layer beneath the gate oxide becomes wider
– Since the amount of negative charges in the ( channel +
depletion ) layer = amount of positive charges in the gate
(Constant for a fixed gate-source voltage)
Æ Channel depth is reduced
– This is equivalent to an increase in the threshold voltage
ELE2110A © 2008
Lecture 07 - 38
Body Effect
z
Non-zero vSB changes threshold
voltage:
V =V + γ ⎛⎜⎜ v + 2φ − 2φ ⎞⎟⎟
TN TO ⎝ SB
F
F⎠
where
VTO= zero substrate bias for VTN (V)
γ= body-effect parameter ( V )
2ΦF= surface potential parameter (V)
(source-body voltage)
It follows that the body voltage controls iD.
This phenomenon is known as the body effect.
ELE2110A © 2008
Lecture 07 - 39
Effects of Temperature
z
Vt and mobility µ are sensitive to temperature:
– Vt decreases by 2mV for every 1ºC rise in temperature
– mobility µ decreases with temperature
z
Overall, increase in temperature results in lower drain
currents
ELE2110A © 2008
Lecture 07 - 40
Avalanche Breakdown
z
z
As VD is increased, the drain-body junction becomes reversed biased
Æ Breakdown occurs at voltages of 20 to 150V
Æ Rapid increase in the drain current
Normally, no permanent damage to the device
ELE2110A © 2008
Lecture 07 - 41
Punch-through Breakdown
z
z
z
Whe VD is increased to a point, Æ the depletion region surrounding
D extends to the S Æ Punch-through breakdown (about 20 V)
Occurs in devices with short channels
Normally, no permanent damage to the device
ELE2110A © 2008
Lecture 07 - 42
Gate Oxide Breakdown
z
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When VGS exceeds about 30 V (or lower in modern IC technology)
Æ Gate oxide breaks down like in the case of a capacitor
Results in permanent damage to the device
ELE2110A © 2008
Lecture 07 - 43
Input Protection
Input Pin
z
to gates
Since the MOSFET has a very small input capacitance and a very
high input resistance, a small amount of static charges accumulating
on the gate can cause the gate voltage to exceed the breakdown
level
– e.g., Electrostatic Discharge (ESD) from human body
z
Clamping diodes can be used in the I/O pins to protect the circuit
from gate-oxide breakdown
ELE2110A © 2008
Lecture 07 - 44
Topics to cover …
z
z
Common-Collector Amplifier
MOS Field Effect Transistor
– Physical Operation and I-V Characteristics of
n-channel devices
– Non-ideal effects
– P-channel devices and other types
ELE2110A © 2008
Lecture 07 - 45
P-channel MOSFET (PMOS)
z
Similar to NMOS, but doping and voltages reversed
–
–
–
–
Body tied to highest voltage (Vdd) to prevent forward-biasing pn junctions
Source typically tied to Vdd too
Gate voltage high: transistor is OFF
Gate voltage low: transistor is ON when VGS < Vt (threshold voltage)
z
Inverted channel of positively charged holes
– vGS and vDS are negative and Vt is also negative
Symbols
ELE2110A © 2008
Lecture 07 - 46
PMOS I-V Characteristics
Cutoff region | vGS |<| Vt |
Triode region
| v GS |≥ | V t |
and
| v DS |< | v GS − V t |
Saturation region
Vt, vGS and vDS are negative.
Cutoff
iD = 0
where K p = K p '
ELE2110A © 2008
| v GS |≥ | V t |
| v DS |≥ | v GS − V t |
Triode/Linear
Saturation
1 2 ⎤
⎡
i D = K p ⎢ ( vGS − Vt ) v DS − v DS
⎥⎦
2
⎣
W
, K p ' = µ p Cox
L
and
iD =
1
K p ( vGS − Vt ) 2
2
µp is 2 or 3-times lower than µn
Lecture 07 - 47
Complementary MOS (CMOS) Technology
PMOS transistor is fabricated in the n well
Complementary MOS or CMOS integrated-circuit
technologies provide both NMOS and PMOS on a same IC
ELE2110A © 2008
Lecture 07 - 48
Depletion-mode MOSFET
z
A depletion-type MOSFET has a built-in
channel by fabrication
– It is ON when no gate-source voltage is applied
– Must apply a negative vGS to turn off device
z
Vt is negative for NMOS
enhancement
depletion
ELE2110A © 2008
Lecture 07 - 49
MOSFET Circuit Symbols
ELE2110A © 2008
z
(g) and(i) are the most
commonly used
symbols in VLSI logic
design.
z
MOS devices are
symmetric.
z
In NMOS, n+ region at
higher voltage is the
drain.
z
In PMOS p+ region at
lower voltage is the
drain
Lecture 07 - 50