Vol. 34, No. 6
Journal of Semiconductors
June 2013
A noise immunity improved level shift structure for a 600 V HVIC
Zhang Yunwu(张允武)Ž , Zhu Jing(祝靖), Sun Guodong(孙国栋), Liu Cuichun(刘翠春),
Sun Weifeng(孙伟峰), and Qian Qinsong(钱钦松)
National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China
Abstract: A novel level shift circuit featuring with high dV /dt noise immunity and improved negative VS capacity is proposed in this paper. Compared with the conventional structure, the proposed circuit adopting two
cross-coupled PMOS transistors realizes the selective filtering ability by exploiting the path which filters out the
noise introduced by the dV /dt . In addition, a differential noise cancellation circuit is proposed to enhance the noise
immunity further. Meanwhile, the negative VS capacity is improved by unifying the detected reference voltage and
the logic block’s threshold voltage. A high voltage half bridge gate drive IC adopting the presented structure is
experimentally realized by using a usual 600 V BCD process and achieves the stable operation up to 65 V/ns of the
dV /dt characteristics.
Key words: gate driver; half bridge; dV /dt noise; level shift; negative VS capacity
DOI: 10.1088/1674-4926/34/6/065008
EEACC: 2570
1. Introduction
With the rapid development of micro-electronics technology, high voltage integrated circuits (HVIC) are widely used
in the area of motor drives, flat panel display, LED lighting,
etc, and the high voltage half bridge gate driver is an essential
circuit block in the modern HVICŒ1 3 .
One of the most urgent requirements for a half bridge gate
driver IC, whose high side circuit adopts floating power supply, is the noise immunity performanceŒ4 7 . High peak pulsating noise applied to the driver though the floating voltage source abnormally changes the output status of the driver
which causes critical damage on the system. The above difficulty is usually solved by adding a pulse-filter behind the level
shift stage. However, it is difficult for the above method to
eliminate the dV /dt noises higher than 50 V/nsŒ8; 9 . In order
to further improve the abilities of noise immunity, a noise cancellation circuit with common feedback techniqueŒ10 and the
active dV /dt noise cancellation topology cooperate with a resistor interleaved CMOS (RiCMOS) based on a logic circuit
with a special processŒ4; 11; 12 have been proposed. However,
these structures require complex circuit design and harsh layout matching which increase cost and process complexity.
In this paper, a novel level shift circuit structure with selective filtering ability realized by two cross-coupled PMOS
transistors and two resistors using a usual 600 V BCD technology is presented. The proposed half bridge gate driver with the
new level shift structure shows excellent noise immunity and
an improved negative VS capacity. In addition, the proposed
structure can also be used in the other high voltage gate drivers
which need a level-shifting circuit.
2. Circuit structure and principle
LMN2), low voltage PMOSs (including LMP1, LMP2) and resistors (R1 , R2 , R3 and R4 ) are used to implement the novel
level shifter, which has the function of level-shifting and selectively filtering. The shifter can transmit the signal from the control logic which is biased to the ground to the high-side drive
module which is biased to the floating ground (VS ).
2.1. Enhanced dV /dt noise immunity
As shown in Fig. 2, when the common dV /dt noise is applied on VB , the displacement current caused by the parasitic
capacitances of the LDMOSs can flow through the resistance
R1 and R2 and it can be expressed as
Idis1 D Cpar1 dV =dt:
(1)
Cpar1 (Cpar2 / is the value of the parasitic capacitance
LMN1 (LMN2), as shown in Fig. 2. Then, the voltage drop
Vdrop1 .Vdrop2 / of the resistance R1 (R2 / is
Vdrop1 D Idis1 R1 D R1 Cpar1 dV =dt;
(2)
Vdrop2 D Idis2 R2 D R2 Cpar2 dV =dt:
(3)
The gate voltage VGLMP1 (VGLMP1 / and the source voltage
VSLMP1 (VGLMP2 / of LMP1 (LMP2) are determined by the following equations
VGLMP1 D VB
Vdrop2 D VB
R2 Cpar2 dV =dt;
(4)
VSLMP1 D VB
Vdrop1 D VB
R1 Cpar1 dV =dt;
(5)
where VB is the supply voltage in high side. Assuming that the
LDMOSs, the PMOSs and the resistors are well matched respectively, so R1 D R2 , Cpar1 D Cpar2 , then according to
Eqs. (2)–(5), it is clear that
The high side module with the proposed level shifter is
shown in Fig. 1. The high voltage LDMOSs (including LMN1,
† Corresponding author. Email: zhangyunwu5555@163.com
Received 20 October 2012, revised manuscript received 27 November 2012
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Vdrop1 D Vdrop2 ;
(6)
© 2013 Chinese Institute of Electronics
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Zhang Yunwu et al.
Fig. 1. High side driver with the proposed level shift structure.
Fig. 3. Working under normal circumstances.
when those are mixed with the common-mode noise.
Fig. 2. Working under noise circumstance.
2.2. Improved negative VS
thus
VGLMP1 D VSLMP1 ;
VGSLMP1 D 0;
(7)
VGLMP2 D VSLMP2 ;
VGSLMP2 D 0:
(8)
From the above two equations, it is clear that both LMP1
and LMP2 stay at the off-state during the noise condition. Consequently, no fault signal can transmit to the output stage of the
high side driver.
Based on the asynchronous character, the normal input signal can pass through the proposed structure by conducting one
LMP and closing the other at each moment, as shown in Fig. 3.
Thus, it can exactly catch the short edge pulses which are generated by the narrow pulse generator module in low side even
As shown in Fig. 4, the negative VS capability is limited
by the noise margin demand in the conventional structure following the relationship below.
Vdrop1 D VBS
VT D VB
VS D Vdrop1 C VT
VS
VB ;
VT ;
(9)
(10)
where VT is the threshold voltage of the logic circuit after the
shifter. From the above equations, it is clear that the negative
VS is restricted by the VT which has to meet the requirement
asked by the noise margin in the conventional structure.
Although the proposed structure still detects the input voltage through the voltage drop across the resistors using the logic
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Fig. 4. Single path of the conventional structure.
Fig. 6. Key point waveform of the circuit.
Fig. 5. Signal transmission diagram.
3. Gate driver with the proposed circuit
circuit, the drop voltage and the logic circuit have the same reference VS , as a result, the threshold voltage is VT which is quite
different from VS C VT shown in conventional structure.
From the structure shown in Fig. 5, it can be easily found
that, the detected signals are these drop voltages across R3 and
R4 (Vdrop3 and Vdrop4 / no longer Vdrop1 and Vdrop2 again. And
they can also be expressed as:
In order to understand the dynamic characters of the level
shifter more clearly, the waveforms of those key points labeled
in Fig. 1 are studied, as shown in Fig. 6. According to the analysis method above, the working conditions of the half bridge
gate driver using the proposed driver can be divided into two
parts:
Vdrop3 D GmLMP1 .VB
VDSLMN2 /R3 ;
(11)
3.1. Without dV /dt noise
Vdrop4 D GmLMP2 .VB
VDSLMN1 /R4 ;
(12)
As the rising edge of input signal is coming, narrow pulse
signal Vup is generated by the pulse generated module in
the low side and it turns the LDMOS LMN1 on and keeps
the LMN2 off. At this moment, there is a voltage difference
between the drain terminals of those two LDMOSs, that is
VDLMN1 < VDLMN2 . Then, the LMP2 turns on and LMP2 is still
off, here the input voltage signal is transformed to a current by
LMP2 which forms the voltage across R4 (Vdrop4 / and triggers
the following logic block finally. In the circuit design, to avoid
the useful signal being filtered by the later differential noise
elimination circuit, the pulse width of Vdrop4 must be greater
than the filter width of the noise elimination circuit. As the
falling edge is coming, the narrow pulse signal Vfall is generated. And Vfall will turn on the LMN2, also there is a voltage
difference at the drain terminal of those two LDMOSs, but now
it is VDLMN2 < VDLMN2 . Then, the LMP1 turns on and the input
signal passes through the proposed structure successfully.
Waveforms of all the key points mentioned above are
shown in Fig. 6(a), which show that the new level shift circuit
where GmLMP1 and GmLMP1 are the transconductances of LMP1
and LMP2, respectively, and
VDSLMN1 D VB
ILMN1 R1 ;
(13)
VDSLMN2 D VB
ILMN2 R2 ;
(14)
when LMN1 and LMN2 are turned on by the input signal asynchronously. And as analyzed before, in order to transmit the
input signal successfully, Vdrop3 and Vdrop4 should meet the relationships described below:
Vdrop3;4
VS > VT
VS :
(15)
From the equation above, it is obvious that the negative VS
is freed from the limitation as Eq. (10) described. Now with the
novel topology shown in Fig. 1, VT can be chosen without take
noise margin which is associated with VS into consideration.
This is another advantage of the proposed structure.
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Fig. 7. Micro-photo of the driver.
Fig. 9. dV /dt noise test results. (a) A 65 V/ns noise is applied to VB .
(b) Experimental results of the driver with the proposed shifter.
3.2. Under high dV /dt noise circumstance
As shown in Fig. 6(b), when high dV /dt noise is applied
on VB , displacement currents Idis form the drop voltage across
R1 and R2 . Due to the synchronous character of dV /dt noise
and the well matched resistors and LDMOSs, the drop voltage
across R1 and R2 are equal which makes sure that both LMP1
and LMP2 are closed at this moment. As a result, the fault signals introduced by dV /dt noise are forbidden to transmit at the
point Vup and Vfall . So, the proposed shifter circuit acts as a
common-mode rejection circuit in nature taken in this sense.
4. Simulation and measurement
Fig. 8. Simulation results (a) Conventional structure wrong triggered
by a dV /dt D 50 V/ns. (b) Driver with the proposed shifter works well
even dV /dt D 65 V/ns.
does not induce any negative influence and is able to realize
each function as the traditional one.
Figure 7 shows the micro-photos of the half bridge driver
with the proposed level shift structure. The following simulated
and experimental results are provided to verify the theoretical
analysis and feasibility of the presented level shifter.
Figure 8 shows the simulation results of dV /dt noise influence. As shown in Fig. 8(a), the driver adopts the conventional
level shifter wrongly trigged after exposing a floating VS with
the slope of 50 V/ns and Figure 8(b) depicts the output result of
the proposed structure is correct when the noise slope is even
65 V/ns.
Figure 9 presents the experimental results of dV /dt noise
test. Figure 9(a) is the waveform of the dV /dt noise with a
65 V/ns transition slope, which is detected by the high voltage
decay test probe. As shown in Fig. 9(b), even after exposing
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floating gate drivers which need a high noise immunity performance.
References
Fig. 10. Allowable negative VS voltage of the shifters.
rising voltage up to 600 V with the slope of 65 V/ns, the output
status is not changed owing to the proposed level shifter.
As shown in Fig. 10, it is possible to transfer the input signal to high-side even when VS is 12 V. However, the conventional driver allows only 7 V at the same VBS .
5. Conclusion
A novel level shift circuit presented for half bridge gate
drive IC has been investigated in this paper. From our results
of circuit simulation and experimental measurement, the controversial issues about dV /dt noise disturbance and negative VS
have been resolved. In comparison to the conventional levelshifting circuit, the structure with two cross-coupled transistors
is more liable and yields improved negative VS . And it is evident that the proposed circuit can be used for those high side
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