Institut d’Electronique Fondamentale
Université Paris-Sud, CNRS
220 rue André Ampère
Orsay 91405, France joseph.friedman@u-psud.fr • +33(0)6.27.26.54.40 http://www.ief.u-psud.fr/~friedman
E DUCATION
Northwestern University, Evanston, IL
Ph.D., Electrical & Computer Engineering
M.S., Electrical & Computer Engineering
Dartmouth College , Hanover, NH
B.E. (Thayer School of Engineering)
A.B., Engineering Sciences
R ESEARCH & T ECHNICAL E XPERIENCE
June 2014
June 2010
June 2009
June 2009
Université Paris-Sud , Orsay, France
CNRS Post-Doctoral Research Associate to Dr. Damien Querlioz
July 2014 – present
Designing hardware systems that perform Bayesian inference with ferromagnetic and superparamagnetic spintronic nanodevices to create decision-making circuits that function analogously to the human brain.
Nov. 2015 RWTH Aachen University , Aachen, Germany
Guest Scientist of Electronic Materials Research Laboratory
Taught tutorial course and initiated collaboration on memristor logic circuit design.
Northwestern University , Evanston, IL Sept. 2009 – June 2014
Doctoral Dissertation: Cascaded Magnetoresistive Spintronic Computing
Advisor: Alan V. Sahakian
Invented spintronic logic families with various magnetic materials to enable low-power high-performance beyond-CMOS computing. These spintronic logic families permit the integration of efficient cascaded circuits through interactions between electric and magnetic fields.
Intel Corporation , Santa Clara, CA
Logic Design Automation Intern
Developed automation and debugging techniques for RTL-toschematic logic design for 22 nm Ivy Bridge and 32 nm Jaketown processors to achieve 90% time reduction for processor verification.
June – Dec. 2010

Curriculum Vitae – 30 March 2016 Joseph S. Friedman
Dartmouth College , Hanover, NH
Laboratory Assistant to Prof. B. Stuart Trembly
Performed product testing and development for microwave treatment of dermatological tissue to increase safety and power efficiency.
Columbia University , New York, NY
Research Assistant to Prof. Ken Shepard
Evaluated modeling methods for graphene transistors and on-chip inductor structures for application to low-noise amplifiers.
Tele Atlas (TomTom subsidiary) , Lebanon, NH
Software Engineering Intern
Streamlined regression testing routines for digital mapping software.
Sept. 2008
Summer 2008
Summer 2007
J OURNAL P APERS
1. J. S. Friedman
, L. E. Calvet, P. Bessière, J. Droulez, D. Querlioz, “Bayesian Inference with
Muller C-Elements,” IEEE Transactions on Circuits & Systems I (accepted).
2. J. S. Friedman , A. Godkin, A. Henning, Y. Vaknin, Y. Rosenwaks, A. V. Sahakian,
“Threshold Logic with Electrostatically Formed Nanowires,”
IEEE Transactions on Electron
Devices 63 :3, 1388-1391 (2016).
3. J. S. Friedman , E. R. Fadel, B. W. Wessels, D. Querlioz, A. V. Sahakian, “Bilayer
Avalanche Spin-Diode Logic,” AIP Advances 5 :11, 117102 (2015).
4. J. S. Friedman , B. W. Wessels, G. Memik, A. V. Sahakian, “Emitter-Coupled Spin-
Transistor Logic: Cascaded Spintronic Computing Beyond 10 GHz,” IEEE Journal on
Emerging and Selected Topics in Circuits and Systems 5 :1, 17-27 (2015).
5. J. S. Friedman , J. A. Peters, B. W. Wessels, G. Memik, A. V. Sahakian, “Emitter-Coupled
Spin-Transistor Logic,” Journal of Parallel and Distributed Computing 74 :6, 2461-2469
(2014).
6. J. S. Friedman , A. V. Sahakian, “Complementary Magnetic Tunnel Junction Logic,” IEEE
Transactions on Electron Devices 61 :4, 1207-1210 (2014).
7. J. S. Friedman
, N. Rangaraju, Y. I. Ismail, B. W. Wessels, “A Spin-Diode Logic Family,”
IEEE Transactions on Nanotechnology 11 :5, 1026-1032 (2012).
C ONFERENCE P APERS & P RESENTATIONS
1. J. S. Friedman
, “CMAT Non-Volatile Spintronic Computing: Complementary MTJ Logic,”
Proc. SPIE Spintronics IX , Aug. 2016 (invited).
2. J. S. Friedman
, L. E. Calvet, P. Bessière, J. Droulez, D. Querlioz, “Bayesian Inference with
Muller C-Elements,” International Symposium on Circuits & Systems , May 2016 (accepted).
3. D. Querlioz, A. F. Vincent, A. Mizrahi, N. Locatelli, J. S. Friedman , D. Vodenicarevic,
“Computational Techniques for the Design of Bioinspired Systems that Employ
Nanodevices,” Proc. International Workshop on Computational Electronics , Sep. 2015
(invited).
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Curriculum Vitae – 30 March 2016 Joseph S. Friedman
4. M. G. A. Martins, F. S. Marranghello, J. S. Friedman , A. V. Sahakian, R. P. Ribas, A. I.
Reis, “Enhanced Spin-Diode Synthesis using Logic Sharing,” Proc. EUROMICRO Digital
System Design Conference , Aug. 2015.
5. J. S. Friedman
, D. Querlioz, A. V. Sahakian, “Magnetoresistance Implications for
Complementary Magnetic Tunnel Junction Logic (CMAT),” Proc.
IEEE/ACM International
Symposium on Nanoscale Architectures , July 2015.
6. M. G. A. Martins, F. S. Marranghello, J. S. Friedman , A. V. Sahakian, R. P. Ribas, A. I.
Reis, “Automated Synthesis Approaches for Digital Integrated Design of Spin-Diode
Circuits,” International Workshop on Logic & Synthesis , June 2015.
7. N. Locatelli, A. F. Vincent, A. Mizrahi, J. S. Friedman , D. Vodenicarevic, J.-V. Kim, J.-O.
Klein, W. Zhao, J. Grollier, D. Querlioz, “Spintronic Devices as Key Elements for Energy-
Efficient Neuroinspired Architectures,” Proc. Design, Automation & Test in Europe , March
2015 (invited).
8. J. S. Friedman
, B. W. Wessels, D. Querlioz, A. V. Sahakian, “High-Performance
Computing based on Spin-Diode Logic,” Proc. SPIE Spintronics VII , Aug. 2014 (invited).
9. M. G. A. Martins, F. S. Marranghello, J. S. Friedman , A. V. Sahakian, R. P. Ribas, A. I.
Reis, “Spin Diode Network Synthesis using Functional Composition,” Proc. Symposium on
Integrated Circuits and Systems Design , Sep. 2013.
10. J. S. Friedman
, B. W. Wessels, A. V. Sahakian, “High-Performance Spintronic Computing with Magnetoresistive Semiconductor Heterojunctions,” Proc.
SPIE Spintronics VI , Aug.
2013 (invited).
11. J. S. Friedman
, “Cascaded Magnetoresistive Spintronics: A Pathway for Computing Beyond
10 GHz,”
CMOS Emerging Technologies Research Symposium , July 2013 (invited).
12. J. S. Friedman
, Y. I. Ismail, G. Memik, A. V. Sahakian, B. W. Wessels, “Emitter-Coupled
Spin-Transistor Logic,” Proc.
IEEE/ACM International Symposium on Nanoscale
Architectures , July 2012.
► Featured in
Science Daily : “Toward Achieving One Million Times Increase in
Computing Efficiency,” July 2012.
13. J. S. Friedman
, N. Rangaraju, Y. I. Ismail, B. W. Wessels, “InMnAs Magnetoresistive Spin-
Diode Logic,” Proc. ACM Great Lakes Symposium on VLSI , May 2012.
P ATENTS
1. J. S. Friedman
, A.V. Sahakian, “Magnetic Tunnel Junctions with Control Wire,”
U.S.
Patent #9,299,917 (2016).
2. J. S. Friedman , G. Memik, B. W. Wessels, “Emitter-Coupled Spin-Transistor Logic,” U.S.
Patent #9,270,277 (2016).
3. J. S. Friedman , B. W. Wessels, A. V. Sahakian, “System and Method for Spin Logic,” U.S.
Patent #9,186,103 (2015).
4. J. S. Friedman , N. Rangaraju, Y. I. Ismail, B. W. Wessels, “Logic Cells Based on Spin
Diode and Applications of Same,”
U.S. Patent #8,912,821 (2014).
5. J. S. Friedman
, A.V. Sahakian, “A Method for Computing with Complementary Networks of Magnetic Tunnel Junctions,” Pending U.S. Patent #15/054,401 (2016).
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Curriculum Vitae – 30 March 2016 Joseph S. Friedman
6. J. S. Friedman
, G. Memik, B. W. Wessels, “Emitter-Coupled Spin-Transistor Logic,”
Pending U.S. Patent #14/997,887 (2016).
7. J. S. Friedman , A. V. Sahakian, A. Godkin, A. Henning, Y. Rosenwaks, “System and
Method for Threshold Logic with Electrostatically Formed Nanowire Transistors,” Pending
U.S. Patent #14/672,503 (2015).
T UTORIAL C OURSE
Spintronic & Beyond-CMOS Computing System Integration
Numerous nanodevices have been developed with exotic electronic and spintronic characteristics. However, it is not obvious how to best connect these devices to each other in cascaded systems that exploit their unique behavior. In this three-lecture tutorial, I describe and analyze the wide range of techniques for cascading logic devices. In addition to the electronic cascading mechanisms of conventional computers, this course evaluates recently proposed integration techniques for new nanocomputing systems. I particularly emphasize spintronics, in which the rich physics enable a large variety of cascading mechanisms. In contrast to conventional presentations that follow the vertical integration of a single device from the physics to the full system performance, this course provides a cross-section of cascading techniques for numerous devices. The advantages and drawbacks of the techniques are evaluated to provide inspiration for innovative circuit designs based on novel devices.
University of Rochester , Rochester, NY
RWTH Aachen University , Aachen, Germany
École Polytechnique , Palaiseau, France
Nov. 30 – Dec. 1, 2015
Nov. 4
–
6, 2015
Oct. 19, 2015
A CTIVE E XTERNAL C OLLABORATIONS
Northwestern University , Evanston, IL
Prof. Alan Sahakian, Prof. Bruce Wessels, Prof. Hooman Mohseni, Prof. Alan Taflove, Prof.
Gokhan Memik
Designing and analyzing spintronic logic circuits
Prof. Mark Hersam, Michael Geier
Designing and fabricating carbon nanotube logic circuits
RWTH Aachen University , Aachen, Germany
Dr. Eike Linn, Anne Siemon
Designing and simulating memristor logic circuits
Tel Aviv University , Tel Aviv, Israel
Prof. Yossi Rosenwaks, Dr. Andrey Godkin, Dr. Gideon Segev, Alex Henning, Yonatan
Vaknin
Designing, simulating, and fabricating electrostatically formed nanowire threshold logic circuits
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Curriculum Vitae – 30 March 2016 Joseph S. Friedman
Unité Mixte de Physique CNRS/Thales & Université Paris-Sud , Palaiseau, France
Dr. Julie Grollier, Daniele Pinna
Designing and simulating skyrmion logic circuits
Universidade Federal do Rio Grande do Sul , Porto Alegre, Brazil
Prof. Andre Reis, Prof. Renato Ribas, Mayler Martins, Felipe Marranghello
Optimizing spin-diode logic synthesis algorithms
Université Pierre-et-Marie-Curie , Paris, France
Dr. Jacques Droulez, Dr. Pierre Bessière
Designing and analyzing Bayesian inference circuits
University of Illinois , Urbana, IL
Prof. Jean-Pierre Leburton, Dr. Anuj Girdhar
Designing and simulating carbon-based spintronic logic circuits
R ECOGNITION
Fulbright Postdoctoral Research Fellowship (awarded; chose to decline)
Microelectronics Journal Editorial Board Member
Reviewer for IEEE Transactions on Electron Devices , IEEE Transactions on Circuits &
Systems , IEEE Transactions on Nanotechnology, Journal of Physics D: Applied Physics
MemoCIS Short Term Scientific Mission to RWTH Aachen University
Northwestern University Walter P. Murphy Award
M ENTORED S TUDENTS
Eric R. Fadel , École Polytechnique (now MIT Ph.D. student)
M1 Internship (four months): Magnetic Domain Wall Oscillator and Logic
► Awarded École Polytechnique’s Prix du Stage de Recherche
Damir Vodenicarevic , Université Paris-Sud
Ph.D. Candidate; Supervising experimental work
T EACHING E XPERIENCE
Northwestern University , Evanston, IL
Course Instructor
EECS 391 – VLSI Systems Design
Teaching Assistant
EA 1 Honors – Engineering Analysis
EECS 203 – Introduction to Computer Engineering
EECS 391 – VLSI Systems Design
Winter 2013
Fall 2011, 2012, & 2013
Spring 2012
Winter 2011, 2012 & 2014
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Curriculum Vitae – 30 March 2016 Joseph S. Friedman
EECS 101 – An Introduction to Computer Science For Everyone
EECS 493 – Design & Analysis of High-Speed Integrated Circuits
EECS 223 – Fundamentals of Solid State Engineering
Spring 2011
Winter 2011
Spring 2010
Johns Hopkins University Center for Talented Youth , Saratoga Springs, NY Summer 2009
Teaching Assistant
Taught electrical engineering concepts to gifted 12 to 16 year old students
Dartmouth College , Hanover, NH
Teaching Assistant
ENGS 32 – Electronics: Introduction to Linear and Digital Circuits
Winter 2009
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