Analysis of Jitter due to
Power-Supply Noise in
Phase-Locked Loops
Payam Heydari, Massoud Pedram
Department of EE-Systems,
University of Southern California,
Los Angeles, CA 90089
OUTLINE
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INTRODUCTION
PLL NOISE SOURCES
POWER SUPPLY NOISE
VCO PHASE NOISE & PLL TIMING JITTER
EXPERIMENTAL RESULTS
CONCLUSION
1
INTRODUCTION
• PLLs are ubiquitous in RF and mixed signal circuits
• The phase-lock concept is fundamental in any
situation where some form of feedback is used to
synchronize some local periodic event with some
observable external event
• Most high-speed microprocessors and memories
employ phase locking to suppress timing skews
PLL APPLICATIONS
•
•
•
•
•
•
Clock and data recovery
Clock generation for microprocessors
Frequency synthesis
Demodulation of FM signals
Coherent demodulation of AM signals
Local oscillator design for cellular phones, cable
modems, and radios
2
PLL DESIGN SPECIFICATIONS
• Lock range
• Capture range
• Acquisition time
• Jitter
! Cycle-to-cycle jitter:
T +∆T1
T +∆T2
• The PLL timing jitter can cause serious problems in a
system which uses the PLL
ΦCLK
Vin
Vin , Vout
1
Chld
Vout
t
PRIOR WORK
• Oscillator phase noise due to the device noise
– Using an LTI feedback system approach to analyze
the phase noise (Razavi, JSSC’96)
– Using an LTV model and stochastic differential
equations to analyze the phase noise (Hajimiri,
JSSC’98) (Demir, DAC’98)
• Oscillator jitter due to power supply noise
– Using a deterministic frequency modulation model
(Hertzel, CICC’98)
3
NOISE SOURCES IN PLL
Input noise
Phase Detector
Input
Low-pass Filter
KDfpd(.)
L(n)[vLP] = L(m)[vPD]
÷M
KD
Frequency
Divider
∫ (.)
t
VCO
VCO phase noise
m
m −1
L( m ) = bm d m + bm −1 d m −1 + ... + b0
dt
dt
(n)
L
n−1
= an d n + an −1 d n−1 + ... + a0
dt
dt
n
POWER SUPPLY NOISE
Impulsive noise
Sinusoidal noise
Wp/Lp=38/0.25
Wp/Lp=38/0.25
Wn/Ln=25/0.25
Wn/Ln=25/0.25
Cdecoup= 0.5pF
Cdecoup= 100pF
Tc
Tc
4
MODELING THE SINUSOIDAL NOISE
• When a large decoupling capacitor is present in the
circuit, the supply noise is modeled as a sinusoidal
waveform with a random maximum amplitude and a
uniformly distributed random phase shift in
[−π , π]
n, max [ k ] = Vn, max ( kT )
k = 0, 1, 2, ...
vn (t ) = Vn , max [ k ] sin(ω0 t + θ )
kT ≤ t ≤ (k + 1)T
• vn(t) is a wide-sense stationary process, therefore:
2
E{Vn, max [k ]}
Rv (τ ) =
cos (ω0τ)
tr
n
ηv = 0
n
MODELING THE IMPULSIVE NOISE
Vclk
lpwr1
G1
lgnd1
t d , G 1 ≠ ... ≠ t d , Gn
lpwr2
PLL
..
..
lgnd2
lpwr3
G2
Small
decoupling
capacitance
GN
lgnd3
Vn,max[3]
Vn,max[2]
Vn,max[1]
τ[1].tr
τ[2].tr
τ[3].tr t
trpz(t)
1
∞
vn (t ) = ∑Vn, max [k ] trpz( t − k T )
τ[k ].tr
k =0
t
∆Vn
where
t
tr
kT ≤ t ≤ (k + 1)T
Vn,max[k] and τ[k] are independent stochastic processes.
5
MODELING THE IMPULSIVE NOISE
• The pulse width of the supply noise is very small
compared to the clock period
Vclk , ∆Vn
Vclk , ∆Vn
τ[1]
τ[2]
τ[3]
t
vn (t ) = s (t − λ )
∞
where
s(t ) = ∑Vn, max [k ] δ (t − k T )
t
k =0
• When a small decoupling capacitor is present in the
circuit, the power supply noise is modeled as an
impulse train with a uniformly-distributed random shift
in [0 , tr] and normally distributed random amplitude
MODELING THE IMPULSIVE NOISE
• s(t) is a wide-sense cyclo-stationary stochastic
process
Theorem:
If s(t) is a cyclo-stationary process and λ is a uniformly
distributed random variable in the interval [0 , tr] and
independent of s(t), then the process:
vn(t) = s(t - λ)
is a stationary process with the following statistics:
tr
1
ηv = t ∫ηs(t ) dt
r
n
0
ηv = E{Vn, max [k ]}
n
tr
1
Rv (τ ) = t ∫ Rs(t + τ , t ) dt
n
r
0
Rv (τ ) =
n
2
σVn
, max
tr
δ (τ )
2
Svn(ω) = t1 SV (e jω) Xδ (ω)
r
n, max
Svn(ω ) =
2
σ Vn
, max
tr
6
PHASE NOISE OF THE VCO
• A VCO implemented as a five-stage fully differential
ring oscillator exhibits good current-frequency
linearity
Using BSIM3v3 MOS model
V0
V1
V2
V3
V4
• The VCO excess frequency is calculated as:
kWυ satCox
.vn (t )
∆ f (t ) =
2 NCeq Vref (kWυ satCox rDS +1)
PHASE NOISE OF THE VCO
• The autocorrelation of ∆ f (t) is a linear function of the
autocorrelation of vn
2
R∆f (τ ) = KVCO
Rvn (τ )
• The phase noise of the VCO is:
K VCO .σ Vn , max
tr
ω2
2
2
SΦ (ω ) =
n
KVCO
ω2
SV (ω ) =
n
2
Impulsive noise
2
π KVCO .
(δ (ω + ωn) + δ (ω − ωn))
2ω2
Sinusoidal noise
7
TIMING JITTER OF THE VCO
• The timing jitter of the VCO is the standard deviation
of the timing uncertainty:
2




clock 
KVCO
2π 2 f 2
στ2 =
2
2π 2 f 2
clock
(RΦ (0) − RΦ (τ ) ) =
n
σV2n , max τ
tr





Impulsive noise
n
2
KVCO
2π 2 f 2
(1 − cos (ωnτ ))
clock
Sinusoidal noise
PLL TIMING JITTER
SΦ 0(ω ) = HPLL (ω ) SΦn(ω )
2
• Assume that the loop filter is narrowband. Hence the
PLL transfer function exhibits a dominant pole
sp2
sp1
sz
2
1 /( RK PFD )
SΦ 0(ω ) =
S (ω )
1 + ( jω M ) /( RK VCO K PFD ) Φ n
sp 2 = −
R K VCO K PFD
M
8
PLL TIMING JITTER (cont’d)
2
2
 KVCO
σVn
, max
jitter (τ ) = 
2
Φ0
 2 K PFD sp2 tr

(1 − exp( − sp τ ) )

2

Impulsive noise
2
4
 KVCO
σVn
, max
.

jitter (τ ) = 
2
2
Φ0
t
r
 2ω n M


1
  2
 ω + sp 2 (1 − cos(ωnτ ) )
 n
2 
Sinusoidal noise
PHASE-FREQUENCY DETECTOR
• Does not suffer from false lock
• The input signal and the VCO output are exactly in phase
• The lock is attained very quickly
Da ta
UP
R E SET
D OW N
C LK
9
CHARGE-PUMP CIRCUIT
• The zero introduced by the resistor causes a smooth and nonoscillatory transition.
• The glitch produced by the voltage drop across resistor is
dampened by a 0.2pF capacitor
MPC1
MPC3
MPC2
500
UP
Din
MSP
PFD
CLKin
3pF
DOWN
MSN
MNC2
0.2pF
MNC1
10K
VOLTAGE-CONTROLLED OSCILLATOR
The wide-swing cascode current tail:
1. increases the Power-Supply Rejection Ratio (PSRR)
2. protects the VCO frequency from the supply variations
MPd18
MPd17
MPd12
MPd15
MPd16
MNd16
MNd15
Replica biasing
Vref
Av
MNd13
MNd18
MPd12
MPd11
MNd11 MNd12
MNd14
MNd17
From Bandgap Reference
10
DESIGNOF BANDGAP REFERENCE
4.2µ
0.25µ
R3
4.2µ
0.25µ
4.2µ
0.25µ
7.54K
…
R2
30.51K
R4
21.7K
R1
…
30.51K
N=150
• The circuit generates a fixed 0.8V
• It exhibits 0.88% variation in response to a
temperature variation of 10-130°C and 0.37%
variation in response to a supply variation of 1.8-3.2V
EXPERIMENTAL SETUP
0.1pF
Cdecoupling
0.1pF
PLL
0.05pF
1 3nH
0.05pF
0.5
3nH
1 0.5nH 1 1nH 10pF
0.1pF
One of five output driver
stages
Frequency offset
(kHz)
5.3
9.1
15.7
32.3
40
64
80
100
1
0.05pF
3nH 0.5 3nH
Phase noise [dB/Hz]
Analytical
-92.2
-96.4
-100.3
-109.3
-110
-112.4
-115.6
-119.7
Simulation [dB/Hz]
-93.4
-97.5
-103
-111.2
-111.4
-114.3
-116.2
-121.8
11
CONCLUSION
• A mathematical model for calculating the power supply
noise induced timing jitter in PLLs was presented
• The model relies on the stochastic modeling of the
power supply noise
• The effect of the power supply noise on the phase
noise of the VCO was analyzed and expressed in
closed form
• The PLL timing jitter was determined using the phase
noise of the VCO
• A PLL was designed and our mathematical model was
utilized to predict the timing jitter
• Experimental results show the accuracy of our model
12