RFIC Design and Testing for Wireless
Communications
A Full-Day Tutorial at VLSI Design & Test Symposium
July 23, 2008
Lecture 1: Introduction
Vish ani D.
Vishwani
D Agrawal,
Agra al vagrawal@eng.auburn.edu
agra al@eng a b rn ed
Foster Dai, daifa01@auburn.edu
Auburn University, Dept. of ECE, Auburn, AL 36849, USA
1
Abstract
This tutorial discusses design and testing of RF integrated circuits
(RFIC) It is suitable for engineers who plan work on RFIC but did not
(RFIC).
have training in that area, those who work on IC design and wish to
sharpen their understanding of modern RFIC design and test methods,
and engineering managers. It is an abbreviated version of a onesemester
t
university
i
it course. Specific
S
ifi topics
t i
i l d semiconductor
include
i
d t
technologies for RF circuits used in a wireless communications system;
basic characteristics of RF devices – linearity, noise figure, gain; RF
front-end design
g – LNA,, mixer;; frequency
q
y synthesizer
y
design
g –p
phase
locked loop (PLL), voltage controlled oscillator (VCO); concepts of
analog, mixed signal and RF testing and built-in self-test; distortion –
theory, measurements, test; noise – theory, measurements, test; RFIC
SOCs and their testing.
testing
2
Objectives
‰ To acquire introductory knowledge about integrated circuits
(IC) used in radio frequency (RF) communications systems.
‰ To learn basic concept of design of RFIC.
‰ To learn basic concepts of RFIC testing.
3
Outline
‰ Introduction to VLSI devices used in RF communications
■ SOC and SIP
■ Functional components
■ Technologies
‰ Design concepts
‰ Test concepts
■ Basic RF measurements
■ Distortion characteristics
■ Noise
■ SOC testing and built-in self-test (BIST)
4
References
1.
M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital,
Memory & Mixed-Signal VLSI Circuits, Boston: Springer, 2000.
2.
J. Kelly and M. Engelhardt, Advanced Production Testing of RF, SoC, and
SiP Devices, Boston: Artech House, 2007.
3
3.
B Razavi,
B.
Razavi RF Microelectronics,
Microelectronics Upper Saddle River,
River New Jersey: Prentice
Hall PTR, 1998.
4.
g , C. Plett and F. Dai,, Integrated
g
Circuit Design
g for High-Speed
g p
J. Rogers,
Frequency Synthesis, Boston: Artech House, 2006.
5.
K. B. Schaub and J. Kelly, Production Testing of RF and System-on-a-chip
Devices for Wireless Communications, Boston: Artech House, 2004.
5
Schedule
09:30AM – 10:00AM
Lecture 1
Introduction
Agrawal
10:00AM – 11:00AM
Lecture 2
RF Design
g I
Dai
11:00AM – 11:30AM
Break
11:30AM – 13:00PM
Lecture 3
RF Design II
Dai
13:00PM – 14:00PM
Lunch
14:00PM – 15:00PM
Lectures 4
RF Testing I
Agrawal
15:00PM – 15:30PM
Break
15:30PM – 17:30PM
Lectures 5-7
RF Testing II
Agrawal
Lecture 8
RF BIST
Dai
6
An RF Communications System
Superheterodyne Transceiver
0°
0
VGA
LNA
Phase
Splitter
LO
Duplexerr
90°
ADC
LO
DAC
0°
PA
VGA
Phase
Splitter
LO
90°
Diigital Signa
al Process
sor (DSP)
ADC
DAC
RF
IF
BASEBAND
7
An Alternative RF Communications System
Zero-IF (ZIF) Transceiver
0°
0
LNA
Phase
Splitter
LO
Duplexerr
90°
ADC
DAC
0°
Phase
Splitter
PA
LO
90°
Digital Signa
al Process
sor (DSP)
ADC
DAC
RF
BASEBAND
8
Components of an RF System
‰Radio frequency
● Duplexer
● LNA: Low noise amplifier
● PA: Power amplifier
● RF mixer
● Local oscillator
● Filter
‰Intermediate frequency
‰Mixed-signal
● ADC: Analog to digital
converter
● DAC: Digital to analog
converter
‰Digital
● Digital
g signal
g processor
p
(DSP)
● VGA: Variable gain amplifier
● Modulator
M d l t
● Demodulator
● Filter
9
Duplexer
‰TDD: Time-Division
Duplexing
‰FDD: FrequencyDivision Duplexing
● Same Tx and Rx frequency
● RF switch (PIN or GaAs FET)
● LLess th
than 1dB lloss
Rx
● Tx to Rx coupling (-50dB)
● More loss (3dB) than TDD
● Adj
Adjacentt channel
h
l lleakage
k
fr
ft
Rx
fr
Tx
TDD command
Tx
ft
10
LNA: Low Noise Amplifier
‰ Amplifies received RF signal
‰ Typical characteristics:
● Noise figure
● IP3
● Gain
● Input and output impedance
● Reverse isolation
● Stability
St bilit factor
f t
2dB
– 10dBm
15dB
50Ω
20dB
>1
‰ Technologies:
● Bipolar
● CMOS
‰ Reference: Razavi, Chapter 6.
11
PA: Power Amplifier
‰ Feeds RF signal to antenna for transmission
‰ Typical characteristics:
● Output power
● Efficiency
● IMD
● Supply voltage
● Gain
● Output harmonics
● Power control
● Stability factor
+20 to +30 dBm
30% to 60%
– 30dBc
3.8 to 5.8 V
20 to 30 dB
– 50 to – 70 dBc
On-off or 1-dB steps
>1
‰ Technologies:
● GaAs
● SiGe
SiG
‰ Reference: Razavi, Chapter 9.
12
Mixer or Frequency (Up/Down) Converter
‰ Translates frequency by adding or subtracting local oscillator
(LO) frequency
‰ Typical characteristics:
● Noise figure
● IP3
● Gain
● Input impedance
● Port to port isolation
12dB
+5dBm
10dB
50Ω
10-20dB
‰ Tecnologies:
● Bipolar
● MOS
‰ Reference: Razavi,
Razavi Chapter 66.
13
Passive Mixer
V(RF)
V(LO)
nFET
V(IF)
RL
14
Active Mixer
VDD
V(IF)
V(LO)
V(RF)
15
LO: Local Oscillator
‰ Provides signal to mixer for down conversion or upconversion.
‰ Implementations:
p
● Tuned feedback amplifier
● Ring oscillator
● Phase-locked loop (PLL)
● Direct digital synthesizer (DDS)
16
Phase Splitter
‰ Splits input signal into two same frequency outputs that differ
in phase by 90 degrees.
‰ Used for image rejection.
C
R
Vout_1
Vin
R
V t 2
Vout_2
C
17
SOC: System-on-a-Chip
‰ All components of a system are implemented on the same VLSI
chip.
‰ Requires same technology (usually CMOS) used for all
components.
‰ Components not implemented on present-day SOC:
● Antenna
● Power amplifier (PA)
18
SIP: System-in- Package
‰ Several chips or SOC are included in a package.
‰ Routing
g within SIP mayy be p
provided via a semiconductor
substrate.
‰ RF communications system may contain:
■ SIP, containing
● SOC consisting of
ƒ CMOS digital
di it l and
d mixed-signal
i d i l components
t (DSP
(DSP, ADC,
ADC DAC)
ƒ CMOS LNA and mixers
ƒ CMOS DDS
ƒ Filters
■ Power amplifier (PA)
■ Antenna
19
RFIC Design and Testing for Wireless
Communications
A Full-Day Tutorial at VLSI Design & Test Symposium
July 23, 2008
Lecture 2: RF Design I
Vishwani D. Agrawal
Foster Dai
Auburn University, Dept. of ECE, Auburn, AL 36849, USA
20
Phase Lock Loop Integer-N Frequency Synthesizer
fr
reference
(input)
Phase
Comparator
Transfer function
that controls
loop dynamics (LPF)
+
F(s)
f o = N ⋅ f ref
ffb
Divider
Controllable
C
t ll bl Si
Signall
Source (VCO)
÷N
Digital signal
to control the
value of N
fo
synthesized signal
(output)
N is an integer Æ the minimum step size = fr Æto get a smaller step size, the reference
frequency must be made smaller Æ N must be higher in order to generate the same fo
Æ larger phase noise (in-band
(in band noise magnified 20logN times by the loop)
loop).
Frequency synthesizer design I (PLL), FDAI, 2008
21
Fractional-N Concept
If the loop divisor N is a fractional number, e.g., N=K/F, where K and F are
integer numbers Æ the minimum step size = fr /FÆ can achieve small step
size without lowering the reference frequency Æ loop divisor N can be small
in order to generate the same fo Æ better phase noise (in-band noise
magnified 20logN times by the loop).
How can we design a fractional divider? Divider is a digital block and its
output transits only at the input clock edge Æ we can only generate integer
frequency divider!!
Dual-modulus divider P/P+1: by toggling between the two integer division
ratios, a fractional division ratio can be achieved by time-averaging the divider
output. As an example, if the control changes the division ratio between 8 and
9 and the divider divides by 8 for 9 cycles and by 9 for 1 cycle and then the
9,
process repeats itself, then the average division ratio will be:
N=
8 × 9 + 9 ×1
= 8.1
10
Frequency synthesizer design I (PLL), FDAI, 2008
22
Fractional-N Synthesizer with a Dual Modulus Prescaler
fo =
Transfer function
that controls
l
loop
d
dynamics
i (LPF)
fr
+
÷R
f r ⎡ ( P + 1) K + P ( F − K ) ⎤ f r ⎡
K⎤
P
=
+
⎥⎦ R ⎢⎣
R ⎢⎣
F
F ⎥⎦
Step Size =
F(s)
fr
RF
ffb
Dual Modulus
Divider
Controllable Signal
Source (VCO)
÷P/P+1
Carry
out bit Cout
synthesized
signal
(output)
fo
CLK
z-11
yI +
Fractional
Accumulator
+
+
log2F
yI-1
K
f Cout =
Frequency synthesizer design I (PLL), FDAI, 2008
Kf clk
F
23
Fractional Accumulator Operations
f Cout
Kf clk
=
F
Accumulator operations with F = 8, K = 1
clock
cycle i
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
yi
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
yi-1
NA
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
Cout
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
Accumulator operations with F = 8, K = 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
yi
0
3
6
1
4
7
2
5
0
3
6
1
4
7
2
5
0
3
6
yi-1
NA
0
3
6
1
4
7
2
5
0
3
6
1
4
7
2
5
0
3
Cout
1
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
1
0
0
clock cycle i
Frequency synthesizer design I (PLL), FDAI, 2008
24
Fractional-N Frequency Synthesizer with a
Multi-Modulus Divider
N MMD = P1 + 21 P2 + ...2 n−2 Pn−1 + 2 n−1 Pn + 2 n
Transfer function
that controls
loop dynamics (LPF)
fr
÷R
+
F(s)
ffb
Multi-Modulus Controllable Signal
Source (VCO)
Divider
fo =
MMD
Modulus
control nbit
fo
fr
R
K⎤
⎡
I
+
⎢⎣
F ⎥⎦
Total divisor I+K/F
+
+
CLK
Fractional
Integer divisor I
F ti
Fractional
l di
divisor
i
K/F
1bit
z-1
+
+
+
Cout
+
log2F
K
Accumulator
Frequency synthesizer design I (PLL), FDAI, 2008
25
Fractional-N Spurious Components
Any repeatable pattern in the time domain causes spurious tones in
the frequency domain.
M a g n it u d e ( d B )
102
The fractional accumulator periodically generates the carry out that
toggles the loop division ratio Æ spurious tones at multiples of the
carryout frequency fr⋅(K/F), which is the step size of the fractional-N
synthesizer Æ the smaller the step size is
synthesizer.
is, the closer the spur locates
to the carrier.
(a)
20
101
100
99
98
4030 4040 4050
4060 4070 4080 4090
Clock Cycles
0
-20
-40
0.1
Frequency synthesizer design I (PLL), FDAI, 2008
1.0
10
26
Design a Fractional-N Synthesizer Architecture
for synthesizing 11 channels from 819.2 MHz to 820.96 MHz with a step
size of 160 kHz and reference comparison frequency of fr/R=5.12 MHz.
Determine the frequencies of fractional-N spurious components.
fr 1
⋅ = 160 kHz
Solution: The synthesizer step size is given by
R F
Since the comparison frequency is fr/R = 5.12 MHz, the fractional accumulator
size can be chosen as: F = f ⋅ 1 = 5120kHz = 32
r
R 160kHz
160kHz
which can be implemented using a 5-bit accumulator. The accumulator input, i.e., the
fine tune frequency word K, can be programmed from 0 to 10 to cover the 11 channels
f
from
819.2
819 2 MHz
MH to
t 820.96
820 96 MH
MHz with
ith step
t size
i off 160 kHz
kH (th
(the fi
firstt channel
h
ld
does nott
require any fractionality). The integer divisor ratio, i.e., the coarse tune frequency word
I, can be determined by the channel frequency. For instance, the first channel frequency
is synthesized
y
as:
fr
R
0⎞ f
⎛
⎜ I + ⎟ = r ⋅ I = 819 .2 MHz
F⎠ R
⎝
which leads to I = 160. Hence, the loop total divisor is given by N = 160 + K/32,
where K = 0, 1, … 10.
Frequency synthesizer design I (PLL), FDAI, 2008
27
Simulated Fractional Accumulator Output
Loop divisor N = 160 + 1/32 and the comparison
frequency fr/R = 5.12 MHz
161
31 clock
l k cycles
l
31 clock
l k cycles
l
160
Instantaneous Loop Divisor
(a)
10
20
30
Magnitude
e (dB)
60
70
80
Accumulator Output Spectrum
20
0
-20
-40
01
0.1
(b)
50
40
Clock Cycles
02
0.2
0 5 0.6
0 6 0.8
08
0.3
0
3 0.4
0 4 0.5
Frequency (MHz)
1
Frequency synthesizer design I (PLL), FDAI, 2008
2
28
PLL Frequency Synthesizer
id = KCP K PD (θ R − θo )
ve ( s ) = K PD (θ R − θo )
vc =
VDD
θR(s)
I
Kphase
UP
Crystal
Oscillator
DN
id
θe(s)
Loop Filter
R
PFD
I
Divider
vc
1 K VCO
⋅
N
s
Cs =
vc(s)
θ VCO ( s)
vc ( s)
VCO
=
K VCO
s
ωVCO = K VCO vc
C1C2
C1 + C2
Magnitude
Response
Gain
K vco
s
÷N
=
C2
C1
θo(s)
θo
K PD K CP (θ R − θo )(1 + sC1R )
s (C1 + C2 )(1 + sCs R )
K phase R
1
RC1
1
RCS
1
RC1
1
RCS
Phase
Response
CS
C2
ω
where CS =
C1C2
C1 + C2
∠ Phase
Frequency synthesizer design I (PLL), FDAI, 2008
ω
29
Open Loop Transfer Function
⎛ θo ⎞
K K K (1 + sC1R )
⎜⎜ ⎟⎟
= 2 VCO PD CP
⎝ θ R ⎠open loop s N (C1 + C2 )(1 + sCs R )
C2 (about C1/10) adds a high
frequency pole to clean up high
frequency ripple on the control line.
line
-40 dB/dec
Magnitude of
the Loop
Gain
Without C2 ,
Cs =
20 dB/dec
-20
C1C2
=0
C1 + C2
ω
-40
40 dB/dec
Phase of the
Loop Gain
− 90°
−135°
−180°
1
RC1
1
RCS
ω
Frequency synthesizer design I (PLL), FDAI, 2008
30
Closed Loop Transfer Function
θo
K VCO K PD K CP (1 + sC1R )
= 2
θ R s N (C1 + C2 )(1 + sCs R ) + K VCO K PD KCP (1 + sC1R )
2nd − orderPLL
Without C2 , Cs = 0
natural frequency
ωn =
K
NC1
θo
K VCO K PD K CP (1 + sC1R )
= 2
θ R s NC1 + K VCO K PD KCP (1 + sC1R )
⎞
⎛ 2ζ
⎜
ωn ⎜ s + 1⎟⎟
ω
θo
⎠
= 2 ⎝ n
θ R s + 2ζω n s + ωn 2
damping constant
ζ =
ω3dB = ωn 1 + 2ζ + 4ζ + 4ζ + 2
2
(
4
)
ω 3 dB ≈ 1 + ζ 2 ω n
ω3dB ≈ 2ζζωn = K N
2
ζ < 1 .5
ζ > 1.5
R
2
KC1
N
ζ=0.3
0.5
0.707
5
2
θo
(dB)
θR
or
0
ζ=5
-5
K VCO VC
(dB)
⋅
N ωR
-10
2
1.414
1
-15
0.707
-20
0.1
0.2
0.4
0.7 1
2
4
ω /ω n
7 10 0.5
0.3
PLL frequency response
Frequency synthesizer design I (PLL), FDAI, 2008
31
MMD Architecture Using 2/3 Cells
N MMD = 2n + 2n −1 Cn −1 + 2n −2 Cn −2 + L + 2C1 + C0
For 3 bit MMD,, N MMD ( n = 3) = 8 + 4C2 + 2C1 + C0 = 8 ~ 15
Say, we need an MMD with division ratios: 128-135.
N = 27 + 26 C6+25C5 + 24 C4 + 23C3 + 22 C2 + 21C1 + C0
The division ratios obtained using 2/3 cells: 128-255.
Frequency synthesizer design I (PLL), FDAI, 2008
32
Dual Modulus Prescaler – 2/3 Cell
modin=1 and C=1 Æ Fo/Fin=1/3; modin=1 and C=0 Æ Fo/Fin=1/2
modin=0 and p=x Æ Fo/Fin=1/2
Dual
modulus
control
Frequency synthesizer design I (PLL), FDAI, 2008
33
Tri-State PFD Circuit
H
IN
OUT
UP
CLK
FF
vR
CLK RST
vo
CLK RST
OUT
FF
H
IN
OUT
DN
RST
Positive edge-triggered D
flip flop with active low
flip-flop
reset and hidden D=1
Frequency synthesizer design I (PLL), FDAI, 2008
34
PFD Dead Zone
dead zone
id
I
0
−π
−2π
−τπ
T
π
2π θe
Phase Noise
P
-I
τπ
T
Dead
Zone
Δ
vo
vR
In band
Noise
VCO Noise
Thermal Noise Floor
Δ
Δ
DN
AND Gate
Threshold
Frequency Offset
UP
τ/2
τ/2
Frequency synthesizer design I (PLL), FDAI, 2008
35
Phase/Frequency Detector
1
Q
D
fr
rst_
active low
w reset
active high
lock detect
reset_
t
Delay
LD
polarity
if low, KV>0
if high, KV<0
rst
rst_
fV
1
Phir
D
Q
Frequency synthesizer design I (PLL), FDAI, 2008
PhiV
36
Differential Charge Pump Circuitry
VCC
CPout
UP+
DOWN+
UP-
DOWNVref
Vref
Frequency synthesizer design I (PLL), FDAI, 2008
37
2nd Order Passive Loop Filters
Charge Pump
PFD
IP
+
UP
-
DN
L
Loop
Filt
Filter
ICP
K phase
VCO
VC
R
In C 1
P
C2
÷N
The 2nd-order filter is the
highest
g
order p
passive RC
filter that can be built without
series resistors between the
charge pump and the VCO
tune line
F (s ) =
(1 + sC1R )
s (C1 + C2 )(1 + sC s R )
C1C2
Cs =
C1 + C2
Frequency synthesizer design I (PLL), FDAI, 2008
38
3rd Order Passive Loop Filters
iCP
R1
C1
F (s ) =
R3
C2
-40 dB/dec
vc
C3
Magnitude
of the Loop
Gain
-20 dB/dec
ω
-40 dB/dec
Phase of the
Loop Gain
(1 + sT1 )
sCt (1 + sT2 )(1 + sT3 )
⎧T1 = R1 ⋅ C1
⎪
⎨T2 = R1 ⋅ C1 ⋅ C2 Ct
⎪T ≈ R ⋅ C
3
3
⎩ 3
⎧Ci << C1 ,
⎪
⎨ C2 T3
⎪ C + T >> 1
1
⎩ 3
Ct = C1 + C2 + C3
Legend:
2nd Order PLL
3rd Order PLL
4th Order PLL
-60 dB/dec
− 90°
− 135 °
− 180°
− 270 °
Filter Filter
Zero Pole(s)
ω
Comparison of open loop
gain and phase in a second,
third, and fourth order PLL
Frequency synthesizer design I (PLL), FDAI, 2008
39
PLL Phase Noise and Spurs
PLL output
vout (t ) = Vo cos(ω LO t + ϕ n (t ))
Random fluctuations in the phase
vout (t ) = V0 cos[ωLOt + ϕ p sin(ωmt )] =
ϕ n (t ) = ϕ p sin (ω m t )
V0 [cos(ωLOt ) cos(ϕ p sin(ωmt )) − sin(ωLOt )sin(ϕ p sin(ωmt ))]
For a small phase fluctuation:
v0 (t ) = V0 [cos(ω LO t ) − ϕ p sin (ω m t )sin (ω LO t )]
ϕp
⎡
⎤
[cos(ω LO − ω m )t − cos(ω LO + ω m )t ]⎥
= V0 ⎢cos(ω LO t ) −
2
⎣
⎦
Single sideband (SSB) phase noise power
spectral density (PSD) to carrier ratio is
defined as the ratio of power in one phase
modulation sideband per Hertz bandwidth, at
an offset Δω away from the carrier, to the
total signal power in units of [dBc/Hz]:
⎡ Noise(ω LO + Δω ) ⎤
PN SSB (Δω ) = 10 log
l ⎢
⎥
⎣ Pcarrier (ω LO ) ⎦
⎡ 1 ⎛ V0ϕ p ⎞2 ⎤
⎟ ⎥
⎢ ⎜
2
⎡ϕ p2 ⎤
⎡ϕ rms
⎤
2⎝ 2 ⎠ ⎥
dB ⎤
⎡ dBc
⎢
PN SSB (Δω ) ⎢
=
10
log
=
10
log
=
10
log
⎥
⎢
⎢
⎥
⎥
⎢ 1 2 ⎥
⎣ Hz ⎦
⎣ 2 ⎦
⎣4⎦
⎥
⎢ 2 V0
⎥⎦
⎢⎣
The rms phase noise or jitter:
ϕ rms (Δf ) =
180
π
10
PN DSB ( Δf )
10
=
180 2
π
10
PNSSB ( Δf )
10
[deg/
Hz
The integrated rms phase noise or jitter:
Jitterrms [rms deg ] =
Δf 2
∫ϕ
2
rms
( f )df
Δf1
Frequency synthesizer design I (PLL), FDAI, 2008
40
]
Spectrum analyzer basic block diagram
RF Input
Attenuator
Filter
IF
Gain
IF
Filter
Log
Amp Detector
Input
Video
Filter
LO
Frequency
Reference
Sweep
Generator
Display
Frequency synthesizer design I (PLL), FDAI, 2008
41
PLL Phase Noise Sources
G (s ) = k PDGLPF kVCO s
θREF
θR
kPD
%R
+
PD
kVCO/s
GLPF
+
VC O
+
θVCO
θPD+θLPF
LPF
LPÆin band noise
NTF
+
%N
+
output
S0
HPÆout of band noise
REF
Close loop transfer function
Nk PD G LPF kVCO
⎛ G
⎞
⎟=
⎜
⎝ 1 + G / N ⎠ Ns + k PD G LPF kVCO
θN
Total output noise power spectral density
⎡ S REF
S PD + S LPF ⎤⎛ G ⎞
1
⎛
⎞
S0 ( f ) = ⎢ 2 + S R + S N +
S
+
⎜
⎜
⎟
⎟
VCO
⎥
2
k PD
⎝1+ G / N ⎠
⎣ R
⎦⎝ 1 + G / N ⎠
2
LPF
HPF
Frequency synthesizer design I (PLL), FDAI, 2008
2
1
1⎛ G ⎞
⎛
⎞
⎜
⎟
⎟ = 1− ⎜
N ⎝1+ G / N ⎠
⎝1+ G / N ⎠
42
In-band PLL Phase Noise
2
⎡ SREF
SPD + SLPF⎤⎛ NkPDGLPFkVCO ⎞ ⎡ SREF
SPD + SLPF⎤ 2
⎜⎜
⎟⎟ →⎢ 2 + SR + SN +
N
S0( f ) = ⎢ 2 + SR + SN +
⎥
⎥
2
2
→
s
0
kPD ⎦⎝ Ns+ kPDGLPFkVCO⎠ ⎣ R
kPD ⎦
⎣R
PLL magnifies the noise from the reference, phase detector, LPF and
the dividers by the amount of 20logN dB Æ Smaller N leads to lower
in-band noise.
For integer-N
g
Synthesizer:
y
output
p frequency
q
y Fo=Fref*N,, step
p size =
Fref Æ cannot simultaneously achieve fine step size and small N Æ
poor in-band noise performance.
For fractional-N Synthesizer: output frequency Fo=Fref*(N+K/F), step
size = Fref/F Æ can achieve fine step size and small N
simultaneously. Æ better in-band noise performance.
Frequency synthesizer design I (PLL), FDAI, 2008
43
Out-of-Band PLL Phase Noise
The noise outside of the PLL bandwidth is determined by the VCO
phase noise, namely,
2
⎛
⎞
1
⎜
⎟⎟ → SVCO
S 0 ( f ) = SVCO ⎜
⎝ 1 + k PD G LPF kVCO Ns ⎠ s →∞
⎧⎪ FkT
SVCO (Δf ) = 10 log⎨
⎪⎩ 2 Ps
2
⎡ ⎛
f0 ⎞ ⎤ ⎡
f c ⎤ ⎫⎪
⎟⎟ ⎥ ⋅ ⎢1 +
⎢1 + ⎜⎜
⎥⎬
2
Δ
f
⋅
Q
Δ
f
⎢⎣ ⎝
L ⎠ ⎥
⎦⎥ ⎪⎭
⎦ ⎣⎢
Flicker 1/f noise is caused by trapping in the semiconductor material
material.
Flicker noise corner fc is an empirical parameter depending on the
device size and processing. For CMOS, fc is found to be 3~7 kHz
typically
yp
y and for bipolar
p
transistors fc is about as 50 kHz. Notice that fc
has impact only on close-in noise. QL is the loaded Q of the resonant
circuit, ranging from 5~20 for on-chip resonator and 40~80 for off-chip
tank. Ps is the average signal power at output of the oscillator active
device, and F is oscillator effective noise factor.
Frequency synthesizer design I (PLL), FDAI, 2008
44
Simulated PLL Phase Noise Sources
3. Crystal/CP Intercept
er n
ois
e
Cr y
stal
n
CP nois
oise
e
2. CP/VCO Intercept
p
1. ΣΔ/VCO Intercept
PD noise
no
ise
nois
e
O
VC
ΣΔ
Div
id
Frequency synthesizer design I (PLL), FDAI, 2008
45
Simulated PLL Phase Noise With Loop Effect
Div
ider
nois
e
Crys
tal n
oise
To
t al
CP
no
i
se
i
no
PD noise
se
se
noi
F
LP
ise
no
ΣΔ
O
VC
ise
no
Frequency synthesizer design I (PLL), FDAI, 2008
46
Comparison of Measured and Simulated
Phase Noise
-60
60
Bc/Hz)
Phase Noise (dB
-70
Frequency
Band
Simulated
Phase
Noise
Measured
Phase
Noise
3.23 3GHz
3.3GHz
0.44°rms
0.50°rms
4.14.3GHz
0.50°rms
0.535°rms
-80
-90
-100
-110
-120
-130
-140
Parameter
Value
-150
C1
3nF
C2
600pF
R
600Ω
-160
0.1
1.0
10
100
Frequency Offset (kHz)
1000
10000
Frequency synthesizer design I (PLL), FDAI, 2008
47
References
‰ J. Rogers, C. Plett, and F. Dai, “Integrated Circuit Design for High-Speed
Frequency Synthesis,” Boston: Artech House, 2006.
‰ F. Dai and C. Stroud, “Analog and Mixed-Signal Test Architectures,” Chapter
15 in System-on-Chip Test Architectures: Nanometer Design for Testability,
Morgan Kaufmann Publishers, 2007.
‰ J. Rogers, F. Dai and C. Plett, “Frequency Synthesis for Multi-band Wireless
Networks,” Chapter 15 in Emerging Wireless Technologies -- From System to
Transistors, CRC Press, 2007.
‰ B. Razavi, RF Microelectronics, Upper Saddle River, New Jersey: Prentice
Hall PTR, 1998.
‰ J. Rogers, F. F. Dai, M. S. Cavin, and D. G. Rahn, “A Fully Integrated MultiBand SD Fractional-N Frequency Synthesizer for a MIMO WLAN Transceiver
RFIC ” IEEE Journal of Solid-State Circuits,
RFIC,
Circuits vol
vol. 40
40, no
no. 33, pp
pp. 678-689
678-689, March
March,
2005.
Frequency synthesizer design I (PLL), FDAI, 2008
48
RFIC Design and Testing for Wireless
Communications
A Full-Day Tutorial at VLSI Design & Test Symposium
July 23, 2008
Lecture 3: RF Design II
Vishwani D. Agrawal
Foster Dai
Auburn University, Dept. of ECE, Auburn, AL 36849, USA
49
Phase Noise Specification of Oscillators
Example of oscillator
periodic waveforms
‰ Phase noise. We desire accurate periodicity with all signal power concentrated in one
discrete oscillator frequency Æ an impulse function in frequency domain.
domain However,
However all
real oscillators have less than perfect spectral purity and thus they develop “skirts”.
Power in the skirts is evidence of phase noise, Phase noise is any noise that charges
the frequency or phase of the oscillator waveform. Phase noise is given by:
P
Spectrum of a
typical oscillator
PN = P0 / N0
noise floor
fo
f
Where Po is the power in the tone at the frequency of oscillation and No is the
noise power spectral density at some specified offset from the carrier. Phase
noise
i iis usually
ll specified
ifi d iin dBc/Hz,
dB /H meaning
i noise
i att 1
1-Hz
H b
bandwidth
d idth measured
d
in decibels with respect to the carrier.
Frequency synthesizer design I (PLL), FDAI, 2008
50
LC Resonator – Core of Oscillators
i(t ) = I
‰ If
pulse
δ (t )
is applied to a parallel resonator, the time
domain response of the system can be found as:
2 I pulse e
vout =
•
−t
2 RC
C
⎞
⎛ 1
1
⎜
cos⎜
−
• t ⎟⎟
2 2
⎠
⎝ LC 4 R C
L
C
R
Oscillation frequency
ω OSC =
•
1
1
−
LC 4 R 2 C 2
Damping must be
vout(t) eliminated for the
waveform to persist!
Amplitude
In most oscillators,
R >> L / C
ω OSC =
1
LC
i(t)
time
Damped LC resonator with current
step applied.
Frequency synthesizer design I (PLL), FDAI, 2008
51
Adding Negative Resistance Through
Feedback to Resonator
a)
b)
L
C
Rp
L
C
rp
-rn
-Rn
The addition of negative resistance to the circuit to overcome
losses in a)) a parallel
p
resonator or b)) a series resonator.
Vin(s)
Vout(s)
+
H1(s)
H2(s)
Linear model of an oscillator as a feedback control system.
system
Frequency synthesizer design I (PLL), FDAI, 2008
52
Barkhausen Criterion
•
Closed loop gain
Vout ( s )
H 1 (s)
=
Vin ( s ) 1 − H 1 ( s ) H 2 ( s )
•
Condition for oscillation: denominator approaches zero. Æ To find
the closed-loop poles
1 − H 1 (s) H 2 (s) = 0
•
•
For sustained oscillation at constant amplitude,
the pole must be on the jω axis. For the openl
loop
analysis
l i
positive
feedback with
gain larger than
H 1 ( j ω ) H 2 ( jω ) = 1
or equal to 1.
Barkhausen criterion, which states that for sustained oscillation at
constant amplitude, the gain around the loop is 1 and the phase
around the loop is 0 or some multiple of 2π.
H 1 ( jω ) H 2 ( jω ) = 1
∠H 1 ( j ω ) H 2 ( j ω ) = 2 n π
Frequency synthesizer design I (PLL), FDAI, 2008
53
VCO Output Spectral Purity
Noise in one sideband in a 1Hz bandwidth:
noise power in 1Hz BW at wo+Δw
Ltotal(Δw) = ————————————————
Carrier power
Units: dBc/Hz
VCO Output
p Spectrum
p
Frequency synthesizer design I (PLL), FDAI, 2008
54
Popular Implementation of Feedback to Resonator
(b)
(a)
(c)
Buffer
L
G
G
G
Amplifier
Amplifier
Amplifier
Resonators with feedback. (a) Colpitts Oscillator.
(b) Hartley Oscillator (not suitable for IC). (c) -Gm oscillator.
v
t
growth
Waveform of an LC resonator with losses
compensated.
p
The oscillation ggrows until a
practical constraint limits the amplitude.
limited
Frequency synthesizer design I (PLL), FDAI, 2008
55
Negative Resistance of Colpitts Amplifier
vin = iin ( jX 1 + jX 2 ) + g m vbe ( jX 2 )
Negative Impedance, if X1
and X2 are the same type
vini
Z in =
= − g m X 1 X 2 + j(X 1 + X 2 )
iin
gm
1
1
Z in = − 2
+
+
ω C1C 2 jωC1 jωC 2
To start the oscillation,
Oscillation frequency
− g m X 1 X 2 > RL
g m > RLω 2 C1C 2
f osc
1
=
2π
Load reactance needs
to equal –j(X1+X2) Æ
add an inductor
⎡1 ⎛ 1
1 ⎞⎤
⎢ ⎜⎜ + ⎟⎟⎥
⎣ L3 ⎝ C1 C2 ⎠⎦
1
2
Frequency synthesizer design I (PLL), FDAI, 2008
56
Impedance Transform for LC Oscillator
Drive low
impedance
ÆG<1
Increase the
impedance
seen by tank
Frequency synthesizer design I (PLL), FDAI, 2008
Impedance
seen by
tank =
n2/g
/ m
57
Passive Impedance Transformer
Impedance
seen by
b tank
k
=(1+C1/C2)2/gm
Impedance
seen by tank =
(1+L2/L1)2/gm
For negligible
loading on the
tank, C1 > 10C2
Æ needs a
large cap.
58
Frequency synthesizer design I (PLL), FDAI, 2008
– Gm Amplifier to Cross-Coupled LC Oscillator
Active Impedance Transformer
Commonly used
differential VCO topology
Frequency synthesizer design I (PLL), FDAI, 2008
59
Negative Resistance of – Gm Oscillator
ii
vπ2
vi
gm1vπ1
vπ1
ii =
•
•
re2
gm2vπ2
re1
vi
= − g m1vπ 1 − g m 2 vπ 2
re1 + re 2
Both transistors are biased
identically,
Zi =
−2
gm
Condition for oscillation is that
gm >
2
Rp
where Rp is the equivalent parallel resistance of the resonator.
Frequency synthesizer design I (PLL), FDAI, 2008
60
VCO Mathematical Model
Output frequency of an ideal VCO: wout = wFR + Kvco Vc
t
Sinusoidal output: y(t) = A cos ( wFR t + Kvco ∫ Vc dt )
-∞
Open loop Q :
Where
Q = (w0/2) |dφ/dw |
w0
φ
is the center frequency
is the phase of open loop transfer function
Frequency synthesizer design I (PLL), FDAI, 2008
61
PMOS VCO with Automatic Amplitude Control
•
•
•
•
Large Vtune range (almost
L
( l
t from
f
0V ~ Vcc
V V)
V).
Tank can be connected to ground rather than DC Ælower phase noise
and diodes can be connected in the proper polarity without additional
biasing.
PMOS transistors
t
i t
can be
b operated
t d into
i t saturation
t
ti without
ith t affecting
ff ti the
th
VCO noise performance Æ higher output swing than bipolar VCO.
High phase noise below 100kHz offset (due to high flicker noise) Æ can
be tolerated by wider loop bandwidth (> 100kHz).
Vcc
CTail
iout+
RBB
Q5
Q6
IBais
M3
M4
LTail
VBias
iout-
RBB
M1
Cvar V Cvar
tune
L
L
M6
D1
RB1
Ibg
Q5
Q4
Q3
M2
Cc
Cc
M5
C1
Vcc
Vcc
Vcc
Rref
RB2
D2
D3
Q1
RE
Q2
RE
Frequency synthesizer design I (PLL), FDAI, 2008
62
Linear or Additive Phase Noise - Leeson’s Formula
Nin(s)
Nout(s)
+
Oscillator Phase Noise Φn(t)
H1(s)
VOSC = A cos[ω 0 t + φ n (t )]
H2(s)
N out ( s )
H 1(s)
=
N in ( s ) 1 − H ( s )
‰ Noise close loop transfer function
•
Open
p loop
p transfer function
H(s) = H1(s)H2(s)
•
Oscillation conditions
•
Noise power
N out ( s )
N in ( s )
H ( jω ) ≈ H ( jω 0 ) + Δ ω
H 1 ( jω 0 ) = H 1
H ( jω 0 ) = 1
2
=
H1
(Δ ω )2
dH
dω
2
dH
dω
2
Frequency synthesizer design I (PLL), FDAI, 2008
63
Oscillator Phase Noise – Leeson’s Equation
d H jφ
dH
e + H je
=
dω
dω
H (ω ) = H e jφ
ignorable
dH
dω
•
2
=
dominant
2
d H
+ H
dω
2
dφ
dω
jφ
dφ
dω
Orthogonal
2
At resonance, the phase changes much faster than magnitude, and |H|=1 near
resonance. Æ ignore amplitude noise and AM to PM conversion as well.
dH
dω
2
dφ
=
dω
2
ω 0 dφ
Q=
2 dω
N out ( s )
N in ( s )
2
N out ( s )
N in ( s )
2
=
H1
(Δ ω )
2
2
dφ
dω
2
H 1 ω 02
2
=
4 Q 2 (Δ ω )
Frequency synthesizer design I (PLL), FDAI, 2008
2
64
Oscillator Phase Noise – Leeson’s Equation
•
If feedback path is unity, then H1=H, and since |H|=1 near resonance
N out ( s )
N in ( s )
•
=
ω 02
4 Q 2 (Δ ω )
2
Phase noise is quoted as an absolute noise referred to the carrier power
PN =
•
•
2
N out ( s )
2 PS
2
⎛ H1 ω0 ⎞
⎟
= ⎜⎜
⎟
⎝ (2 Q Δ ω ) ⎠
2
⎛ N in ( s )
⎜
⎜ 2P
S
⎝
⎞
⎟
⎟
⎠
Ps is the signal power at active device input.
input
If the transistor and bias were noiseless, then the only noise present
would be due to the resonator losses. The transistors and the bias will
add noise to the minimum noise of
N in ( s )
2
= kT
Frequency synthesizer design I (PLL), FDAI, 2008
65
Oscillator Phase Noise – Leeson’s Equation
Active
A
ti Device
D i noise:
i
‰ If ρ is the fraction of cycle for which the
transistors are completely switched, int is the
j
into the oscillator from the
noise current injected
bias during this time.
‰ During transitions (1- ρ), the transistors act like an
amplifier, and collector shot noise icn usually
dominates
dominates.
c)) -G
G
L
C
Q2
Q1
Ibias
O ill t
m Oscillator
N in ( s )
2
= kT +
i nt2 R p
2
ρ + i cn2 R p (1 − ρ )
Resonator loss
Bias noise
(source)
F =1+
i Rp
2
nt
2 kT
ρ+
Transistor shot
noise
i R p (1 − ρ )
2
cn
kT
Rp is the
equivalent
parallel
resistance of the
tank.
2
⎛ H 1 ω 0 ⎞ ⎛ FkT ⎞
⎜
⎟ ⎜
PN = ⎜
⎟
⎟
⎝ (2 Q Δ ω ) ⎠ ⎝ 2 Ps ⎠
Frequency synthesizer design I (PLL), FDAI, 2008
66
Oscillator Phase Noise – Leeson’s Equation
•
It has been assumed that flicker noise is insignificant at the frequencies
of interest. This may not be the case for CMOS designs. If ωc represents
the flicker noise corner where flicker noise and thermal noise are equal,
2
phase⎛noise
is
given
by
H 1 ω 0 ⎞ ⎛ FkT
ωc ⎞
⎞⎛
⎟ ⎜
+
PN = ⎜⎜
1
⎟ ⎝ 2 Ps ⎟⎠⎜⎝ Δω ⎟⎠
(
)
Δ
2
Q
ω
⎝
⎠
•
Assuming unity feedback, oscillator output spectrum density
Phase noise
Ph
i att
Df from carrier
⎧⎪ FkT
SVCO (Δf ) = 10 log ⎨
30 dB/decade
⎪⎩ 2 Ps
2
⎡ ⎛
f0 ⎞ ⎤ ⎡
f c ⎤ ⎫⎪
⎟⎟ ⎥ ⋅ ⎢1 +
⎢1 + ⎜⎜
⎥⎬
⎢⎣ ⎝ 2Δf ⋅ QL ⎠ ⎥⎦ ⎢⎣ Δf ⎥⎦ ⎪⎭
20 dB/decade
Thermal noise floor
fc
f
Frequency synthesizer design I (PLL), FDAI, 2008
67
Simulated PLL Phase Noise Sources
3. Crystal/CP Intercept
er n
oi s
e
Cr y
stal
n
C P nois
e
2. CP/VCO Intercept
oise
1. ΣΔ/VCO Intercept
PD noise
no
ise
nois
e
O
VC
ΣΔ
Div
id
Frequency synthesizer design I (PLL), FDAI, 2008
68
Simulated PLL Phase Noise With Loop Effect
nois
e
Crys
ta
l noi
se
To
ta l
no
CP
ise
no
PD noise
F
LP
ise
no
se
ise
no
noi
O
VC
ise
ΣΔ
Div
ider
Frequency synthesizer design I (PLL), FDAI, 2008
69
Comparison of Measured and Simulated
Phase Noise
-60
Bc/Hz)
Phase Noise (dB
P
-70
-80
-90
-100
Frequency
Band
Simulated
Phase
Noise
Measured
Phase
Noise
3.23.3GHz
0.44°rms
0.50°rms
4.14 3GHz
4.3GHz
0.50°rms
0.535°rms
-110
-120
-130
-140
-150
-160
0.1
1.0
10
100
Frequency Offset (kHz)
1000
10000
Parameter
Value
C1
3nF
C2
600pF
R
600Ω
Frequency synthesizer design I (PLL), FDAI, 2008
70
RFIC Design and Testing for Wireless
Communications
A Full-Day Tutorial at VLSI Design & Test Symposium
July 23, 2008
Lecture 4: Power and Gain Measurements
Vishwani D. Agrawal
Foster Dai
Auburn University, Dept. of ECE, Auburn, AL 36849, USA
71
Testing
‰ Definition: Having designed and fabricated a device, testing
must determine whether or not the device is free from any
manufacturing defect.
‰ Testing is distinctly different from verification, which checks
the correctness of the design.
‰ Forms of testing:
g
■ Production testing
■ Characterization testing
72
Production Testing
‰ Applied to every manufactured device
‰ Major
j considerations
■ Reduce cost; minimize test time per device.
■ Maximize quality; reduce defect level (DL), defined as
fraction of bad devices passing test.
‰ Reference
■ M. L. Bushnell and V. D. Agrawal, Essentials of Electronic
Testing for Digital, Memory & Mixed-Signal VLSI Circuits,
Boston: Springer,
Springer 2000,
2000 Chapter 33.
73
Method of Production Testing
Automatic Test Equipment (ATE) System
Test
Program
User
Interface
Test computer
DSP
RF sources
Signal generators
Handler
(Feed robatics,
Binning)
DUTs
Contactors
Probe cards
Load boards
74
Some Features of Production ATE
‰ Binning: Tested DUTs are grouped as
■ Passing the entire test
■ Failing any of the tests
■ Failing because of dc test
■ Failing
F ili because
b
off RF T
Testt
■ Failing speed (maximum clock frequency) test
‰ Multisite testing: Testing off several DUTs is parallelized to
reduce the test cost.
‰ Test time for a typical device: 1 – 2 seconds.
‰ Testing cost of a device: 3 – 5 cents.
75
Characterization Testing
‰ Performed at the beginning of production phase.
‰ Objective:
j
To verifyy the design,
g , manufacturability,
y, and test
program.
‰ Method:
■ Few devices tested very thoroughly
g
■ Failures are often diagnosed
■ Tests are more elaborate than the production tests
■ Test time (and testing cost) not a consideration
■ Test program is verified and corrected in necessary
■ ATE system and additional laboratory setup may be used
76
RF Tests
‰ Basic tests
■ Scattering parameters (S-parameters)
■ Frequency and gain measurements
■ Power measurements
■ Power
P
efficiency
ffi i
measurements
t
‰ Distortion measurements
‰ Noise measurements
77
Scattering Parameters (S-Parameters)
‰ An RF function is a two-port device with
■ Characteristic impedance (Z0):
● Z0 = 50Ω for wireless
ireless communications
comm nications devices
de ices
● Z0 = 75Ω for cable TV devices
■ Gain and frequency characteristics
‰ S-Parameters of an RF device
■ S11 : input return loss or input reflection coefficient
■ S22 : output return loss or output reflection coefficient
■ S21 : g
gain or forward transmission coefficient
■ S12 : isolation or reverse transmission coefficient
‰S
S-Parameters
a a ete s are
a e complex
co p e numbers
u be s and
a d can
ca be expressed
e p essed in
decibels as 20 × log | Sij |
78
Active or Passive RF Device
a1
Port 1
(input)
a2
RF
Device
b1
Input return loss
Output return loss
Gain
Isolation
Port 2
(output)
b2
S11 = b1/a1
S22 = b2/a2
S21 = b2/a1
S12 = b1/a2
79
S-Parameter Measurement by Network Analyzer
Directional couplers
DUT
a1
Digitizer
b1
Directional couplers
a2
Digiti er
Digitizer
b2
80
Application of S-Parameter: Input Match
‰ Example: In an S-parameter measurement setup, rms value of
input voltage is 0.1V and the rms value of the reflected voltage
wave is 0.02V. Assume that the output of DUT is perfectly
matched. Then S11 determines the input match:
■ S11 = 0.02/0.1 = 0.2, or 20 × log (0.2) = –14 dB.
■ Suppose the required input match is –10 dB; this device
passes the test.
test
‰ Similarly, S22 determines the output match.
81
Gain (S21) and Gain Flatness
‰ An amplifier of a Bluetooth transmitter operates over a frequency
band 2.4 – 2.5GHz. It is required to have a gain of 20dB and a gain
fl t
flatness
off 1dB.
1dB
‰ Test: Under properly matched conditions, S21 is measured at
several frequencies in the range of operation:
● S21 = 15.31 at 2.400GHz
● S21 = 14.57
14 57 at 2.499GHz
2 499GHz
‰ From the measurements:
● At 2.400GHz,
2 400GH G
Gain
i = 20×l
20×log 15.31
15 31 = 23
23.70
70 dB
● At 2.499GHz, Gain = 20×log 14.57 = 23.27 dB
‰ Result:
R lt Gain
G i andd gain
i flatness
fl t
meett specification.
ifi ti Measurements
M
t
at more frequencies in the range may be useful.
82
Power Measurements
‰ Receiver
■ Minimum detectable RF power
■ Maximum
M i
allowed
ll
d iinput power
■ Power levels of interfering tones
‰ Transmitter
■
■
■
■
Maximum RF power output
Changes in RF power when automatic gain control is used
RF power distribution over a frequency band
Power-added efficiency (PAE)
‰ Power
P
unit:
it dB
dBm, relative
l ti to
t 1mW
1 W
■ Power in dBm
= 10 × log (power in watts/0.001 watts)
■ Example:
p 1 W is 10×log
g 1000 = 30 dBm
■ What is 2 W in dBm?
83
Power Spectrum Measurements
‰ Spur measurement
‰ Harmonic measurement
‰ Adjacent channel interference
84
Spur Measurement
‰ “Spur” is a spurious or unintended frequency in the output of an RF device.
‰ Example: leakage of reference frequency used in the phase detector of PLL.
‰ A spur can violate the channel interference standard of a communication
system.
‰ Complete power spectrum measured in characterizing phase to determine
RF power sspectrum
R
(dBm/M
MHz)
which interfering frequencies should be checked during production testing.
– 10
SPUR
– 40
– 80
0
200
400
600
800
MHz
1000
1200
1400
85
Harmonic Measurements
‰ Multiples of the carrier frequency are called harmonics.
‰ Harmonics are g
generated due to nonlinearityy in semiconductor
devices and clipping (saturation) in amplifiers.
‰ Harmonics may interfere with other signals and must be
measured to verify that a manufactured device meets the
specification.
p
86
Adjacent Channel Power Ratio (ACPR)
‰ Ratio of average power in the adjacent frequency channel to the
average power in the transmitted frequency channel.
‰ Also known as adjacent channel leakage ratio (ACLR).
‰ A measure of transmitter performance.
87
Power-Added Efficiency (PAE)
‰ Definition: Power-added efficiency of an RF amplifier is the ratio
of RF power generated by the amplifier to the DC power
supplied:
■ PAE = ΔPRF / PDC where
ƒ ΔPRF = PRF(output)
( t t) – PRF(input)
(i t)
ƒ Pdc = Vsupply × Isupply
‰ Important
I
t t for
f power amplifier
lifi (PA).
(PA)
‰ 1 – PAE is a measure of heat generated in the amplifier, i.e., the
battery power that is wasted.
‰ In mobile phones PA consumes most of the power. A low PAE
reduces the usable time before battery recharge.
88
PAE Example
‰ Following measurements are obtained for an RF power
amplifier:
● RF Input power
=
+2dBm
● RF output power
=
+34dBm
● DC supply voltage =
3V
● DUT current
=
2.25A
‰ PAE is calculated as follows:
● PRF(input) = 0.001 × 102/10
= 0.0015W
● PRF(output) = 00.001
001 × 1034/10
= 2.5118W
2 5118W
● Pdc
= 3× 2.25
= 6.75W
● PAE = (2.5118
(2 5118 – 0.00158)/6.75
0 00158)/6 75 = 0.373
0 373 or 37
37.2%
2%
89
Automatic Gain Control Flatness(SOC DUT)
‰ Tester pseudocode:
■ Set up input signal to appropriate frequency and power level
■ Set up output measurement equipment to receive output
signal when triggered
■ Program
P
SOC AGC tto fifirstt gain
i llevell and
d trigger
ti
receiver
i
● Cycle SOC AGC to next gain level
● Wait long enough to capture relevant data
● Cycle to next gain level and repeat though all levels
‰ Transfer time-domain data to host computer for processing
■ Power at ith gain level = 20 × log [VR(i)2 + Vi(i)2]1/2 + 13 dBm for
p
, where VR and Vi are the
50Ω characteristic impedance,
measured real and imaginary voltages
90
Power (dBm)
AGC – Other Characteristics
0.6
Ideal
0.4
0.2
0.0
Power (dBm)
0
0.6
200
Time (μs)
400
600
Actual measurement
Overshoot
0.4
Missing
gain step
0.2
Nonlinearity
0.0
0
200
Time (μs)
400
600
91
AGC Characteristics to be Verified
‰ Gain errors and missing levels
‰ Overshoots and undershoots – settling
g time
‰ Finite (non-zero) transition times
‰ Varying gain steps – nonlinearity; DNL (differential nonlinearity)
and INL (integral nonlinearity) similar to ADC and DAC
92
RF Communications Standards
Frequency range Channel
F
Ch
l
(MHz)
bandwidth (MHz)
802.11b (WLAN)
2400-2500
802 11 / (WLAN) 2400
802.11a/g
2400-2500
2500 (g)
( )
5000-6000 (a)
802 16a (WIMAX)
802.16a
802.15 (UWB)
GSM
2000-11000
2000
11000
3 most common
bands: 2500,
3400, 5800
3100-10600
3 bands: 890-960
1710-1880
1850 1990
1850-1990
CDMA 2000
450, 800, 1700,
1900, 2100
Bluetooth
2,400-2,500
22
16.8
Data
D
t rate
t
(Mbps)
M d l ti format
Modulation
f
t
11
CCK
54
OFDM, 52
OFDM
subcarriers (4 pilots,
48 data channels)
1.25-20
Up to 75
OFDM, 256
OFDM
Subcarriers(200
actually used; 192
are data channels
528
53.3-480
OFDM
0 200
0.200
0 270
0.270
GMSK
1.25
0.060-0.100
1
CDMA
FSK
93
RFIC Design and Testing for Wireless
Communications
A Full-Day Tutorial at VLSI Design & Test Symposium
July 23, 2008
Lecture 5: Testing for Distortion
Vishwani D. Agrawal
Foster Dai
Auburn University, Dept. of ECE, Auburn, AL 36849, USA
94
Distortion and Linearity
‰ An unwanted change in the signal behavior is usually referred
to as distortion.
‰ The cause of distortion is nonlinearity of semiconductor
devices constructed with diodes and transistors.
‰ Linearity:
■ Function f(x)
( ) = ax + b,, although
g a straight-line
g
is not referred
to as a linear function.
■ Definition: A linear function must satisfy:
● f(x + y) = f(x) + f(y), and
● f(ax) = a f(x), for all scalar constants a
95
Linear and Nonlinear Functions
f(x)
f(x)
slope
l
=a
b
b
x
x
f(x) = ax + b
f(x) = ax2 + b
f(x)
slope = a
x
f(x) = ax
96
Generalized Transfer Function
‰ Transfer function of an electronic circuit is, in general, a
nonlinear function.
‰ Can be represented as a polynomial:
■ vo = a0 + a1 vi + a2 vi2 + a3 vi3 + · · · ·
■ Constant term a0 is the dc component that in RF circuits is
usually removed by a capacitor or high-pass filter.
■ For
F a lilinear circuit,
i i a2 = a3 = · · · · = 00.
Electronic
vi
circuit
vo
97
Effect of Nonlinearity on Frequency
‰ Consider a transfer function, vo = a0 + a1 vi + a2 vi2 + a3 vi3
‰ Let vi = A cos ωt
‰ Using the identities (ω = 2πf):
● cos2 ωt = (1 + cos 2ωt)/2
● cos3 ωt = (3 cos ωt + cos 3ωt)/4
‰ We get,
● vo
=
a0 + a2A2/2 + ((a1A + 3a3A3/4)) cos ωt
+ (a2A2/2) cos 2ωt + (a3A3/4) cos 3ωt
98
Problem for Solution
‰ A diode characteristic is, I = Is ( eαV – 1)
‰ Where, V = V0 + vin, V0 is dc voltage and vin is small signal ac
voltage. Is is saturation current and α is a constant that
depends on temperature and the design parameters of diode.
‰ Using the Taylor series expansion, express the diode current I
as a polynomial in vin.
I
0
V
– Is
99
Linear and Nonlinear Circuits and Systems
‰ Linear devices:
■ All frequencies in the output of a device are related to input
by a proportionality, or weighting factor, independent of
power level.
■ No frequency will appear in the output
output, that was not present
in the input.
‰ Nonlinear devices:
■ A true linear device is an idealization. Most electronic
devices are nonlinear.
■ Nonlinearity in amplifier is undesirable and causes
distortion of signal.
■ Nonlinearity in mixer or frequency converter is essential.
100
Types of Distortion and Their Tests
‰ Types of distortion:
■ Harmonic distortion: single-tone test
■ Gain compression: single-tone test
■ Intermodulation distortion: two-tone or multitone test
● Source
S
intermodulation
i t
d l ti di
distortion
t ti (SIMD)
● Cross Modulation
‰ Testing procedure: Output
O
spectrum measurement
101
Harmonic Distortion
‰ Harmonic distortion is the presence of multiples of a
fundamental frequency of interest. N times the fundamental
frequency is called Nth harmonic.
‰ Disadvantages:
■ Waste of power in harmonics.
■ Interference from harmonics.
‰ Measurement:
■ Single-frequency input signal applied.
■ Amplitudes of the fundamental and harmonic frequencies
are analyzed to quantify distortion as:
● Total harmonic distortion (THD)
● Signal, noise and distortion (SINAD)
102
Problem for Solution
‰ Show that for a nonlinear device with a single frequency input
of amplitude A, the nth harmonic component in the output
always contains a term proportional to An.
103
Total Harmonic Distortion (THD)
‰ THD is the total power contained in all harmonics of a signal
expressed as percentage (or ratio) of the fundamental signal
power.
‰ THD(%) = [(P2 + P3 + · · · ) / Pfundamental ] × 100%
‰ Or THD(%) = [(V22 + V32 + · · · ) / V2fundamental ] × 100%
■ Where P2, P3, . . . , are the power in watts of second, third, . . . ,
harmonics, respectively, and Pfundamental is the fundamental signal power,
■ And V2, V3, . . . , are voltage amplitudes of second, third, . . . , harmonics,
respectively,
p
y, and Vfundamental is the fundamental signal
g amplitude.
p
‰ Also, THD(dB) = 10 log THD(%)
‰ For an ideal distortionless signal,
signal THD = 0% or – ∞ dB
104
THD Measurement
‰ THD is specified typically for devices with RF output.
‰ The fundamental and harmonic frequencies
q
together
g
are often
beyond the bandwidth of the measuring instrument.
‰ Separate power measurements are made for the fundamental
and each harmonic.
‰ THD is tested at specified power level because
■ THD may be small at low power levels.
■ Harmonics appear
pp when the output
p p
power of an RF device is
raised.
105
Signal, Noise and Distortion (SINAD)
‰ SINAD is an alternative to THD. It is defined as
SINAD ((dB)) = 10 log
g10 [(
[(S + N + D)/(N
) ( + D)]
)]
where
■ S = signal power in watts
■ N = noise power in watts
■ D = distortion (harmonic) power in watts
‰ SINAD is normally measured for baseband signals.
106
Problems for Solution
‰ Show that SINAD (dB) > 0.
‰ Show that for a signal
g with large
g noise and high
g distortion,,
SINAD (dB) approaches 0.
‰ Show that for any given noise power level, as distortion
increases SINAD will drop.
‰ For a noise-free signal show that SINAD (dB) = ∞ in the
absence of distortion.
107
Gain Compression
‰ The harmonics produced due to nonlinearity in an amplifier
reduce the fundamental frequency power output (and gain).
This is known as gain compression.
‰ As input power increases, so does nonlinearity causing greater
gain compression.
‰ A standard measure of Gain compression
p
is “1-dB compression
p
point” power level P1dB, which can be
■ Input referred for receiver, or
■ Output referred for transmitter
108
Amplitude
A
e
Amplitude
A
e
Linear Operation: No Gain Compression
time
time
f1
frequency
Power (d
dBm)
Power (d
dBm)
LNA
or PA
f1
frequency
109
Amplitude
A
e
Amplitude
A
e
Cause of Gain Compression: Clipping
time
time
f1
frequency
Power (d
dBm)
Power (d
dBm)
LNA
or PA
f1
f2
f3
frequency
110
Effect of Nonlinearity
‰ Assume a transfer function, vo = a0 + a1 vi + a2 vi2 + a3 vi3
‰ Let vi = A cos ωt
‰ Using the identities (ω = 2πf):
● cos2 ωt = (1 + cos 2ωt)/2
● cos3 ωt = (3 cos ωt + cos 3ωt)/4
‰ We get,
● vo
=
a0 + a2A2/2 + (a1A + 3a3A3/4) cos ωt
+ ((a2A2/2)) cos 2ωt + ((a3A3/4)) cos 3ωt
111
Gain Compression Analysis
‰ DC term is filtered out.
‰ For small-signal
g input,
p , A is small
● A2 and A3 terms are neglected
● vo = a1A cos ωt, small-signal gain, G0 = a1
‰ Gain at 1-dB compression point, G1dB = G0 – 1
‰ Input referred and output referred 11-dB
dB power:
P1dB(output) – P1dB(input) = G1dB = G0 – 1
112
1 dB
1 dB
Compression
point
P1dB(output))
Outputt power (d
dBm)
1-dB Compression Point
Linear region
(small-signal)
Compression
region
P1dB(input)
Input power (dBm)
113
Testing for Gain Compression
‰ Apply a single-tone input signal:
1. Measure the gain at a power level where DUT is linear.
2. Extrapolate the linear behavior to higher power levels.
3. Increase input power in steps, measure the gain and
compare to
t extrapolated
t
l t d values.
l
4. Test is complete when the gain difference between steps 2
and 3 is 1dB.
‰ Alternative test: After step 2, conduct a binary search for 1-dB
compression point.
point
114
Example: Gain Compression Test
‰ Small-signal gain, G0 = 28dB
‰ Input-referred
p
1-dB compression
p
point p
p
power level,,
P1dB(input) = – 19 dBm
‰ We compute:
■ 1-dB compression point Gain, G1dB = 28 – 1 = 27 dB
■ Output
Output-referred
referred 11-dB
dB compression point power level,
level
P1dB(output)
=
P1dB(input) + G1dB
=
– 19 + 27
=
8 dBm
115
Intermodulation Distortion
‰ Intermodulation distortion is relevant to devices that handle
multiple frequencies.
‰ Consider an input signal with two frequencies ω1 and ω2:
vi = A cos ω1t + B cos ω2t
‰ Nonlinearity in the device function is represented by
vo = a0 + a1 vi + a2 vi2 + a3 vi3
neglecting
l ti higher
hi h order
d terms
t
‰ Therefore, device output is
vo = a0 + a1 (A cos ω1t + B cos ω2t)
DC and fundamental
+ a2 (A cos ω1t + B cos ω2t)2
2nd order terms
+ a3 (A cos ω1t + B cos ω2t)3
3rd order terms
116
Problems to Solve
‰ Derive the following:
vo =
a0 + a1 ((A cos ω1t + B cos ω2t))
+ a2 [ A2 (1+cos ω1t)/2 + AB cos (ω1+ω2)t + AB cos (ω1 – ω2)t
+ B2 (1
(1+cos
cos ω2t)/2 ]
+ a3 (A cos ω1t + B cos ω2t)3
‰ Hint:
Hi t Use
U the
th identity:
id tit
■ cos α cos β = [cos(α + β) + cos(α – β)] / 2
‰ Simplify
Si lif a3 (A cos ω1t + B cos ω2t)3
117
Two-Tone Distortion Products
‰ Order for distortion product mf1 ± nf2 is |m| + |n|
Nunber of distortion p
products
Order Harmonic Intermod.
Frequencies
q
Total
Harmonic
Intrmodulation
2
2
2
4
2f1 , 2f2
f1 + f2 , f2 – f1
3
2
4
6
3f1 , 3f2
2f1 ± f2 , 2f2 ± f1
4
2
6
8
4f1 , 4f2
2f1 ± 2f2 , 2f2 – 2f1 , 3f1 ± f2 , 3f2 ± f1
5
2
8
10
5f1 , 5f2
3f1 ± 2f2 , 3f2 ± 2f1 , 4f1 ± f2 , 4f2 ± f1
6
2
10
12
6f1 , 6f2
3f1 ± 3f2 , 3f2 – 3f1 , 5f1 ± f2 , 5f2 ± f1 ,
4f1 ± 2f2 , 4f2 ± 2f1
7
2
12
14
7f1 , 7f2
4f1 ± 3f2 , 4f2 – 3f1 , 5f1 ± 2f2 , 5f2 ± 2f1 ,
6f1 ± f2 , 6f2 ± f1
N
2
2N – 2
2N
Nf1 , Nf2 . . . . .
118
Problem to Solve
Write Distortion products for two tones 100MHz and 101MHz
Harmonics
Od
Order
I t
Intermodulation
d l ti products
d t (MH
(MHz))
(MHz)
2
200, 202 1, 201
3
300, 3003 99, 102, 301, 302
4
400, 404 2, 199, 203, 401, 402, 403
5
500, 505 98, 103, 299, 304, 501, 503, 504
6
600, 606 3, 198, 204, 399, 400, 405, 601, 603, 604, 605
97 104,
97,
104 298,
298 305,
305 499
499, 506
506, 701
701, 707
707, 703
703,
7
700, 707
704, 705, 706
Intermodulation products close to input tones are
shown in bold.
119
f1 f2
frequency
f2 – f1
DUT
Ampliitude
Ampliitude
Second-Order Intermodulation Distortion
f1 f2 2f1 2f2
frequency
120
Amplitu
ude
Higher-Order Intermodulation Distortion
DUT
Third-order intermodulation
distortion products (IMD3)
2f2 – f1
Amplitud
de
frequency
2f1 – f2
f1 f2
f1 f2
2f1 2f2
3f1 3f2
frequency
121
Problem to Solve
‰ For A = B, i.e., for two input tones of equal magnitudes, show
that:
■ Output amplitude of each fundamental frequency, f1 or f2 , is
9
a1 A + — a3 A3
4
■ Output amplitude of each third-order intermodulation
frequency, 2f1 – f2 or 2f2 – f1 , is
3
— a3 A3
4
122
Third-Order Intercept Point (IP3)
‰ IP3 is the power level of the fundamental for which the output of
each fundamental frequency equals the output of the closest
third-order intermodulation frequency.
‰ IP3 is a figure of merit that quantifies the third-order
intermodulation distortion.
a1 IP3 = 3a3 IP33 / 4
IP3 = [4a1 /(3a3 )]1/2
Outpu
ut
‰ Assuming
g a1 >> 9a3 A2 /4,, IP3 is g
given byy
a1 A
3a3 A3 / 4
IP3
A
123
Test for IP3
‰ Select two test frequencies, f1 and f2, applied in equal
magnitude to the input of DUT.
‰ Increase input power P0 (dBm) until the third-order products are
well above the noise floor.
‰ Measure output power P1 in dBm at any fundamental frequency
and P3 in dBm at a third-order intermodulation frquency.
q
y
‰ Output-referenced IP3:
OIP3
=
P1 + (P1 – P3) / 2
‰ Input-referenced
Input referenced IP3:
IIP3
=
P0 + (P1 – P3) / 2
=
OIP3 – G
Because, Gain for fundamental frequency, G = P1 – P0
124
IP3 Graph
Outputt power (dBm)
OIP3
P1
2f1 – f2 or 2f2 – f1
20 log (3a3 A3 /4)
slope = 3
f1 or f2
20 log a1 A
slope = 1
P3
(P1 – P3)/2
P0
IIP3
Input power = 20 log A dBm
125
Example: IP3 of an RF LNA
‰ Gain of LNA = 20 dB
‰ RF signal
g frequencies:
q
2140.10MHz and 2140.30MHz
‰ Second-order intermodulation distortion: 400MHz; outside
operational band of LNA.
‰ Third-order intermodulation distortion: 2140.50MHz; within the
operational band of LNA.
LNA
‰ Test:
■
■
■
■
■
Input power,
power P0 = – 30 dBm,
dBm for each fundamental frequency
Output power, P1 = – 30 + 20 = – 10 dBm
Measured third-order intermodulation distortion power, P3 = – 84 dBm
OIP3 = – 10 + [( – 10 – ( – 84))] / 2 = + 27 dB
dBm
IIP3 = – 10 + [( – 10 – ( – 84))] / 2 – 20 = + 7 dBm
126
Source Intermodulation Distortion (SIMD)
‰ When test input to a DUT contains multiple tones, the input may
contain intermodulation distortion known as SIMD.
‰ Caused by poor isolation between the two sources and
nonlinearity in the combiner.
‰ SIMD should be at least 30dB below the expected
intermodulation distortion of DUT.
127
Cross Modulation
‰ Cross modulation is the intermodulation distortion caused by
multiple carriers within the same bandwidth.
‰ Examples:
■ In cable TV, same amplifier is used for multiple channels.
■ Orthogonal frequency division multiplexing (OFDM) used in WiMAX or
WLAN use multiple carriers within the bandwidth of the same amplifier.
‰ Measurement:
■ Turn on all tones/carriers except one
■ Measure the power at the frequency that was not turned on
‰ B. Ko, et al., “A Nightmare for CDMA RF Receiver: The Cross
Modulation,” Proc. 1st IEEE Asia Pacific Conf. on ASICs, Aug.
1999, pp. 400-402.
128
RFIC Design and Testing for Wireless
Communications
A Full-Day Tutorial at VLSI Design & Test Symposium
July 23, 2008
Lecture 6: Testing for Noise
Vishwani D. Agrawal
Foster Dai
Auburn University, Dept. of ECE, Auburn, AL 36849, USA
129
What is Noise?
‰ Noise in an RF system is unwanted random fluctuations in a
desired signal.
‰ Noise is a natural phenomenon and is always present in the
environment.
‰ Effects of noise:
■ Interferes with detection of signal
g ((hides the signal).
g )
■ Causes errors in information transmission by changing
signal.
■ Sometimes noise might imitate a signal falsely.
‰ All communications system design and operation must account
for noise.
130
Describing Noise
‰ Consider noise as a random voltage or current function, x(t),
over interval – T/2 < t < T/2.
‰ Fourier transform of x(t) is XT(f).
‰ Power spectral density (PSD) of noise is power across 1Ω
Sx(f)
=
lim [ E{ |XT(f)|2 } / (2T) ]
volts2/Hz
T→
T→∞
This is also expressed in dBm/Hz.
131
Thermal Noise
‰ Thermal (Johnson) noise: Caused by random movement of
electrons due to thermal energy that is proportional to
t
temperature.
t
‰ Called white noise due to uniform PSD over all frequencies.
‰ Mean square open circuit noise voltage across R Ω resistor
[Nyquist, 1928]:
v2
=
4hfBR / [exp(hf/kT) – 1]
■ Where
● Plank’s constant h = 6.626 × 1034 J-sec
● Frequency and bandwidth in hertz = f, B
● Boltzmann’s
B lt
’ constant
t t k = 1.38
1 38 × 10 – 23 J/K
● Absolute temperature in Kelvin = T
132
Problem to Solve
‰ Given that for microwave frequencies, hf << kT, derive the
following Rayleigh-Jeans approximation:
v2
=
4kTBR
‰ Show that at room temperature (T = 290K), thermal noise power
supplied by resistor R to a matched load is ktB or – 174 dBm/Hz.
Noisy
resistor
R
R
Matched
load
v = (4kTBR)1/2
133
Other Noise Types
‰ Shot noise [Schottky, 1928]: Broadband noise due to random behavior of
charge carriers in semiconductor devices.
‰ Flicker (1/f) noise: Low-frequency noise in semiconductor devices, perhaps
due to material defects; power spectrum falls off as 1/f. Can be significant at
audio frequencies.
q
‰ Quantization noise: Caused by conversion of continuous valued analog
signal to discrete-valued digital signal; minimized by using more digital bits.
‰ Quantum noise: Broadband noise caused by the quantized nature of charge
carriers; significant at very low temperatures (~0K) or very high bandwidth
( > 1015 Hz).
Hz)
‰ Plasma noise: Caused by random motion of charges in ionized medium,
possibly
poss
b y resulting
esu t g from
o spa
sparking
g in eelectrical
ect ca co
contacts;
tacts; ge
generally,
e a y, not
ot a
concern.
134
Measuring Noise
‰ Expressed as noise power density in the units of dBm/Hz.
‰ Noise sources:
■ Resistor at constant temperature, noise power = kTB W/Hz.
■ Avalanche diode
‰ Noise temperature:
■ Tn = (Available noise power in watts)/(kB) kelvins
‰ Excess noise ratio (ENR) is the difference in the noise output
between hot ((on)) and cold (off)
( ) states,, normalized to reference
thermal noise at room temperature (290K):
■ ENR = [k( Th – Tc )B]/(kT0B) = ( Th / T0) – 1
■ Where noise output in cold state is takes same as reference.
135
■ 10 log ENR ~ 15 to 20 dB
Signal-to-Noise Ratio (SNR)
‰ SNR is the ratio of signal power to noise power.
Si/Ni
G
Po
ower (dBm
m)
Input signal: low peak power,
good SNR
G
So/No
Output
Ou
pu signal:
s g a high
g peak
pea po
power,
e,
poor SNR
So/No
Si/Ni
Noise floor
Frequency (Hz)
136
Noise Factor and Noise Figure
‰ Noise factor (F) is the ratio of input SNR to output SNR:
■ F = (Si /Ni) / (So /No)
= No / ( GNi )
when Si = 1W and G = gain of DUT
= No /( kT0 BG)
when Ni = kT0 B for input noise source
■ F≥1
‰ Noise figure (NF) is noise factor expressed in dB:
■ NF = 10 log F dB
■ 0 ≤ NF ≤ ∞
137
Cascaded System Noise Factor
‰ Friis equation [Proc. IRE, July 1944, pp. 419 – 422]:
Fsys
=
F1
Gain = G1
Noise factor
= F1
F2 – 1
+ ———
G1
+
Gain = G2
Noise factor
= F2
F3 – 1
Fn – 1
——— + · · · · + ———————
G1 G2
G1 G2 · · · Gn – 1
Gain = G3
Noise factor
= F3
Gain = Gn
Noise factor
= Fn
138
Measuring Noise Figure: Cold Noise Method
‰ Example: SOC receiver with large gain so noise output is
measurable; noise power should be above noise floor of
measuring equipment.
‰ Gain G is known or previously measured.
‰ Noise factor, F = No / (kT0BG), where
● No is measured output
p noise p
power ((noise floor))
● B is measurement bandwidth
● At 290K, kT0 = – 174 dBm/Hz
‰ Noise figure, NF = 10 log F
(dB)) – ( – 174 d
dBm/Hz)
/ ) – B(dB)
(d ) – G(d
G(dB))
= No (d
‰ This measurement is also done using S-parameters.
139
Y – Factor
‰ Y – factor is the ratio of output noise in hot (power on) state to
that in cold (power off) state.
‰Y
=
Nh / Nc
=
Nh / N0
‰ Y is a simple ratio.
‰ Consider,
C id Nh = kThBG and
d Nc = kT0BG
‰ Then Nh – Nc = kBG( Th – T0 ) or kBG = ( Nh – Nc ) / ( Th – T0 )
‰ Noise factor, F = Nh /( kT0 BG) = ( Nh / T0 ) [ 1 / (kBG) ]
= ( Nh / T0 ) ( Th – T0 ) / (Nh – Nc )
= ENR / (Y – 1)
140
Measuring Noise Factor: Y – Factor Method
‰ Noise source provides hot and cold noise power levels and is
characterized by ENR (excess noise ratio).
‰ Tester measures noise power, is characterized by its noise
factor F2 and Y-factor Y2.
‰ Device under test (DUT) has gain G1 and noise factor F1.
‰ Two-step measurement:
■ Calibration: Connect noise source to tester, measure output
power for hot and cold noise inputs,
p
p
compute
p Y2 and F2.
■ Measurement: Connect noise source to DUT and tester
cascade, measure output power for hot and cold noise
i t compute
inputs,
t compute
t Y12, F12 and
d G1.
141
■ Use Friis equation to obtain F1.
Calibration
Noise
source
ENR
Tester
(power meter)
F2, Y2
‰ Y2 = Nh2 / Nc22, where
● Nh2 = measured power for hot source
● Nc2 = measured p
power for cold source
‰ F2 = ENR / (Y2 – 1)
142
Cascaded System Measurement
Noise
source
ENR
Tester
(power meter)
F2, Y2
DUT
F1, Y1, G1
F12, Y12
‰ Y12 = Nh12 / Nc12, where
● Nh12 = measured power for hot source
● Nc12 = measured power for cold source
‰ F12 = ENR / ( Y12 – 1 )
‰ G1 = ( Nh12 – Nc12 ) / ( Nh2 – Nc2 )
143
Problem to Solve
‰ Show that from noise measurements on a cascaded system, the
noise factor of DUT is given by
F2 – 1
F1 = F12 – ———
G1
144
Phase Noise
‰ Phase noise is due to small random variations in the phase of
an RF signal. In time domain, phase noise is referred to as jitter.
‰ Understanding phase:
δ amplitude
noise
t
V sin ωt
ω
Frequency (rad/s)
φ
phase
noise
t
[V + δ(t)] sin [ωt + φ(t)]
ω
Frequency (rad/s)
145
Effects of Phase Noise
‰ Similar to phase modulation by a random signal.
‰ Two types:
yp
■ Long term phase variation is called frequency drift.
■ Short term phase variation is phase noise.
‰ Definition: Phase noise is the Fourier spectrum (power spectral
density) of a sinusoidal carrier signal with respect to the carrier
power.
( ) = Pn /Pc ((as ratio))
L(f)
= Pn in dBm/Hz – Pc in dBm (as dBc)
■ Pn is RMS noise power in 11-Hz
Hz bandwidth at frequency f
■ Pc is RMS power of the carrier
146
Phase Noise Analysis
[V + δ(t)] sin [ωt + φ(t)] = [V + δ(t)] [sin ωt cos φ(t) + cos ωt sin φ(t)]
≈ [V + δ(t)] sin ωt + [V + δ(t)] φ(t) cos ωt
In-phase carrier frequency with amplitude noise
White noise δ(t) corresponds to noise floor
Quadrature-phase carrier frequency with amplitude and phase noise
Short-term phase noise corresponds to phase noise spectrum
Phase spectrum, L(f) = Sφ(f)/2
Where Sφ(f) is power spectrum of φ(t)
147
Phase Noise Measurement
Powerr (dBm)
‰ Phase noise is measured by low noise receiver (amplifier) and
spectrum analyzer:
■ Receiver must have a lower noise floor than the signal noise
floor.
■ Local
L l oscillator
ill t iin th
the receiver
i mustt h
have llower phase
h
noise
i
than that of the signal.
Signal spectrum
Receiver phase noise
Receiver noise floor
Frequency (Hz)
148
Phase Noise Measurement
Pure tone
Input
(carrier)
DUT
Hz
offset
Spectrum analyzer power measurement
Power (dBm) over resolution bandwith (RBW)
carrier
149
Phase Noise Measurement Example
‰ Spectrum analyzer data:
■ RBW = 100Hz
■ Frequency offset = 2kHz
■ Pcarrier = – 5.30 dBm
■ Poffset = – 73.16
73 16 dBm
dB
‰ Phase noise, L(f) = Poffset – Pcarrier – 10 log RBW
= – 73.16 – ( – 5.30) – 10 log 100
= – 87.86 dBc/Hz
‰ Phase noise is specified as “ – 87.86 dBc/Hz at 2kHz from the
carrier.”
150
Problem to Solve
‰ Consider the following spectrum analyzer data:
■ RBW = 10Hz
■ Frequency offset = 2kHz
■ Pcarrier = – 3.31 dBm
■ Poffset = – 81.17
81 17 dBm
dB
‰ Determine phase noise in dBc/Hz at 2kHz from the carrier.
151
RFIC Design and Testing for Wireless
Communications
A Full-Day Tutorial at VLSI Design & Test Symposium
July 23, 2008
Lecture 7: ATE and SOC Testing
Vishwani D. Agrawal
Foster Dai
Auburn University, Dept. of ECE, Auburn, AL 36849, USA
152
Automatic Test Equipment (ATE)
‰ ATE provides test facility for:
■ Digital and memory devices
■ Analog devices (analog instrumentation)
■ RF devices (AWG – arbitrary waveform generators, LNA,
noise
i source, RF sources, filt
filters, PMU – power
measurement units, Spectrum analyzer)
■ Test fixtures, load
load-boards,
boards, handlers
‰ Cost of ATE: $500,000 to $2M, or higher
‰ Testing
T ti costt off chip
hi ~ 3 – 5 cents/second
t /
d
153
Variables in Cost of Testing
‰ Shifts per day:
3
‰ Hours p
per shift:
8
‰ Yield:
80%
‰ Utilization:
60% (significant effort for calibration)
‰ Depreciation:
5 years
‰ Cost of ATE:
$1M
‰ Cost of handler:
$250,000
‰ Test time:
1.5 seconds
‰ Handler index time: 1 second
154
Problem to Solve
‰ Find the testing cost for a good device shipped using the data
given in the previous slide.
155
Testing Cost
‰ Tester time per year:
■ T = 365 × 24 × 3600 × 0.6
= 18,921,600 s
‰ Number of devices tested per year:
■ NT = T/(1.5 + 1.0)
= 7,568,640
‰ Number of good devices produced per year:
■N
= NT × Yield = 7,568,640 × 0.8 = 6,054,912
‰ Testing cost per year:
)
■C
= ((1,000,000 + 250,000)/5
= 250,000 dollars
‰ Testing cost per device shipped:
■ Cost = C/N
= 4.13 cents
156
Reducing Test Cost
‰ Ping-pong testing: Use the same ATE with multiple handlers.
‰ Multisite testing:
g Test multiple
p chips
p together,
g
, typically,
yp
y, 4,, 16,, . . .
‰ Built-in self-test (BIST): Applicable to SOC and SIP devices.
‰ Low-cost
Low cost testers.
testers
157
BIST for a SOC ZIF Transceiver
0°
0
LNA
Phase
Splitter
LO
Duplexerr
90°
ADC
TA
DAC
0°
Phase
Splitter
PA
LO
90°
SOC
RF
Digital Signa
al Process
sor (DSP)
ADC
DAC
BASEBAND
158
ZIF SOC BIST
‰ Test implemented at baseband.
‰ Loopback between A/D and D/A converters.
‰ DSP implemented with digital BIST.
‰ Test amplifier (TA) implemented on chip; is disabled during normal
operation.
i
‰ A test procedure:
■ Test DSP using digital BIST.
BIST
■ Apply RF BIST:
● Pseudorandom bit sequence generated by DSP
● Upconverted
U
t db
by transmitter
t
itt chain
h i and
d applied
li d tto receiver
i th
through
h TA
● Down converted signal compared to input bit sequence by DSP to
analyze bit error rate (BER)
● BER correlated to relevant characteristics of SOC components
‰ Advantage: Low tester cost. Disadvantage: Poor diagnosis.
159
Low-Cost Tester for Wideband RF Parameters
I
Arbitrary waveform
generator (AWG)
Q
RF generator
modulation source
RF to
t
DUT
DUT
DUT RF
output
Tester
Computer
Digital
pin or
digitizer
RF detector
and buffer
amplifier
Filter
160
References
‰ SOC BIST
■ J. Dabrowski, “BiST Model for IC RF-Transceiver Front-End,” Proc. 18th
IEEE International
I t
ti l Symp.
S
on Defect
D f t and
dF
Fault
lt Tolerance
T l
in
i VLSI S
Systems,
t
2003.
■ D. Lupea, et al., “RF-BIST: Loopback Spectral Signature Analysis,” Proc.
Design, Automation and Test in Europe Conf., 2003.
‰ BIST for power amplifier
■ F
F. Obaldia,
Ob ldi ett al.,
l “O
“On-Chip
Chi Test
T t Mechanism
M h i for
f Transceiver
T
i Power
P
Amplifier and Oscillator Frequency,” US Patent No. 20040148121A1,
2004.
‰ Low-cost testing
■ F. Goh, et al., “Innovative Technique for Testing Wide Bandwidth
F
Frequency
Response,”
R
” Wireless
Wi l
Broadband
B db d F
Forum, Cambridge,
C b id UK,
UK
2004.
161
RFIC Design and Testing for Wireless
Communications
A Full-Day Tutorial at VLSI Design & Test Symposium
July 23, 2008
Lecture 8: RF BIST
Vishwani D. Agrawal
Foster Dai
Auburn University, Dept. of ECE, Auburn, AL 36849, USA
162
Purpose
‰ Develop Built-In Self-Test (BIST) approach using direct digital
synthesizer (DDS) for functionality testing of analog circuitry in
mixed-signal systems
‰ Provides BIST-based measurement of
■ Amplifier
A lifi linearity
li
it (IP3)
■ Gain and frequency response
‰ Implemented in hardware
■ IP3, gain, and freq. response measured
Analog and mixed signal testing, FDAI, 2008
163
Outline
‰ Overview of direct digital synthesizers (DDS)
‰ 3rd order inter-modulation p
product ((IP3))
‰ BIST architecture
■ Test pattern generator
■ Output response analyzer
‰ Experimental results
■ Implementation in hardware
■ IP3 Measurements
Analog and mixed signal testing, FDAI, 2008
164
Direct Digital Synthesis (DDS)
‰ DDS ⇒ generating deterministic communication carrier/reference
signals in discrete time using digital hardware
■ converted
t d iinto
t analog
l signals
i l using
i a DAC
‰ Advantages
■ Capable of generating a variety of waveforms
■ High precision ⇒ sub Hz
■ Digital circuitry
● Small
S ll size
i ⇒ fraction
f ti off analog
l synthesizer
th i size
i
● Low cost
● Easy to implementation
Analog and mixed signal testing, FDAI, 2008
165
Typical DDS Architecture
Frequency
Word
N
Fr
clk
Digital Circuits
Sine
to-A
R D-toAccum W
Lookup
Conv.
-ulator
Table
1/ffout
1/
1/ffclk
1/
1/ffout
1/
1/ffclk
1/
Low
Pass
Filter
1/ffout
1/
fclkFr
fout= N
2
Sine
Wave
1/ffout
1/
1/ffclk
1/
Analog and mixed signal testing, FDAI, 2008
166
Intermodulation
f1 f2
7 8 freq
f2- f1
f1 f2
2f1- f2
2f2- f1
f1+f2
2f1 2f2
3f1
3f2
0 2 4 6 8 10 12 14 16 18 20 22 24 freq
IM3
‰ Two signals with different frequencies are applied to a
nonlinear system
■ Output exhibits components that are not harmonics of
input fundamental frequencies
‰ Third-order intermodulation (IM3) is critical
■ Very close to fundamental frequencies
Analog and mixed signal testing, FDAI, 2008
167
Mathematical Foundation
‰ Input 2-tone:
x(t)=A1cos ω1t + A2 cos ω2t
‰ Output of non-linear device:
y(t)=α0+α1x(t)+α2x2(t)+α3x3(t)+…
‰ Substituting x(t) into y(t):
y(t) = ½α2(A12+A22)
+ [α1A1+¾α3A1(A12+2A22)]cosω1t + [α1A2+¾α3A2(2A12+A22)]cosω2t
+ ½α2(A12cos2ω1t+A22cos2ω2t )
+ α2A1A2[cos(ω1+ω2)t+cos(ω1-ω2)t]
+ ¼α3[A13cos3ω1t+A22cos3ω2t]
+ ¾α3{A12A2[cos(2ω1+ω2)t+cos(2ω1-ω2)t]
+A1A22[[cos(2ω
( 2+ω1))t+cos(2ω
( 2-ω1))t]}
]}
α1A
ΔP
¾ α3A2
freq
2ω1-ω2 ω1 ω2 2ω2-ω1
Analog and mixed signal testing, FDAI, 2008
168
3rd order Intercept Point (IP3)
• IP3 is theoretical input power point where 3rd-order distortion
and fundamental output lines intercept
Outtput Pow
wer
(OIP3)
•
ΔP[dB]
IIP32[dBm]=
dBm]=
+Pin [dBm]
dBm]
Practical measurement
with spectrum analyzer
IM3
IP3
20log(¾
20log(¾α
g( α3A3)
20log(α
20log(
α1A)
fundamental
α1A
ΔP
¾ α3A2
ΔP
freq
ΔP/2
Input Power
(IIP3)
2ω1-ω2 ω1 ω2 2ω2-ω1
Analog and mixed signal testing, FDAI, 2008
169
2-tone Test Pattern Generator
• Two DDS outputs are superimposed using adder to
generate 2
2--tone waveform used for IP3 measurement
• Fr1 and Fr2 control frequencies of 22-tone waveform
Fr1 Accum
-ulator
#1
Sine
Lookup
p
Table 1
Σ
Fr2 Accum
-ulator
#2
Sine
Lookup
Table 2
D-toto-A
Conv
Conv.
Analog and mixed signal testing, FDAI, 2008
Low
Pass
Filter
2-tone
Waveform
170
Actual 2-tone IP3 Measurement
•
O t t off DAC and
Outputs
d DUT taken
t k with
ith scope ffrom our experimental
i
t l
hardware implementation
•
Typical ΔP measurement requires expensive, external spectrum
analyzer
– For BIST we need an efficient output response analyzer
DAC output x(t
x(t):
ΔP
DUT output y(t
y(t):
171
Analog and mixed signal testing, FDAI, 2008
171
Output Response Analyzer
Multiplier/accumulator-based ORA
‰ Multiply the output response by a frequency
‰ Accumulate the multiplication result
‰ Average
g byy # of clock cycles
y
of accumulation
■ Gives DC value proportional to power of signal at that
frequency
‰ Advantages
■ Easy to implement
■ Low area overhead
■ Exact frequency control
■ More efficient than FFT
y(tt)
y(
multiplier
X
fx
Analog and mixed signal testing, FDAI, 2008
Σ
DC
accumulator
172
DC1 Accumulator
•
y(tt)
y(tt) x f2 ⇒ DC1≈ ½A22α1 y(
y(
•
Ripple in slope due to low
frequency components
Σ
X
DC1
ΔP
– Longer accumulation f2
reduces effect of ripple
α1A
¾ α3A2
freq
Simulation Results
Millions
f2 2f2-f1
Actual Hardware Results
140
120
100
80
slope = DC1
≈ ½A22α1
60
40
20
0
1
21
41
Analog and mixed signal testing, FDAI, 2008
61
81 101 121 141 161 181 201 221 241 261
Clock cycles (x50)
173
DC2 Accumulator
•
y(tt) x f2 ⇒ DC2≈ 3/8A12A22α3
y(
•
Ripple is bigger for DC2
y(tt)
y(
DC2
Σ
X
– Test controller needed to
2f2-f1
obtain DC2 at integral
multiple
p of 2f2-f1
ΔP
Simulation Results
¾ α3A2
f2 2f2-f1
Millions
slope = DC2
= 3/8A12A22α3
α1A
freq
Actual Hardware Results
20
15
10
5
0
1
Analog and mixed signal testing, FDAI, 2008
21
41
61
81 101 121 141 161 181 201 221 241 261
-5
Clock cycles (x50)
174
BIST-based ΔP Measruement
•
DC1 & DC2 same proportionality to power at f2 & 2f
2f2-f1
•
Only need DC1 & DC2 from accumulators to calculate
ΔP = 20 log (DC1) – 20 log (DC2)
Actual Hardware Results
Simulation Results
70
60
50
40
30
20
10
0
1
21
41
61
81 101 121 141 161 181 201 221 241 261
Clock cycles (x50)
Analog and mixed signal testing, FDAI, 2008
175
BIST Architecture
•
BIST--based IP3 measurement
BIST
– Reduce circuit by repeating test sequence for DC2
•
BIST--based Gain & Frequency Response is subset
BIST
x(tt()=
x(
)=cos
x(tt)=
x(
)=cos
cos((f1)+
)+cos
cos(
f2),cos((f2)
f1
Accum
LUT1
Test Pattern Generator
f2
2f2-f1
Σ
DAC
DUT
ADC
y(tt)
y(
Output Response
Analyzer
Accum
LUT2
X
Accum
Accum
LUT3
X
Accum
Analog and mixed signal testing, FDAI, 2008
DC1
DC2 Gain
Freq
Resp
DC2
176
Experimental Implementation of BIST
‰ TPG, ORA, test controller, & PC interface circuits
■ Three 8-bit DDSs and two 17-bit ORA accumulators
■ Implementation in Verilog
■ Synthesized into Xilinx Spartan 2S50 FPGA
‰ Amplifier device under test implemented in FPAA
‰ DAC-ADC
DAC ADC PCB
1600
1400
PC
FPGA
TPG/ORA
1200
Total in FPGA
Double ORA
Single
g ORA
1000
800
600
FPAA
DUT
DAC &
ADC
400
200
0
Slices
Analog and mixed signal testing, FDAI, 2008
LUTs
FFs
177
Hardware Results
BIST measures ΔP ≈ 14
30
ΔP≈14
255
20
15
10
5
1
201
401
601
801 1001 1201
Clock Cycles (x100)
ΔP distribution for 1000
BIST measurements
mean=13 97 dB
mean=13.97
dB, σ =0.082
=0 082
2
Percentage(%)
D eltta_P (dB
B)
Spectrum analyzer
1.5
1
0.5
0
13.68 13.77 13.87 13.96 14.05 14.14 14.24
Analog and mixed signal testing, FDAI, 2008
Measured Delta_P(dB)
178
More Hardware Results
Spectrum analyzer
BIST
S measures ΔP ≈ 22
ΔP≈22
80
60
40
20
0
1
501
1001
1501
2001
Clock Cycles (x50)
ΔP distribution for 1000
BIST measurements
mean=21.7
21 7 dB
dB, σ =2.2
22
Analog and mixed signal testing, FDAI, 2008
2501
2
Percenta
age(%)
D eltta P (dB))
100
1.5
1
0.5
0
16.30
18.94
21.58
24.23
26.87
Measured Delta_P (dB)
29.51
179
BIST IP3 Measurement Results
•
Good agreement with actual values for ΔP < 30dB
•
For measured ΔP > 30dB, the actual ΔP is greater
BIST measured delta P (dB)
– Good threshold since ΔP < 30dB is of most interest
50
45
40
35
30
25
20
15
10
5
0
0
5
10
15
20
25
30
35
40
45
50
actual delta P (dB)
Analog and mixed signal testing, FDAI, 2008
180
Conclusion
‰ BIST-based approach for analog circuit functional testing
■ DDS-based TPG
■ Multiplier/accumulator-based
M lti li /
l t b d ORA
‰ Good for manufacturing or in-system circuit characterization
and on-chip compensation
■ Amplifier linearity (IP3)
■ Gain and frequency response
‰ Measurements with hardware implementation
■ Accurately
A
t l measures IP3 ≤ 30dB
■ Measurements of IP3 > 30dB imply higher values
Analog and mixed signal testing, FDAI, 2008
181