Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-1
LECTURE 290 – LOW POWER AND LOW NOISE OP AMPS
LECTURE ORGANIZATION
Outline
• Review of subthreshold operation
• Low power op amps
• Review of MOSFET noise modeling and analysis
• Low noise op amps
• Summary
CMOS Analog Circuit Design, 2nd Edition Reference
Pages 393-414
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-2
REVIEW OF SUBTHRESHOLD OPERATION
Subthreshold Operation
Most micropower op amps use transistors in the subthreshold region.
Subthreshold characteristics:
iD
;;;;
Square Law
The model that has
been developed for
the large signal subthreshold operation
is:
1μA
100nA
iD
Strong Inversion
vGS =VT
Transition
Exponential
100nA
vGS ≤VT
Weak Inversion
0
0
VT
vGS
0
0
1V
vDS
2V Fig. 7.4-0A
vDS
W
vGS-V T iD = It L exp nVt 1+VA where vDS > 0 and VDS(sat) = VON = VGS -VT = 2nVt
Small-signal model:
vDS ID qID ID Cox
diD |
W It
vGS-V T gm = dvGS Q = It L nVt exp nVt 1+VA = nVt = nkT = V t Cox+Cjs
diD | ID
gds = dvDS Q V A
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-3
Boundary Between Subthreshold and Strong Inversion
It is useful to develop a means of estimating when a MOSFET is making the transition
between subthreshold and strong inversion to know when to use the proper model.
The relationship developed is based on the following concept:
iD
We will solve for the value of vGS
iD = K‘W(vGS-VT)2
(actually vGS -VT) and find the drain
2L
current where these two values are
v -V
IW
equal [vGS(tran.) -VT)].
iD = t exp( GS T )
L
nVt
iD(tran.)
The large signal expressions for each
region are:
vGS
VT vGS(tran.)
070507-01
Subthreshold
iD It(W/L)
W
vGS-V T
iD It L exp nVt vGS-V T = nVt lnIt(W/L) nVt 1- iD if
0.5 < iD/(ItW/L).
Strong inversionK'W
iD = 2L vGS-V T2
vGS-V T =
CMOS Analog Circuit Design
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
2iD
K'(W/L)
© P.E. Allen - 2010
Page 290-4
Boundary Between Subthreshold and Strong Inversion - Continued
Equating the two large signal expressions gives,
2iD
2iD
It(W/L)
It(W/L)2
2
2
=
n
V
1-
nVt 1- iD =
t
iD K'(W/L)
K'(W/L)
Expanding gives,
I 2(W/L)2 2I (W/L)
2iD
t
t
2
2
2V 2 =
n Vt -
+1
n
if (ItW/L)/iD < 0.5
t
iD
K'(W/L)
i D2
Therefore we get,
K'W
iD(tran.) = 2L n2V t2
For example, if K’ = 120μA/V2, W/L = 100, and n = 2, then at room temperature the
value of drain current at the transition between subthreshold and strong inversion is
120μA/V2100
iD(tran.) =
4·(0.026)2 = 16.22μA
2
One will find for UDSM technology, that weak inversion or subthreshold operation can
occur at large currents for large values of W/L.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-5
LOW POWER OP AMPS
Two-Stage, Miller Op Amp Operating in Weak Inversion
VDD
M6
M3
vin
+
M1
+
VBias
-
M4
Cc
vout
CL
M2
M7
M5
VSS
Fig.7.4-1
Low frequency response:
1
1
ro2ro4 ro6ro7 )
Avo = gm2gm6 ro2+ro4 ro6+ro7 = n2n6(kT/q)2(2+4)(6+7) (No longer ID
GB and SR:
ID1
ID5
ID1
kT
GB = (n1kT/q)C
and
SR = C = 2 C = 2GB n1 q = 2GBn1V t
CMOS Analog Circuit Design
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
© P.E. Allen - 2010
Page 290-6
Example 290-1 Gain and GB Calculations for Subthreshold Op Amp.
Calculate the gain, GB, and SR of the op amp shown above. The currents are ID5 =
200 nA and ID7 = 500 nA. The device lengths are 1 μm. Values for n are 1.5 and 2.5 for
p-channel and n-channel transistors respectively. The compensation capacitor is 5 pF.
The channel length modulation parameters are N = 0.06V-1 and P = 0.08V-1. Assume
that the temperature is 27 °C. If V DD = 1.5V and V SS = -1.5V, what is the power
dissipation of this op amp?
Solution
The low-frequency small-signal gain is,
1
Av = (1.5)(2.5)(0.026)2(0.06+0.08)(0.06+0.08) = 20,126 V/V
The gain bandwidth is
100x10-9
GB = 2.5(0.026)(5x10-12) = 307,690 rps 49.0 kHz
The slew rate is
SR = (2)(307690)(2.5)(0.026) = 0.04 V/μs
The power dissipation is,
Pdiss = 3(0.7μA) =2.1μW
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-7
Push-Pull Output Op Amp in Weak Inversion
First stage gain is,
gm2 ID2n4V t ID2n4
Avo = gm4 = ID4n2V t = ID4n2 1
Total gain is,
M8
gm1(S6/S4)
(S6/S4)
Avo = (gds6+gds7) = (6+7)n1V t
At room temperature (Vt = 0.0259V) and
for typical device lengths, gains of 60dB
can be obtained.
M9
The GB is,
gm1 S6 gm1b
GB = C S4 = C
VDD
M3
M4
M6
vi2
M1
M2
vou
+
VBias
-
Cc
M5
M7
VSS
Fig. 7.4-2
where b is the current ratio between M4:M6 and M3:M8.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-8
Increasing the Gain of the Previous Op Amp
1.) Can reduce the currents in M3
and M4 and introduce gain in the
M8
M3
current mirrors.
2.) Use a cascode output stage
(can’t use self-biased cascode,
vi2
currents are too low).
M1
VDD
M4
M6
VT+2VON
M13
M2
+
vi1
M14
M10
vout
Cc
M5
I5
+ M11
M12 M15
gm1+gm2
+
VT+2VON
Av =
Rout
2
VBias
M9
M7
gm1
= gds6gds10 gds7gds11
Fig. 7.4-3A
VSS
gm10 + gm11
I5
I 2nnV t
1
5 = I 2 2 I 2 2 = 2I7 nnV t2(nnn2+npp2)
7 n
7 p
I7 + I7
nnV t
npV t
Can easily achieve gains greater than 80dB with power dissipation of less than 1μW.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-9
Increasing the Output Current for Weak Inversion Operation
A significant disadvantage of the weak inversion is that very small currents are available
to drive output capacitance so the slew rate becomes very small.
Dynamically biased differential amplifier input stage:
Note that the sinking current for M1 and M2 is
Isink = I5 + A(i2-i1) + A(i1-i2) where (i2-i1) and (i1-i2) are only positive or zero.
If vi1>vi2, then i2>i1 and the sinking current is increased by A(i2-i1).
If vi2>vi1, then i1>i2 and the sinking current is increased by A(i1-i2).
CMOS Analog Circuit Design
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
© P.E. Allen - 2010
Page 290-10
Dynamically Biased Differential Amplifier - Continued
How much output current is available from this circuit if there is no current gain from the
input to output stage?
Assume transistors M18 through M21 are equal to M3 and M4 and that transistors M22
through M27 are all equal.
W
W
W 28
W 29
26
27
Let
L28 = A L26 and L29 = A L27 The output current available can be found by assuming that vin = vi1-vi2 > 0.
i1 + i2 = I5 + A(i2-i1)
The ratio of i2 to i1 can be expressed as
v i2
in =
exp
i1
nVt
If the output current is iOUT = b(i2-i1) then combining the above two equations gives,
v in bI5expnVt-1
vin
iOUT =
i
=
when
A
=
2.16
and
v OUT
nVt = 1
in (1+A)-(A-1)expnVt
where b corresponds to any current gain through current mirrors (M6-M4 and M8-M3).
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-11
Overdrive of the Dynamically Biased Differential Amplifier
2
The enhanced output current is
accomplished by the use of positive
feedback (M28-M2-M19-M28).
The loop gain is,
A=2
g
g
gm19
m28 m19
LG = gm4 gm26 = A gm4 = A
Note that as the output current
increases, the transistors leave the weak IOUT 1
inversion region and the above analysis I5
is no longer valid.
A = 1.5
A=1
A = 0.3
A=0
0
0
1
vIN nVt
CMOS Analog Circuit Design
2
Fig. 7.4-5
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-12
Increasing the Output Current for Strong Inversion Operation
An interesting technique is to bias the output transistor of a current mirror in the active
region and then during large overdrive cause the output transistor to become saturated
causing a significant current gain.
Illustration:
i1
i2
M2 +
Vds2
+
VGS
-
M1
Current
530µA
VGS
i2 for W2/L2 = 5.3(W1/L1)
i2 for W2/L2 = W1/L1
VGS
100µA
0.1Vds2(sat)
Volts
Vds1(sat)=Vds2(sat)
070507-02
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-13
Example 290-2 Current Mirror with M2 operating in the Active Region
Assume that M2 has a voltage across the drain-source of 0.1Vds(sat). Design the
W 2/L2 ratio so that I1 = I2 = 100μA if W1/L1 = 10. Find the value of I2 if M2 is
saturated.
Solution
Using the value of KN’ = 120μA/V2, we find that the saturation voltage of M2 is
2I1
200
KN’ (W 2/L2) = 120·10 = 0.408V
Now using the active equation of M2, we set I2 = 100μA and solve for W2/L2.
V ds1(sat) =
100μA = KN’(W 2/L2)[V ds1(sat)·Vds2 - 0.5Vds22]
= 120μA/V2 (W 2/L2)[0.408·0.0408 - 0.5·0.04082]V2 = 1.898x106(W 2/L2)
Thus,
W2
L2 = 52.7 53
Now if M2 should become saturated, the value of the output current of the mirror with
100μA input would be 530μA or a boosting of 5.3 times I1.
100 =1.898(W2/L2)
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-14
Implementation of the Current Mirror Boosting Concept
VDD
M8
M17
M10
M7
M9
M18
M21
M13
i1
vi1
i2
M1 M2
M29
ki1
vo1
i1
M30
M27
i2
M14
M22
vi2
M3 M4
M28
ki2
i1
i2
vo2
ki1
ki2
M25
+
M23 VBias
M15
M5
M26
i2
i1
M11
M24
M16
M20
M19
M12
-
M6
VSS
Fig.7.4-7
k = overdrive factor of the current mirror
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-15
A Better Way to Achieve the Current Mirror Boosting
It was found that when the current mirror boosting idea illustrated on the previous slide
was used that when the current increased through the cascode device (M16) that V GS16
increased limiting the increase of VDS12. This can be overcome by the following circuit.
VDD
iin+IB
iin
IB
kiin
M3
50/1
M5 M4
1/1
1/1
M1
M2
1/1
210/1
Fig. 7.4-7A
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-16
REVIEW OF MOSFET NOISE MODELING AND ANALYSIS
Transistor Noise Sources (Low-Frequency)
Drain current model:
D
D
M1
M1
G
M1 is
noisy S
2 8kTgm (KF)ID
in = 3 +
fCoxL2 2
in1
G
M1 is
noiseless S
or
2
Fig. 7.5-0A
8kTgm(1+)
in = 3
(KF)ID
if vBS 0
+
fCoxL2 gmbs
Recall that = gm
Gate voltage model assuming common source operation:
2
i N 8kT
KF
2
en = 2 = 3gm+2fCoxWLK’
or
gm
KF
2 8kT
en = 3gm(1+)+2fCoxWLK’ if vBS 0
CMOS Analog Circuit Design
D
D
2
en1
M1
G
G
M1 is
noisy S
M1
*
M1 is
noiseless S
Fig. 7.5-0C
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-17
Minimization of Noise in Op Amps
1.) Maximize the signal gain as close to the input as possible. (As a consequence, only
the input stage will contribute to the noise of the op amp.)
2.) To minimize the 1/f noise:
a.) Use PMOS input transistors with appropriately selected dc currents and W and L
values.
b.) Use lateral BJTs to eliminate the 1/f noise.
c.) Use chopper stabilization to reduce the low-frequency noise.
Noise Analysis
1.) Insert a noise generator for each transistor that contributes to the noise. (Generally
ignore the current source transistor of source-coupled pairs.)
2.) Find the output noise voltage across an open-circuit or output noise current into a
short circuit.
3.) Reflect the total output noise back to the input resulting in the equivalent input noise
voltage.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-18
LOW NOISE OP AMPS
A Low-Noise, Two-Stage, Miller Op Amp
VDD
VDD
M7
M10
I5
M5
+
vin
-
2
en1
2
en2
M1
*
M1
M2
Cc
2
en8
vout
VBias
+
M8 M9
VBias
M3
M2
M8
*
2
en3
M4
M3
2
en4
*
*
VSS
The total output-noise voltage spectral density,
2
eto
2
2
2
m6
II n6
=g
R e
M4
VSS
2
eto,
M7
*
2
en6
M6
*
eto2
2
M9 en9
*
M11
2
en7
VSG7
*
VBias
M6
Fig. 7.5-1
is as follows where gm8(eff) 1/rds1,
2
2
2
2
2
2
2
+en7+RI2
gm12en1+gm22en2+gm32en3+gm42en4+(en8/rds12)+(en9/rds22)
2
Divide by (gm1RIgm6RII)2 to get the eq. input-noise voltage spectral density, eeq, as
2
2
2
2
2
eto
2en6
en8
2 gm32
en3
2 gm32
en3
= (gm1gm6RIRII)2 = gm12RI2 + 2en11+
gm1 2 +
2 2en11+
gm1 2 en1 gm12rds12en1
en1
2 = e 2 , e 2 = e 2 , e 2 = e 2 and e 2 = e 2 and g R is large.
where en6
m1 I
n7 n3
n4 n1
n2
n8
n9
2
eeq
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-19
1/f Noise of a Two-Stage, Miller Op Amp
Consider the 1/f noise:
Therefore the noise generators are replaced by,
B
2
2 2BK’Ii
(V2/Hz)
and
ini = fLi2
(A2/Hz)
eni = f WiLi
Therefore, the approximate equivalent input-noise voltage spectral density is,
KN’B N L1 2
2
2 eeq = 2en1 1+ KP’B P L3 (V2/Hz)
Comments;
2
• Because we have selected PMOS input transistors, en1 has been minimized if we
choose W 1L1 (W 2L2) large.
• Make L1<<L3 to remove the influence of the second term in the brackets.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-20
Thermal Noise of a Two-Stage, Miller Op Amp
Let us focus next on the thermal noise:
The noise generators are replaced by,
2 8kT
2 8kTgm
eni 3gm
(V2/Hz)
and
ini 3
(A2/Hz)
where the influence of the bulk has been ignored.
The approximate equivalent input-noise voltage spectral density is,
2
eeq
=
2 2 gm32en3
2en1
1+gm1 2 en1
=
2
2en1 1+
KNW 3L1 KPW 1L3 (V2/Hz)
Comments:
• The choices that reduce the 1/f noise also reduce the thermal noise.
Noise Corner:
Equating the equivalent input-noise voltage spectral density for the 1/f noise and the
thermal noise gives the noise corner, fc, as
3gmB
fc = 8kTWL
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-21
Example 290-3 Design of A Two-Stage, Miller Op Amp for Low 1/f Noise
Use the model parameters of KN’ = 120μA/V2, KP’ = 25μA/V2, and Cox = 6fF/μm2
along with the value of KF = 4x10-28 F·A for NMOS and 0.5x10-28 F·A for PMOS and
design the previous op amp with ID5 = 100μA to minimize the 1/f noise. Calculate the
corresponding thermal noise and solve for the noise corner frequency. From this
information, estimate the rms noise in a frequency range of 1Hz to 100kHz. What is the
dynamic range of this op amp if the maximum signal is a 1V peak-to-peak sinusoid?
Solution
1.) The 1/f noise constants, BN and BP are calculated as follows.
KF
4x10-28F·A
BN = 2CoxKN’ = 2·60x10-4F/m2·120x10-6A/V2 = 1.33x10-22 (V·m)2
and
KF
0.5x10-28F·A
BP = 2CoxKP’ = 2·60x10-4F/m2·25x10-6A/V2 = 1.67x10-22 (V·m)2
2.) Now select the geometry of the various transistors that influence the noise
performance.
2
To keep en1 small, let W1 = 100μm and L1 = 1μm. Select W3 = 10μm and L3 =
20μm and letW8 and L8 be the same as W1 and L1 since they little influence on the
noise.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-22
Example 290-3 - Continued
Of course, M1 is matched with M2, M3 with M4, and M8 with M9.
BP
1.67x10-22
1.67x10-12 2
2
(V /Hz)
en1 = f W1L1 = f·100μm·1μm =
f
120·1.33 1 1.67x10-12 3.33x10-12
3.452x10-12 2
2
2
2
1+
=
eeq = 2x
1.0365
=
(V /Hz)
25·1.67 20
f
f
f
Note at 100Hz, the voltage noise in a 1Hz band is 3.45x10-14V2(rms) or 0.186μV(rms).
3.) The thermal noise at room temperature is
8kT 8·1.38x10-23·300
2
en1 = 3gm = 3·500x10-6 = 2.208x10-17 (V2/Hz)
which gives
2
eeq
-17
= 2·2.208x10
1+
120·10·1 -17
-17 2
25·100·20 = 4.416x10 ·1.155= 5.093x10 (V /Hz)
2
4.) The noise corner frequency is found by equating the two expressions for eeq to get
3.452x10-12
fc = 5.093x10-17 = 67.8kHz
This noise corner is indicative of the fact that the thermal noise is much less than the 1/f
noise.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-23
Example 290-1 - Continued
5.) To estimate the rms noise in the bandwidth from 1Hz to 100,000Hz, we will ignore
the thermal noise and consider only the 1/f noise. Performing the integration gives
105
3.452x10-12
2
V eq(rms) = df = 3.452x10-12[ln(100,000) - ln(1)]
=
f
1
0.408x10-10 Vrms2 = 6.39 μVrms
The maximum signal in rms is 0.353V. Dividing this by 6.39μV gives 55,279 or 94.85dB
which is equivalent to more than 15 bits of resolution.
6.) Note that the design of the remainder of the op amp will have little influence on the
noise and is not included in this example.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-24
Low-Noise Op Amp using Lateral BJT’s at the Input
VDD
46.8
3.6
M13M14
46.8
3.6
vi2
M15M16
58.2
7.2
M5
Q1
58.2
7.2
M7
Q2
VSS
M3 M4
480
R1 18
=34kΩ
D1
1296
3.6
511
3.6
vi1
81.6
3.6
M10 M11
Rz = 300Ω Cc = 1pF vout
M12
M8 M9
M6
480
18
270
1.2
130 43.8
3.6 6.6
384
1.2
45.6
3.6
VSS
Fig. 7.5-6
10
Noise (nV/ Hz)
Experimental noise
performance:
8
Eq. input noise voltage of low-noise op amp
6
4
Voltage noise of lateral BJT at 170μA
2
0
CMOS Analog Circuit Design
10
100
1000
Frequency (Hz)
104
105
Fig. 7.5-7
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-25
Summary of Experimental Performance for the Low-Noise Op Amp
Experimental Performance
Value
Circuit area (1.2μm)
Supply Voltages
Quiescent Current
-3dB frequency (at a gain of 20.8 dB)
en at 1Hz
en (midband)
fc(en)
in at 1Hz
in (midband)
fc(in)
Input bias current
Input offset current
Input offset voltage
CMRR(DC)
PSRR+(DC)
PSRR-(DC)
Positive slew rate (60 pF, 10 k load)
Negative slew rate (60 pF, 10 k load)
0.211 mm2
±2.5 V
2.1 mA
11.1 MHz
23.8 nV/ Hz
3.2 nV/ Hz
55 Hz
5.2 pA/ Hz
0.73 pA/ Hz
50 Hz
1.68 μA
14.0 nA
1.0 mV
99.6 dB
67.6 dB
73.9 dB
39.0 V/μS
42.5 V/μS
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-26
Chopper-Stabilized Op Amps - Doubly Correlated Sampling (DCS)
Illustration of the use of chopper stabilization to remove the undesired signal, vu, form the
desired signal, vin.
Clock
Vu(f)
+1
Vin(f)
t
-1
f
T =1
fc
vu
f
vin
vB
vA
vC
A1
A2
vout
VA(f)
VB(f)
VC(f)
0
fc
2fc
3fc
0
fc
2fc
3fc
fc
2fc
3fc
0
CMOS Analog Circuit Design
f
f
f
Fig. 7.5-8
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-27
Chopper-Stabilized Amplifier
VDD
Chopper-stabilized Amplifier:
VDD
M3 M4
+
vin
M7 M8
φ1
φ1
φ2
-
φ2
M1 M2
φ2
φ1
M5 M6
φ2
φ1
IBias
IBias
V
Circuit equivalent during φ1 phase: SS
vu1
vueq
VSS
vu2
+ A1
+ A2
-
-
+
v
vueq = vu1 + u2
A1
Circuit equivalent during the φ2 vphase:
vu2
u1
+ A1
vueq
+
+ A2
-
+
vu2 , v (aver) =vu2
vueq = -vu1 +
ueq
A1
A1
+
Fig. 7.5-10
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-28
Example of a Two-Stage, Chopper-Stablized Op Amp
VDD
clkb
clkb
M3
clk
vnn
vnp
clkb
Cc
clk
clk
vnn
VDD
vnp
clkb
CMOS Analog Circuit Design
M6
M4
clkb
VNB1
vout
clk
M1
clk
clk
vnp
VDD
vnn
M2
M5
vnp
vnn
M7
clkb
070507-03
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-29
Experimental Noise Response of the Chopper-Stabilized Amplifier
1000
nV/ Hz
Without chopper
With chopper
fc = 16kHz
100
With chopper fc = 128kHz
10
0
10
20
30
Frequency (kHz)
40
50
Fig. 7.5-11
Comments:
• The switches in the chopper-stabilized op amp introduce a thermal noise equal to kT/C
where k is Boltzmann’s constant, T is absolute temperature and C are capacitors
charged by the switches (parasitics in the case of the chopper-stabilized amplifier).
• Requires two-phase, non-overlapping clocks.
• Trade-off between the lowering of 1/f noise and the introduction of the kT/C noise.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
Page 290-30
Improved Chopper Operation
In some cases, there are spurious signals in the neighborhood of the chopping
frequencies and its harmonics. These spurious signals such as common-mode
interference can mix to the baseband since the chopper amplifier is a time variant system
and therefore inherently nonlinear.
A bandpass filter centered at
fc
the clock frequency can be used to
eliminate the aliasing of the
Output
Input
spurious signals and achieve a
Amplifier
Amplifier
reduction in effective offset.
vou
vin
f
o
Output
Input
fc-fo
Bandpass
Filter
Modulator
Modulator
Let = fo and be a given
041006-03
†
bound of . It can be shown that
the achievable effective offset reduction, EOR, and the optimum Q for the bandpass filter,
Qopt, is
8Q
EOR = (1+8Q2) , <<1
and
Qopt = 1/ 8
Improvements of 14dB reduction in effective offset are possible for = 0.8%.
†
C. Menolfi and Q. Huang, “A Fully Integrated, Untrimmed CMOS Instrumentation Amplifier with Submicrovolt Offset,” IEEE J. of Solid-State
Circuits, vol. 34, no.8, March 1999, pp. 415-420.
CMOS Analog Circuit Design
© P.E. Allen - 2010
Lecture 290 – Low Power and Low Noise Op Amps (3/28/10)
•
•
•
•
•
•
•
•
Page 290-31
SUMMARY
Operation of transistors for low power op amps is generally in weak inversion
Boosting techniques are needed to get output sourcing and sinking currents that are
larger than that available during quiescent operation
Be careful about using circuits at weak inversion, i.e. the self-biased cascode will cause
the resistor to be too large
Primary sources of noise for CMOS circuits is thermal and 1/f
Noise analysis:
1.) Insert a noise generator for each transistor that contributes to the noise.
(Generally ignore the current source transistor of source-coupled pairs.)
2.) Find the output noise voltage across an open-circuit or output noise current into a
short circuit.
3.) Reflect the total output noise back to the input resulting in the equivalent input
noise voltage.
Noise is reduced in op amps by making the input stage gain as large as possible and
reducing the noise of this stage as much as possible.
The input stage noise can be reduced by using lateral BJTs (particularily the 1/f noise)
Doubly correlated sampling can transfer the noise at low frequencies to the clock
frequency (this technique is used to achieve low input offset voltage op amps).
CMOS Analog Circuit Design
© P.E. Allen - 2010