Laser Driver Design in 0.18 µm CMOS
Technology
by
Michael Charles O’Farrell
A thesis submitted to the
Department of Electrical and Computer Engineering
in conformity with the requirements for
the degree of Master of Applied Science
Queen’s University
Kingston, Ontario, Canada
September 2010
c Michael Charles O’Farrell, 2010
Copyright Abstract
This thesis presents the design and analysis of two high speed analog laser driver
stages (LDS) for use in a passive optical network (PON) upstream burst-mode transmitter (BM-Tx) using low cost complementary metal oxide semiconductors (CMOS)
technology. The maturation of CMOS technology has lead to aggressive scaling of
device sizes which has made it an increasingly attractive technology for high speed
analog design. CMOS provides high levels of integration as it is the industry standard
for digital circuits, analog and digital systems can share one substrate reducing costs.
Additionally CMOS is a more cost effective solution than traditional expensive high
speed analog substrates.
A 2.5 Gbps LDS fabricated in 0.18 µm CMOS technology is presented. The LDS
uses a two stage pre-amplifier. Stage one consists of a cascode differential pair with a
source follower voltage buffer, while stage two consists of a shunt inductively peaked
differential pair using active inductors. A differential pair composed of large transistors is used in an open drain configuration for the output stage. Measurements of
S-parameters are presented which accurately agree with simulations. Electrical eye
diagram measurements are presented which demonstrate the LDS is able to provide a
modulation current of 14.6-58 mA to a 50 Ω load. A 10%-90% approximate rise/fall
time of 200 ps was obtained for modulation currents below 44 mA, while a rise/fall
time of 230/260 ps was obtained for a modulation current of 58 mA. Power consumption of the core was determined to be 68.5 mW, while the chip consumed an area of
0.8 x 0.7 mm2 including pads. Bias currents greater than 50 mA were achieved under
i
DC testing.
A 10 Gbps LDS fabricated in 0.18 µm CMOS technology is also presented. The
LDS uses a cascode differential pair for the output stage. The pre-amplifier for this
design consists of a differential pair and utilizes spiral inductors for series inductive
peaking between the pre-amplifier and output stage. Measurements of S-parameters
are presented which accurately agree with simulations. Electrical eye diagram measurements are presented which demonstrate the LDS is able to provide a modulation
current of 22.6-62 mA. 10%-90% rise/fall time of 87 ps and 75 ps are respectively
obtained while operating at maximum modulation current. The core of the LDS consumes a power of 287 mW, while the chip consumed an area of 0.79 x 0.7 mm2 . Bias
currents greater than 50 mA were obtained while performing DC testing.
The measured electrical eye diagrams for the 2.5 Gbps and the 10 Gbps meet the
timing requirements for the GPON standard. Further work is needed to investigate
whether or not the timing requirements would still be met once the CMOS chips are
integrated with commercial laser diodes.
ii
Acknowledgments
I would like to acknowledge and thank the many people and agencies who have aided
in the completion of this thesis. Integrated circuit fabrication support was supplied
by CMC Microsystems, testing equipment was made available through the Advanced
Photonics Systems Lab (APSL) of the National Microelectronics and Photonics Testing Collaboratory and financial support was provided by Queen’s University.
First, I would like to thank my thesis supervisor Dr. Brian Frank for his guidance,
encouragement and patience over the past years. His support and technical expertise
in CMOS design were instrumental in the success of this work.
Second, I would like to express my deep gratitude to the students of the Very High
Speed Circuits Group at Queen’s University. Thank you for always being available
and having the patience to talk through many design issues associated with this work.
The occasional distractions were always welcome during the long hours in the lab. I
have gained some great friends.
Third, I would like to thank Patricia Greig, lab engineer of the APSL. You have
always been able to accommodate my testing needs. Our discussions have been very
valuable are greatly appreciated.
Finally I would like to thank my family. Without the support of my parents, Joe
and Katherine I never would have been able to complete this degree - thank you. To
my brothers, you have been a vital part of my life and are a huge part of who I am
today. To my girlfriend Kelsee, thanks for all the proofreading and support this last
year.
iii
Table of Contents
Abstract
i
Acknowledgments
iii
Table of Contents
iv
List of Tables
vii
List of Figures
ix
Nomenclature
xiii
Chapter 1: Introduction
1.1 Motivation . . . . . . . . . . . . . . . . . . .
1.2 Fiber to the Home . . . . . . . . . . . . . .
1.2.1 Multiple Access Techniques for PONs
1.3 Challenges of CMOS . . . . . . . . . . . . .
1.4 Thesis Overview and Major Contributions .
Chapter 2: Background Theory
2.1 The Optical Communication Link
2.2 Optical Source . . . . . . . . . . .
2.3 Semiconductor Laser . . . . . . .
2.3.1 L-I Curve . . . . . . . . .
2.3.2 Large-Signal Modulation .
2.3.3 Thermal Effects . . . . . .
2.3.4 Turn-on Delay . . . . . . .
2.4 GPON Performance Metrics . . .
2.5 Figures of Merit . . . . . . . . . .
2.5.1 Eye Diagram . . . . . . .
2.5.2 Eye Mask . . . . . . . . .
iv
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1
1
3
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7
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26
Chapter 3: Literature Review
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 CMOS Burst-Mode Transmitters . . . . . . . . . . . . . . . . . . . .
28
28
28
Chapter 4: 2.5 Gbps Laser Driver Design
4.1 Introduction . . . . . . . . . . . . . . . . . . . . .
4.2 Design Goals and Assumptions . . . . . . . . . .
4.3 Output Stage Topology - CMOS Differential Pair
4.3.1 Large Signal Operation . . . . . . . . . . .
4.4 Pre-Driver Topology . . . . . . . . . . . . . . . .
4.5 2.5 Gbps Laser Driver Design . . . . . . . . . . .
4.5.1 Final Schematic . . . . . . . . . . . . . . .
4.6 Simulation Results . . . . . . . . . . . . . . . . .
4.7 Measured Results . . . . . . . . . . . . . . . . . .
4.7.1 Small Signal Measurements . . . . . . . .
4.7.2 Time Domain Measurements . . . . . . . .
4.8 Conclusion and Discussion . . . . . . . . . . . . .
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44
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46
48
50
52
54
56
60
63
66
83
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86
86
86
88
89
91
92
94
99
101
106
117
Chapter 5: 10 Gbps Laser Driver Design
5.1 Introduction . . . . . . . . . . . . . . . . . . .
5.2 Design Goals and Assumptions . . . . . . . .
5.3 Output Stage - The Differential Cascode . . .
5.4 Pre-Driver . . . . . . . . . . . . . . . . . . . .
5.5 10 Gbps Laser Driver Design . . . . . . . . . .
5.5.1 Final Schematic . . . . . . . . . . . . .
5.6 Simulation Results . . . . . . . . . . . . . . .
5.7 Measured Results . . . . . . . . . . . . . . . .
5.7.1 Small Signal Measurements . . . . . .
5.7.2 Electrical Eye Diagram Measurements
5.8 Conclusion and Discussion . . . . . . . . . . .
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Chapter 6: Conclusions and Future Work
121
6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
References
125
Appendix A: Integration
130
v
A.0.1 PCB Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
A.0.2 Wirebonding Attempt . . . . . . . . . . . . . . . . . . . . . . 134
A.0.3 Future Suggestions . . . . . . . . . . . . . . . . . . . . . . . . 136
vi
List of Tables
2.1
Typical Characteristics of Diode Light Sources . . . . . . . . . . . . .
12
2.2
ITU-T Upstream Transmission Performance Reccomendation G.984.3
24
2.3
Eye Mask Properties for Transmitted Upstream Optical Signal . . . .
27
4.1
2.5 Gbps Laser Driver Design Goals . . . . . . . . . . . . . . . . . . .
46
4.2
LVDS Volage Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . .
50
4.3
2.5 Gbps LDS Component Values . . . . . . . . . . . . . . . . . . . .
54
4.4
Bias voltages for S-parameter Measurements . . . . . . . . . . . . . .
65
4.5
2.5 Gbps Measured and Simulated Gain and Bandwidth Results . . .
65
4.6
Measured PRBS Characteristics Used in ADS for Simulation . . . . .
68
4.7
2.5 Gbps Approximate Measured and Simulated Eye Diagram Voltages 81
4.8
2.5 Gbps Approximate Measured and Simulated Rise and Fall Times
82
4.9
2.5 Gbps Approximate Measured and Simulated Modulation Currents
82
4.10 2.5 Gbps Laser Driver Performance Comparison . . . . . . . . . . . .
85
5.1
10 Gbps Laser Driver Design Goals . . . . . . . . . . . . . . . . . . .
87
5.2
LVPECL Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . .
90
5.3
10 Gbps LDS Component Values . . . . . . . . . . . . . . . . . . . .
93
5.4
Bias voltages for S-parameter Measurements . . . . . . . . . . . . . . 103
5.5
10 Gbps Measured and Simulated Gain and Bandwidth Results . . . 104
5.6
10 Gbps Approximate Measured and Simulated Eye Diagram Voltage
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
vii
5.7
10 Gbps Approximate Measured and Simulated Eye Diagram Timing
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
5.8
10 Gbps Approximate Measured and Simulated Modulation Currents
5.9
10 Gbps Laser Driver Performance Comparison . . . . . . . . . . . . 120
viii
117
List of Figures
1.1
Fiber Access Network Architectures . . . . . . . . . . . . . . . . . . .
3
1.2
Passive Optical Network Architecture . . . . . . . . . . . . . . . . . .
4
1.3
Integrated PON Transceiver . . . . . . . . . . . . . . . . . . . . . . .
7
1.4
Typical Burst Mode Laser Driver Block Diagram . . . . . . . . . . .
8
2.1
Simplified Block Diagram of Optoelectric Link . . . . . . . . . . . . .
11
2.2
Ideal Power-Current Relationships (LI Curve) . . . . . . . . . . . . .
12
2.3
Comparison of Spontaneous and Stimulated Emission in a Semiconductor Laser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
2.4
Semiconductor Laser Energy Level Diagrams . . . . . . . . . . . . . .
16
2.5
Simplified Cross Section of a Double Heterostructure Laser . . . . . .
17
2.6
Optical Output Power Versus Input Current for a Laser (L-I Curve) .
18
2.7
Example of Relaxation oscillation in Lasers . . . . . . . . . . . . . . .
19
2.8
Temperature Effects on Ith and Optical Output Power for a Laser Diode 21
2.9
Temperature Dependence of Optical Output Power for a Given Modulation Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
2.10 Simplified Example of Variable Delay in a Laser Diode . . . . . . . .
24
2.11 Ideal Eye Diagram of an Optical System for an NRZ Modulation Format 25
2.12 Eye Diagram Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
3.1
Laser Driver Block Diagram . . . . . . . . . . . . . . . . . . . . . . .
29
3.2
Burst Mode Power Control Block Diagram . . . . . . . . . . . . . . .
30
3.3
Peak Comparator Circuit . . . . . . . . . . . . . . . . . . . . . . . . .
31
ix
3.4
Burst-Mode Upstream Transmitter with APC Block Diagram . . . .
33
3.5
Laser Driver Schematic and Peak Detection Circuit . . . . . . . . . .
34
3.6
Laser Driver Block Diagram . . . . . . . . . . . . . . . . . . . . . . .
35
3.7
TIA and V/I Converter . . . . . . . . . . . . . . . . . . . . . . . . . .
36
3.8
Burst-Mode Laser Diode Driver Block Diagram . . . . . . . . . . . .
38
3.9
Burst-Mode Modulation and Bias Circuit Schematics . . . . . . . . .
39
3.10 Peak Detection Circuit Schematic . . . . . . . . . . . . . . . . . . . .
40
3.11 LDS Output Stage Schematic . . . . . . . . . . . . . . . . . . . . . .
41
4.1
CMOS Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . .
47
4.2
Normalized Plots of the Currents in a CMOS Differential Pair . . . .
49
4.3
2.5 Gbps LDS Pre-Driver Topology . . . . . . . . . . . . . . . . . . .
51
4.4
Active Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
4.5
2.5 Gbps LDS Output Schematic . . . . . . . . . . . . . . . . . . . .
53
4.6
2.5 Gbps LD Final Schematic . . . . . . . . . . . . . . . . . . . . . .
54
4.7
Current Mirrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
4.8
Layout of 2.5 Gbps CMOS Laser Driver Stage . . . . . . . . . . . . .
56
4.9
Altered Layout for Extraction . . . . . . . . . . . . . . . . . . . . . .
57
4.10 Momentum simulation setup for top metal layer . . . . . . . . . . . .
57
4.11 ADS Transient Simulation Setup . . . . . . . . . . . . . . . . . . . .
58
4.12 Transient Simulation Results . . . . . . . . . . . . . . . . . . . . . . .
59
4.13 Transient Simulation Results From 70-80 ps . . . . . . . . . . . . . .
61
4.14 Simulated Eye Diagrams . . . . . . . . . . . . . . . . . . . . . . . . .
62
4.15 Die photograph of 2.5 Gbps LDS . . . . . . . . . . . . . . . . . . . .
63
4.16 Four Port S-parameter Test Setup . . . . . . . . . . . . . . . . . . . .
64
4.17 ADS Simulation Setup for S21 . . . . . . . . . . . . . . . . . . . . . .
66
4.18 2.5 Gbps LDS Measured and Simulated S21 . . . . . . . . . . . . . .
67
4.19 Transient Measurement Test Setup . . . . . . . . . . . . . . . . . . .
69
x
4.20 Measured 2.5 Gbps input signal . . . . . . . . . . . . . . . . . . . . .
70
4.21 Measured and Simulated 2.5 Gbps Input Signal . . . . . . . . . . . .
71
4.22 2.5 Gbps Simulated and Measured Eye Diagram vmod = 0.7 . . . . .
72
4.23 2.5 Gbps Simulated and Measured Eye Diagram vmod = 0.8 . . . . .
73
4.24 2.5 Gbps Simulated and Measured Eye Diagram vmod = 0.9 . . . . .
74
4.25 2.5 Gbps Simulated and Measured Eye Diagram vmod = 1.0 . . . . .
75
4.26 2.5 Gbps Simulated and Measured Eye Diagram vmod = 1.3 . . . . .
76
4.27 625 Mbps Simulated and Measured Eye Diagram vmod = 0.9 . . . .
77
4.28 1.25 Gbps Simulated and Measured Eye Diagram vmod = 0.9 . . . .
78
4.29 3.0 Gbps Simulated and Measured Eye Diagram vmod = 0.9 . . . . .
79
4.30 4.0 Gbps Simulated and Measured Eye Diagram vmod = 0.9 . . . . .
80
4.31 2.5 Gbps Commercial Laser Diode LI Curve . . . . . . . . . . . . . .
84
4.32 Measured Eye Diagram with Eye Mask . . . . . . . . . . . . . . . . .
85
5.1
Differential Cascode . . . . . . . . . . . . . . . . . . . . . . . . . . . .
88
5.2
Schematic of the 10 Gbps LDS Pre-Amplifier . . . . . . . . . . . . . .
90
5.3
Schematic of the 10 Gbps Output Stage . . . . . . . . . . . . . . . .
91
5.4
10 Gbps LDS schematic . . . . . . . . . . . . . . . . . . . . . . . . .
92
5.5
Layout of 10 Gbps CMOS Laser Driver Stage . . . . . . . . . . . . .
93
5.6
1.5 nH inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
94
5.7
Extracted layout for simulation . . . . . . . . . . . . . . . . . . . . .
95
5.8
Momentum simulation of top metal layer . . . . . . . . . . . . . . . .
95
5.9
ADS Transient Simulation Setup . . . . . . . . . . . . . . . . . . . .
96
5.10 Transient Simulation Results . . . . . . . . . . . . . . . . . . . . . . .
97
5.11 Transient Simulation Results From 17.5-20 ns . . . . . . . . . . . . .
98
5.12 Simulated Eye Diagrams . . . . . . . . . . . . . . . . . . . . . . . . .
99
5.13 10 Gbps Laser Driver Stage Chip Photo . . . . . . . . . . . . . . . . 100
5.14 FIB of 10 Gbps LDS . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
xi
5.15 Four Port S-parameter Test Setup . . . . . . . . . . . . . . . . . . . . 102
5.16 ADS Simulation Setup for S21 . . . . . . . . . . . . . . . . . . . . . . 104
5.17 Measured and Simulated Gain . . . . . . . . . . . . . . . . . . . . . . 105
5.18 Transient Measurement Test Setup . . . . . . . . . . . . . . . . . . . 107
5.19 10 Gbps Simulated and Measured Eye Diagram vmod=0.9 V . . . . . 109
5.20 10 Gbps Simulated and Measured Eye Diagram vmod=1.2 V . . . . . 110
5.21 10 Gbps Simulated and Measured Eye Diagram vmod=1.5 V . . . . . 111
5.22 10 Gbps Simulated and Measured Eye Diagram vmod=1.8 V . . . . . 112
5.23 2.5 Gbps Simulated and Measured Eye Diagram vmod=1.8 V . . . . 113
5.24 5.0 Gbps Simulated and Measured Eye Diagram vmod=1.8 V . . . . 114
5.25 7.0 Gbps Simulated and Measured Eye Diagram vmod=1.8 V . . . . 115
5.26 10 Gbps Comercial Laser Diode LI Curve . . . . . . . . . . . . . . . . 118
5.27 Measured Eye Diagram with Eye Mask . . . . . . . . . . . . . . . . . 119
A.1 Manufactured PCBs . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
A.2 Photograph of CMOS Chip Attached to PCB . . . . . . . . . . . . . 133
A.3 Photograph of Wire bonder Setup in PEARL Lab . . . . . . . . . . . 134
A.4 Example of Successful Planar Wirebond on PCB . . . . . . . . . . . . 135
A.5 Example of Wirebond Length Required . . . . . . . . . . . . . . . . . 136
xii
Nomenclature
Latin Symbols
A
Ampere
c
Speed of Light [m/s]
CGD
Gate to Drain Capacitance [F]
dB
Decibel
eV
Electron Volts [J]
gm
Transconductance [V/V]
IP D
Photodiode Current [mA]
Ith
Threshold Current [mA]
ID
Drain Current [A]
IREF
Reference Current [A]
P1
Power for a 1
P0
Power for a 0
Q
Quality Factor
R
Responsivity [A/W]
RD
Dampening Resistor [Ω]
s
seconds
Sd1
Signal level for a 1
Sd0
Signal level for a 0
T
Temperature [K]
xiii
VBIAS
Bias Control Voltage [V]
Vd
Drain Voltage [V]
Vg
Gate Voltage [V]
VM OD
Modulation Control Voltage [V]
VP C
Pre-charge Voltage [V]
VREF
Reference Voltage [V]
W
Watt [J/s]
Greek Symbols
λ
Wavelength [1/m]
Ω
Ohm
ν
Frequency [1/s]
Acronyms
AC
Alternating Current
ABC
Automatic Bias Control
ADC
Analog-to-Digital Converter
ADS
Advanced Design System
AMC
Automatic Modulation Control
APC
Automatic Power Control
APON
ATM Passive Optical Network
ATM
Asynchronous Transfer Mode
BER
Bit Error Rate
BM-Tx
Burst-Mode Transmitter
CMOS
Complimentary Metal Oxide Semiconductor
COB
Chip On Board
DAC
Digital-to-Analog Converter
xiv
DC
Direct Current
DFB
Distributed Feedback
DIG
Digital Block (Counter)
DSL
Digital Subscriber Line
DUT
Device Under Test
EM
Electro-Magnetic
EPON
Ethernet Passive Optical Network
EOL
End of Life
ER
Extinction Ratio
FET
Field-Effect Transistor
FP
Fabry-Perot
GaAs
Gallium Arsenide
Gbps
Gigabits Per Second
GPON
Gigabit Passive Optical Network
HDTV
High Definition Television
HFC
Hybrid Fiber Coax
I/V
Current-to-Voltage
IC
Integrated Circuit
IDGCFN
Intrinsic Drain-Gate Capacitance Feedback Network
IEEE
Institute of Electrical and Electronics Engineers
InP
Indium Phosphide
ISI
Inter Symbol Interference
ITU-T
International Telecommunications Union - Standards Sector
LDS
Laser Driver Stage
LED
Light Emitting Diode
LVDS
Low Voltage Differential Signaling
LVPECL
Low Voltage Positive Emitter Coupled Logic
xv
Mbps
Mega bits per second
MMIC
Monolithic Microelectronic Integrated Circuit
MIC
Microelectronic Integrated Circuit
MiM
Metal-Insulator-Metal
NG-PON
Next Generation Passive Optical Network
nMOS
n-type Metal Oxide Semiconductor
NRZ
Non Return to Zero
MPD
Monitor Photodiode
OCDMA
Optical Code Division Multiple Access
OLT
Optical Line Termination
ONU
Optical Network Unit
P2P
Point-to-Point
P2MP
Point-to-Multi-Point
PC
Peak Comparator
PCB
Printed Circuit Board
PCML
Pseudo Current Mode Logic
PD
Photodiode
PIC
Photonic Integrated Circuit
pMOS
p-type Metal Oxide Semiconductor
PON
Passive Optical Network
PRBS
Pseudo Random Bit Sequence
PSTN
Public Switched Telephone Network
RGC
Regulated-Cascode
SCMA
Subcarrier Multiple Access
SNR
Signal to Noise Ratio
TDMA
Time Division Multiple Access
TODC
Turn-On Delay Compensation
xvi
TSMC
Taiwan Semiconductor Manufacturing Company
TIA
Transimpedance Amplifier
TX enable
Transmission Enable
VCSEL
Vertical Cavity Surface-Emitting Laser
VNA
Vector Network Analyzer
VoD
Video on Demand
VoIP
Voice Over Internet Protocol
V/I
Voltage-to-Current
WDMA
Wavelength Division Multiple Access
XG-PON
Next Generation PON
xvii
Chapter 1
Introduction
1.1
Motivation
Prior to the boom of the Internet in the early to mid 1990’s, telecommunication
customers primarily used standard telephones, fax machines, or dial-up modems to
communicate [1]. Users were connected via the public switched telephone network
(PSTN), which consists of twisted-pair copper wire lines that run from the users home
to the local telecommunications switching center. To increase long haul link usage,
telecommunication service providers would multiplex many low speed users onto highspeed, high capacity optical links. Companies focused a great deal of time and money
deploying long haul, large capacity optical links for long distance communication,
while neglecting to update the lower speed access network which connects customers
to the local switching station.
Coupled with the Internet boom, personal computing power has also advanced at a
ferocious pace. Many users are now demanding higher bandwidth applications such as
high speed Internet, video on demand (VoD), high definition television (HDTV), and
voice over Internet protocol (VoIP). However, due to the high cost of implementing
a fiber-based network, legacy systems such as hybrid fiber coax (HFC) and digital
subscriber line (DSL) currently dominate at this access level. HFC was the cable
1
CHAPTER 1. INTRODUCTION
2
companies solution for delivering television services in dense urban environments and
now also provides Internet services. However, due to the growth of the Internet and
the increasing demand for high speed digital services, these legacy systems are being
pushed to their maximum capacity. This has created a bottleneck in the last mile of
the communications networks.
Telecommunication service providers are being challenged to identify opportunities for revenue growth through innovation of the access network [2]. The most
desirable scenario is to be able to support voice, video and data communications all
over one network. This has been described as the ’triple play’ [3] of services. Before
service providers deploy a network to meet these needs at the access level they must
consider the networks ability to grow for future use. It is tough predict the bandwidth
requirements of future applications, however before investing the money to deploy the
infrastructure required, they must ensure that the network can meet future needs and
have a reasonable lifetime.
Over the past several years there have been many advances in the backbone of
fiber networks. There are multi-channel terrestrial optical links operating at 10 gigabits per second (Gbps) and rapidly approaching 40 Gbps. Novel solutions are needed
to push the deployment of fiber further to the end user. The cost of long haul and
metropolitan networks are absorbed by many customers which make them economically viable. Passive Optical Networks (PONs) are thought to be a viable solution
for access networks as they can offer near unlimited bandwidth, long lifetime and
point-to-multi-point (P2MP) communication. The renewed interest in these PONs is
due to many technological factors that have led to lowering the cost of electrical and
optical components, and further integration making them economically attractive [4].
3
CHAPTER 1. INTRODUCTION
1.2
Fiber to the Home
When deploying fiber into the access network, three network architectures are commonly considered [5, 6]. The first is a Point-to-Point (P2P) architecture, shown in
Figure 1.1a. For this network a dedicated fiber is run from the local exchanges optical
line terminal (OLT) to each customers optical network unit (ONU). This architecture
has a higher initial cost as a dedicated fiber is needed for each subscriber, and there
is more equipment required at the local exchange. This is a major drawback as none
of these costs are shared amongst the subscribers. However, the system provides the
largest capacity as each customer has a dedicated line and not have to share the
bandwidth with other users. This architecture also has the most flexibility as each
connection can be customized to meet the subscriber’s needs by making adjustments
to their associated ONU.
ONU
ONU
ONU
Customer
Termination
OLT
ONU
ONU
Local
Exchange
OLT
Active
Node
Customer
Termination
ONU
Local
Exchange
ONU
(a)
ONU
(b)
Figure 1.1: Fiber Access Network Architectures a) Point-to-Point b) Active Star
The remaining architectures are based around sharing a single fiber for a certain
length before splitting off, they are referred to as Point-to-Multi-Point (P2MP) networks. The first architecture is called the active star, shown in Figure 1.1b. For
this architecture, a single fiber is run from the local exchange to an active node. At
the active node the signal is split and individual fibers run to each customer’s ONU.
4
CHAPTER 1. INTRODUCTION
This system is advantageous as there is a shared fiber from the local exchange, which
reduces the amount of transmission equipment needed at the local exchange and
therefore reduces cost. Disadvantages of this system include the increased complexity
of the ONU as it is servicing many customers at once, the active node requires maintenance and power, and a reduced data throughput relative to the P2P architecture.
The second P2MP architecture is called the passive star. This architecture can be
seen in Figure 1.2. In this architecture the active node is replaced by a passive optical
splitter/combiner. This system shares all of the advantages of the active star. It also
eliminates active equipment in the field thereby reducing cost due to maintenance.
The trade off, however is a reduction in link length. This topology has become very
popular for pushing fiber into the access level. It has become widely known as the
PON.
Access Network
ONU
OLT
ONU
Optical power
splitter/combiner
ONU
Figure 1.2: Passive Optical Network Architecture
1.2.1
Multiple Access Techniques for PONs
With PONs being a very attractive solution for increasing bandwidth in the access
level, the challenges of sharing the link must be addressed. The common fiber feeder
of the PON is shared by all of the ONUs in the network. The data sent downstream
from the OLT is split at the passive splitter/combiner and received by all of the
CHAPTER 1. INTRODUCTION
5
ONUs. Each ONU must have a way to distinguish the appropriate data and ignore the
information intended for other customers. In addition, sending data in the upstream
direction from the ONU to the OLT requires accurate multiplexing to ensure collisionfree traffic in the common fiber. Multiple access techniques are needed to ensure
collision free traffic in both directions.
There have been several proposed multiple access techniques for PONs. The first
is time division multiplexing(TDMA), where each ONU is given a time slot to transmit and receive data. Synchronization is achieved from grants sent by the OLT to
instruct the ONU when to send a packet. To correctly time this process a ranging
protocol is needed upon start up to determine the different distances between customers. The second proposed access technique is subcarrier multiple access (SCMA).
In this scheme, the various ONUs modulate their packets onto a unique carrier frequency which is used to modulate the laser diode. This places packets into different
frequency bands which can be demultiplexed at the OLT. A third way to enable multiple access is through optical code division multiple access (OCDMA). In OCDMA
each ONU is given a unique optical code word. Two options exist for generating
this code word, one is a time-sliced word, and the other is a frequency-sliced word.
Lastly wavelength division multiple access (WDMA) has each ONU use a different
wavelength to send upstream data [6].
TDMA has received the most attention for implementing PONs as it allows for
high data rate multiple access with a low level of complexity. To date there have
been several standards developed that are based on TDMA; several are implemented
currently. The first standard developed was Asynchronous Transfer Mode (ATM)
PON (APON) where native ATM cells were used. This is outlined in the international telecommunication union (ITU-T) G.983 standard. Ethernet PON (EPON)
was developed by the Institute of Electrical and Electronics Engineers (IEEE) 802.3
ethernet group. This standard was designed to transmit ethernet packets in a TDMA
CHAPTER 1. INTRODUCTION
6
fashion. Lastly, the ITU-T updated the APON standard to the gigabit PON (GPON)
standard in which enabled ATM and ethernet packets to be transmitted with high
line rates up to 2.5 Gbps upstream and downstream. This is outlined in the ITU-T
G.984 standard series.
For this work TDMA was chosen as the standard multiple access technique, the
upstream laser driver located in the ONU must be able to operate in a burst mode
configuration. The laser driver must be able to bias up quickly and deliver a burst of
data, then turn off until it is needed again. The laser driver designed in chapter 4 is
designed to meet the GPON specification for 2.5 Gbps upstream transmission. The
laser driver designed in chapter 5 has been designed for future applications such as
next generation PON (XG-PON) at a bit rate of 10 Gbps [6].
1.3
Challenges of CMOS
To deploy the PON as discussed above, the infrastructure cost of laying the fiber will
be fixed. An area to explore for cost savings is to implement the ONU transceivers
as cheap as possible. Historically, monolithic microwave integrated circuits (MMICs)
for telecommunications were designed in III-V semiconductor technologies, such as
GaAs and InP [7]. These technologies have superior electron mobility, breakdown
voltages, and high quality-factor (Q) passives, which aid in designing high speed,
high bandwidth circuits needed for optical communications. However, due to the
aggressive scaling of the Complimentary Metal Oxide Semiconductor (CMOS) process
it is now possible to design high speed analog CMOS circuits [8]. The largest benefit
of moving from GaAs/InP to CMOS is the cost savings. CMOS circuits are widely
used in high volume digital circuits, which makes it a relatively cheap technology to
work with. In addition, greater levels of integration are possible on a single chip as
the analog and digital circuits can share one die.
7
CHAPTER 1. INTRODUCTION
1.4
Thesis Overview and Major Contributions
This thesis presents the design, fabrication and test of two analog high speed laser
driver stages (LDS) which are to be used in a GPON transceiver which was proposed
in [9]. The transceiver is a two chip solution consisting of a photonic integrated circuit
(PIC), and a microelectronic integrated circuit (MIC). The transceiver block diagram
is shown in Figure 1.3. The PIC integrates a photodiode and a laser, while the MIC
integrates the optical receiver with a laser driver used to generate the upstream signal.
Transceivers that are currently available use a number of discrete components that
add to the component cost, as well as the manufacturing cost of each transceiver. An
integrated solution can significantly reduce the cost, and provide better performance
by optimizing how the components to work together.
Focus of this work
PIC
MIC
Laser
Laser Driver
Cross Talk
Optical
Splitter
Photodiode
Optical Receiver
Figure 1.3: Integrated PON Transceiver
The block diagram of a fully implemented burst mode laser driver which is a
required component of the aforementioned transceiver is shown in Figure 1.4. This
thesis focuses on the design of the LDS in the block diagram, the blocks which function
as automatic power control (APC) are left for future work. The thesis is organized
as follows.
8
CHAPTER 1. INTRODUCTION
VDD
Focus of this work
Data
Data
Laser
Driver
Stage
Burst Enable
Bias Current
Controller
Level
Monitoring
Modulation Current
Controller
Figure 1.4: Typical Burst Mode Laser Driver Block Diagram
Chapter two reviews background theory relevant to the considerations needed to
be taken for designing high speed laser drivers in CMOS technology. First, a basic
optical communications system is presented. Next, a brief comparison of possible
optical sources is performed. A semiconductor laser diode and a light emitting diode
(LED) are examined. Following this, important characteristics of the semiconductor
laser diode are investigated. Finally, the GPON standard is presented followed by
discussing the figures of merit for the evaluation of system performance.
Chapter three consists of a literature review that presents the current work that
has been performed in the area of high speed laser diode driver design using CMOS
technology for upstream burst mode transmitters. A number of different topologies
are examined and their performance is compared.
Chapter four presents a 2.5 Gbps LDS fabricated using 0.18 µm CMOS technology.
The LDS uses a differential pair as the output stage. A two stage pre-driver is
implemented that accepts a low-voltage differential signaling (LVDS) signal as an
input. The driver is designed to be pseudo differential in order to improve noise
performance. Electrical eye diagram measurements are presented that show the LDS
CHAPTER 1. INTRODUCTION
9
can achieve a variable modulation current of 14.6-58 mA. A 10%-90% approximate
rise/fall time of 200 ps was obtained for modulation currents below 44 mA, while
an approximate rise/fall time of 230/260 ps was obtained for a modulation current
of 58 mA. Power consumption of the core was determined to be 68.5 mW while
consuming an area of 0.8 x 0.7 mm2 including pads. Bias currents greater than
50 mA were achieved under DC testing.
Chapter five presents the design of a 10 Gbps LDS using 0.18 µm CMOS technology. The driver consists of a differential input gain stage utilizing series inductive
peaking to drive the cascode output stage of the driver. The input signal is compliant
with the low voltage positive emitter coupled logic (LVPECL) differential signaling
standard. The driver is designed to be pseudo differential in order to improve noise
performance. Electrical eye diagram measurements are presented which demonstrate
the LDS is able to provide a modulation current of 22.6-62 mA. 10%-90% rise/fall
time of 87 ps and 75 ps are respectively obtained while operating at maximum modulation current. The core of the LDS consumes a power of 287 mW, while the chip
consumed an area of 0.79 x 0.7 mm2 . Bias currents greater than 50 mA were obtained
while performing DC testing.
Finally, chapter six concludes the work contained in the thesis and summarizes
the results. Discussion of future areas of work are also explored.
Chapter 2
Background Theory
2.1
The Optical Communication Link
The basic operation of a communication link is to transmit a signal from a source
at one location to a receiver at another location with a high degree of accuracy and
reliability. The block diagram for a simplified optical communication link is shown
in Figure 2.1. The link consists of an information source which provides a voltage
signal to the laser driver. The laser driver takes the voltage signal and converts
it into a modulated current signal to drive the laser diode. The laser diode then
generates a corresponding optical signal which is coupled into an optical medium and
is transmitted to the receiver. At the receiver the optical signal is coupled out of the
optical medium onto a photo diode. The photo diode is a square law device which
provides an output current dependent upon the power of the incident optical signal.
A transimpedance amplifier then converts the low amplitude output current from the
photo diode into a voltage which can then be used by the electronics in the receiver.
If the optical communication link is designed properly, the received bit pattern will
accurately match the pattern that was transmitted.
In a PON the optical medium consists of optical fiber, passive splitters and combiners. No optical wave regeneration is performed between the transmitter and receiver,
10
11
CHAPTER 2. BACKGROUND THEORY
Laser Diode
Photo Diode
Optical Fiber
LD
TIA
Figure 2.1: Simplified Block Diagram of Optoelectric Link
which greatly contrasts backbone long haul optical networks that perform dispersion
compensation and optical amplification in order to maintain an acceptable bit error
rate (BER). In a PON the link is also bidirectional and shared by multiple users.
The splitting ratio can potentially range from 1:16, 32, 64 and 128. Therefore, a
maximum of 128 users would have to share the upstream and downstream bandwidth
in the link.
2.2
Optical Source
The primary function of an optical source is to convert current from the laser driver
into light. The two primary light sources typically used in telecommunications are the
semiconductor laser and the LED. These sources are primarily used due to their small
form factor, low power requirements, compatibility with optical fibers and synergy
with solid state electronics [10]. There are several requirements that an optical source
must meet to serve this purpose. First, it should operate linearly with the electrical
input signal. Second, it needs to be able to emit light at the appropriate wavelength
in the range of 1260-1360 nm. Finally, it should have the capability of maintaining a
stable output in the presence of temperature variation and aging.
For a LED the relationship of optical power out is linear with the input current,
as shown in Figure 2.2a. When the input current is increased above 0 mA the emitted
optical power increases. This contrasts a laser diode which has a threshold current
12
CHAPTER 2. BACKGROUND THEORY
(Ith ),below which the laser diode emits little light. This is shown in Figure 2.2b. Once
Optical Power (mW)
Optical Power (mW)
the input current increases above Ith the emitted optical power increases linearly.
Ith
Current (mA)
Current (mA)
(a)
(b)
Figure 2.2: Ideal Power-Current Relationship for a) LED b) Semiconductor Laser
A comparison of the two types of optical sources is presented in Table 2.1. In addition, multi-mode and single mode laser diode characteristics are also presented. Due
to the geometry of the semiconductor lasers, certain lasers output multiple frequency
components (fabry-perot laser) while others output single frequency components (distributed feedback laser). The table examines the critical properties to consider for
the selection of the optical source for a PON.
Table 2.1: Typical Characteristics of Diode Light Sources taken from [10]
Property
LED
Spectral Width (nm)
Rise time (ns)
Modulation bandwidth (MHz)
Temperature sensitivity
Circuit Complexity
Lifetime (hours)
20-100
2-250
<300
Low
Simple
105
Multi-Mode
Laser Diode
1-5
0.1 - 1
2000
High
Complex
104 - 105
Single-Mode
Laser Diode
<0.2
0.05 - 1
6000
High
Complex
104 - 105
CHAPTER 2. BACKGROUND THEORY
13
The first and most important observation that we can take from the comparison
in Table 2.1 is the difference in modulation bandwidth between LED and a semiconductor laser. The modulation bandwidth expresses how fast the devices output
optical power can reliably adjust to changes in the input current. The LED has a
much lower maximum modulation bandwidth of 300 MHz while a single-mode semiconductor laser is rated for 6000 MHz. The GPON standard is outlined for upstream
data rates of 155, 622, 1244, and 2488 Mbps respectively. Due to these data rates
the logical choice of an optical source is a single-mode laser which can be used as the
system is upgraded. Another attractive property is the narrow spectral width of the
laser. Since there is no dispersion compensation in the PON, a source with a narrow
spectral width will be able to achieve greater distances than one with a broad width.
However, utilizing a laser will increase the complexity of the laser driver design.
Table 2.1 indicates that the semiconductor laser has a greater temperature sensitivity than the LED. Additional circuitry is required in order to maintain a constant
optical output. The operating speed of the semiconductor laser also requires creative
techniques to be used in order to reach these frequencies of operation in a 0.18 µm
CMOS realization.
The following section will provide a more in depth look at the operation and design
considerations that must be taken into account when designing a CMOS laser driver
for a semiconductor laser diode.
2.3
Semiconductor Laser
A semiconductor laser is an optical oscillator [11]. A system will oscillate if it can
provide both positive feed back and adequate gain at the frequency of interest. A
semiconductor laser provides adequate gain via stimulated emission as light travels
through its active region.
CHAPTER 2. BACKGROUND THEORY
14
To further understand how a semiconductor laser amplifies light, we will investigate the differences between stimulated and spontaneous emission. In a semiconductor
the outer electrons can have two energy levels. Figure 2.3a shows these two levels
which are referred to as the conduction band and valence band. The difference between these two energy levels is quantized. Electrons can also move between the two
states by absorbing a photon and moving from E1 to E2 , or by releasing energy in the
form of a photon moving from E2 to E1 . Figures 2.3b and 2.3c show this phenomenon
respectively. The situation depicted in Figure 2.3c is referred to as spontaneous emission which is an effect exploited in many light sources including LEDs and fluorescent
lamps [11]. Light produced by spontaneous emission is incoherent which means that
it is formed with an arbitrary phase and polarization.
Alternatively, a photon traveling in the material can interact with an electron in
the conduction band knocking it to the valence band creating an additional photon.
The newly created photon contains the same phase as the original photon, and now
they can travel through the material together. This process is called stimulated
emission, which is how a laser operates. The term laser is actually an acronym for
Light Amplification by Stimulated Emission of Radiation. This process can be seen
in Figure 2.3d. This effect can continue as long as electrons are supplied to the upper
energy states. Photons will also interact with electrons in the valence band being
absorbed and rising to the conduction band.
A semiconductor laser operates on the principle of having the density of electrons
in the conduction band consistently exceeding that of the electrons in the valence
band. This is referred to as population inversion and is achieved by injecting the
laser with a current large enough (Ith ) to have the conduction band consistently
supplied with electrons. Once population inversion is achieved, a cycle begins where
photons interact with electrons stimulating more photons. Confining the photons to
the active region allows for optical amplification to occur.
15
CHAPTER 2. BACKGROUND THEORY
Conduction
Band E2
E2
Photon
Valence E1
Band
E1
(a)
(b)
Photon
E2
E2
Photon
E1
(c)
Photon
E1
(d)
Figure 2.3: Comparison of Spontaneous and Stimulated Emission in a Semiconductor
Laser (a) Energy Levels in a Semiconductor, (b) Excitation of an Electron to the
Conduction Band Via a Photon, (c) Spontaneous Emission, (d) Stimulated Emission
Typically a laser is manufactured with a direct-bandgap semiconductor such as
AlGaAs or InGaAsP [11]. A material is said to be direct bandgap if an electron
from the conduction band can transition directly to the valence band. Through this
transition a photon is emitted with energy equal to hν or hc/λ where h is Planck’s
constant h=6.6256x10−34 Js, ν is the optical frequency, λ is the wavelength and c is
the speed of light. Examples of energy level diagrams of direct bandgap and indirect
bandgap materials can be seen in Figure 2.4. In an indirect bandgap material the
electron transition from conduction band to valence band can occur via a photon
and phonon transition. A phonon is a vibrational translation of energy in the crystal
lattice of the material. Due to this fact, indirect bandgap materials are not used
to make semiconductor lasers because the light emitted from them would not be
coherent due to the possibility of multiple photon energies produced. A material with
a bandgap energy of approximately 0.947eV is needed to emit light near 1310 nm [12].
Generally, a semiconductor laser achieves population inversion through the use
16
CHAPTER 2. BACKGROUND THEORY
Conduction Band
Electron Transition
Conduction Band
Phonon of Energy
Photon Energy
E=hν
E1
Photon Energy
E2
E1 6= E2
Valence Band
(a)
Valence Band
(b)
Figure 2.4: Bandgap Energy Level Diagrams (a) direct bandgap, (b) indirect bandgap
of a double heterostructure which can be seen in Figure 2.5. A narrow bandgap InGaAsP active layer is sandwiched between the two larger bandgap p-type and n-type
InP layers. The difference in bandgap energy between the active and cladding regions
creates a barrier for electrons and holes generated in the active region. In addition,
due to its lower refractive index, the active region acts as an optical waveguide for
photons that are generated [11]. When the p-n junction is forward biased the normally
empty conduction band of the semiconductor becomes populated with electrons and
population inversion is achieved for stimulated emission. To ensure the continuation
of stimulated emission, antireflective coating is deposited on the facets of the semiconductor laser to aid in confining photons to the active region. The coating allows
for a portion of the light to escape which is the output of the laser, while another
portion is reflected to aid in the continued process of stimulated emission. This is the
mechanism which provides the positive feedback to the system and allows the laser
to act as an oscillator.
The structure of the laser described in the previous paragraph is called a FabryPerot (FP) laser. It is an edge emitting structure that produces a multi-mode output
signal. In many cases the side-modes produce undesirable effects due to each mode
experiencing different delays during propagation due to dispersion in the fiber. Many
technological advances have been made to improve the operational performance of
17
CHAPTER 2. BACKGROUND THEORY
Anode
111111
000000
+
000000
111111
000000
111111
p-InP 111111
000000
000000
111111
000000
111111
InGaAsP 111111
000000
000000
111111
000000
111111
000000
n-InP 111111
000000
111111
000000
111111
-
Active
Region
Cathode
Figure 2.5: Simplified Cross Section of a Double Heterostructure Laser
semiconductor lasers. Distributed feedback (DFB) lasers utilize a periodic Bragg
grating in the cladding layer above or below the active layer to produce a wavelength
selective feedback. This grating produces differences in the index of refraction which
attenuate certain wavelengths while letting others pass with little attenuation. DFB
lasers can provide side-mode suppression up to 30 dB below the fundamental and
operate at rates of up to 20 Gbps [11].
Many of the advances made in laser technology attempt to improve certain characteristics of the laser such as IT H , slope efficiency, output power and direct modulation
speeds. While designing a laser driver the following effects must be considered.
2.3.1
L-I Curve
When designing a laser driver it is important examine the measure of the optical
power emitted from the laser as a function of the injection current. This is referred
to as the L-I curve of the laser; a sample plot can be seen in Figure 2.6. From this
plot the designer can locate the threshold current IT H , which is an important value
in the design. While the injected current is below IT h , the emitted optical power is
minimal and is generated via spontaneous emission. Once the current is raised above
IT h lasing occurs and the output optical power increases rapidly.
In addition to IT h , the L-I curve indicates the output optical power for a given
input drive current. In reality the L-I curve is exponential in nature, however, one
18
CHAPTER 2. BACKGROUND THEORY
Optical Output
Power
(mW)
Spontaneous
Stimulated
Emission
Emission
Ith
Input Current (mA)
Figure 2.6: Optical Output Power Versus Input Current for a Laser (L-I Curve)
can take a linear approximation over a limited range of the curve to define the slope
efficiency of the laser as
∆P
∆I
(mW/mA). The slope efficiency indicates the incremental
power gain per mA of additional drive current.
With these values the designer can place minimum and maximum allowances for
the required amount of bias current and modulation current needed for the laser
driver.
2.3.2
Large-Signal Modulation
A laser diode is typically directly modulated with a large current when used as a
transmitter in a PON. Generally the laser diode is biased just above IT H to ensure
a minimum power level for a Sd0 . It is then modulated with a larger current corresponding to an appropriate power level for a Sd1 . The large currents are required
to ensure the power level difference between a Sd0 and a Sd1 are large enough that
the receiver can differentiate between them. Two important factors to consider while
directly modulating a laser diode with a large-signal are: 1) Relaxation oscillations,
and 2) Laser Chirping. Both are limiting factors for the maximum modulation speed
of a laser diode.
19
CHAPTER 2. BACKGROUND THEORY
Relaxation oscillations are a result of the interaction between carrier and photon
densities in the laser’s active region. When a step input of current occurs, stimulated
emission raises the photon density to a certain level which causes electron density in
the upper level to fall. Electrons then accumulate again in the upper energy level.
This exchange of energy causes a ringing in the output optical power which can be
seen in Figure 2.7. The transition from a 0 to a 1 causes a higher resonant frequency
than the transition from a 1 to a 0, which can also be observed in Figure 2.7. Due
to the ringing there is an introduced nonlinear pattern dependence in the modulated
signal. At a high modulation speed, the pulse width of a single bit narrows and
relaxation oscillations limit the speed of lasers [11]. The ringing created with each
transition can affect the next transition, causing inter symbol interference (ISI) and
jitter.
Pout
t
Figure 2.7: Example of Relaxation oscillation in Lasers
Frequency chirping is also a result of direct modulation of a laser. Chirping refers
to the phase modulation that accompanies the direct amplitude modulation of a
semiconductor laser. A time-varying phase is equivalent to transient changes in the
mode frequency from its steady-state value [12]. This results in the pulse having a
broader spectrum and therefore having more pulse spreading due to dispersion as it
travels down the fiber.
CHAPTER 2. BACKGROUND THEORY
20
The optical field of the laser output is given by
E(t) =
p
p(t)ej(ωo t+φpn (t)+φchirp (t))
(2.1)
where p(t) is the envelope of the signal, ωo is the carrier frequency, φpn (t) is the
phase noise of the laser and φchirp (t) is the chirp [13]. Laser chirp is defined by [12]
1 dφchirp (t)
1
1
∆ν(t) =
=
α Γgo (N (t) − No ) −
2π
dt
4π
τp
(2.2)
where α is the linewidth enhancement factor, Γ is the optical confinement factor,
go is the gain coefficient, N(t) is the instantaneous electron density, No is the electron
density at transparency, and τn is the electron lifetime [13]. All of these values are
physical properties associated with the active region of the laser. From equation 2.2
it can be seen that as the electron density N(T) increases, the amount of chirp on
the signal increases. For a directly modulated laser this indicates that the optical
frequency increases at the leading edge of a pulse, while it decreases at the trailing
edge of a pulse.
The implications of chirp come into play as the optical signal is propagated down
a fiber. As an optical signal travels down a fiber, different frequency components
travel with different phase velocities. Laser chirp causes the optical signal to have
more frequency content than is intended, which in turn causes the various frequency
components to arrive at the receiver at different times. This delay between frequency
components causes the pulses to spread as they propagate down the fiber introducing
ISI at the receiver.
21
CHAPTER 2. BACKGROUND THEORY
2.3.3
Thermal Effects
The output power of a semiconductor lasers is greatly effected by temperature. As
temperature increases Ith increases, as does the required drive current for a desired
output power. An example of L-I curves are shown in Figure 2.8 where T1 <T2 <T3 .
The threshold current is found to increase exponentially with temperature shown in
equation 2.3 [12], where I0 is a constant and T0 is a characteristic temperature used
to express the sensitivity of the threshold current.
T1
T2
T3
Optical Power
(mW)
Ith1
Ith2
Ith3
Drive Current (mA)
Figure 2.8: Temperature Effects on Ith and Optical Output Power for a Laser Diode
Ith (T ) = I0 exp
T
T0
(2.3)
Typically in a InGaAsP laser T0 is in the 50-70 K range, while GaAs have a T0
of 120 K and are less sensitive to temperature variations.
From Figure 2.8 it can also be seen that the slope efficiency of the laser decreases
as temperature increases. This has a two fold effect. First, it means the laser driver
must have variable bias and modulation currents. The bias current must adjust to be
greater than IT H , as well the modulation current must increase as the slope efficiency
CHAPTER 2. BACKGROUND THEORY
22
decreases to maintain the same optical power. An example of this phenomena is
shown in figure 2.9. If a given driving current is applied to a laser diode at two
different temperatures, different optical output powers are achieved. To combat this
effect, a feedback system is typically used. It will be discussed in Chapter 3.
2.3.4
Turn-on Delay
When a laser is switched on from a level below IT H the optical signal is delayed by
the time required for carrier density to reach its threshold value. Photon generation
in the active region begins as spontaneous emissions; due to the randomness of this
mechanism the turn on delay experiences variations. This induces a delay between
the drive signal and optical signal. The effects of variable turn-on delay can be viewed
in Figure 2.10 [11]. If the laser is operated in this manner, the variable delay will
induce jitter on the optical signal. To eliminate this delay in a digital system the
laser is typically biased above its threshold for a 0. This degrades the extinction ratio
(ER) of the optical signal, however, it will improve rise and fall times.
2.4
GPON Performance Metrics
To ensure the transmitter and receiver can communicate properly with each other a
strict set of standards must be adhered to. These standards ensure proper operation
of the link and reliability of the link while being stressed. The standards also allow
multiple manufacturing companies to produce products that can meet these performance goals. Increasing competition in manufacturing generally results in a lower
net cost for the end user which is desirable.
The ITU-T G984.x standard has been developed for data rates greater than 1 Gbps
and is the standard being used in this work. Table 2.2 contains important performance
metrics for the upstream optical signal.
Optical Output Power
CHAPTER 2. BACKGROUND THEORY
23
T1
P1
PAve
∆Pout for T=T1 > ∆Pout for T=T2
P0
η1
Optical Output Power
Laser Current
T2
η2
P1
PAve
P0
Laser Current
Laser Diode Input Current
Figure 2.9: Temperature Dependence of Optical Output Power for a Given Modulation Current
24
CHAPTER 2. BACKGROUND THEORY
Iin
IT H
Pout
∆T1
∆T2
Figure 2.10: Simplified Example of Variable Delay in a Laser Diode
Table 2.2: ITU-T Recommendation G.984.3 for 1244 and 2488 Mbps upstream direction [14](For furthur study(FFS))
Items
Nominal bit rate
Operating wavelength
Line code
Maximum Tx Enable
Maximum Tx Disable
Extinction ratio
Unit
Mbit/s
nm
bits
bits
dB
Single Fiber
1244.16
1260 - 1360
Scrambled NRZ
16
16
> 10
Single Fiber
2488.32
1260 - 1360
Scrambled NRZ
32
32
FFS
The ITU has yet to complete the standards for 2488 Mbps upstream transmission.
By comparing all other upstream bit rates outlined in the G984.3 recommendation,
the assumption can be made that an extinction ratio greater than 10 dBm is required.
The ER of an optical signal is defined by
ER = 10log
P1
P0
(2.4)
where P1 is the average optical power at the center of the logical “Sd1 ” and P0
is the average optical power level at the center of the logical “Sd0 ” [14]. In addition timing parameters are given to determine if the laser driver can meet the burst
mode requirements at this modulation speed. the maximum number of bits for Tx
enable/disable is 32, this corresponds to transmission enable and disable times of
25
CHAPTER 2. BACKGROUND THEORY
12.8 ns at a data rate of 2.5 Gbps. The last important piece of information to take
from Table 2.2 is the non-return to zero (NRZ) modulation format. In this format
the data stream does not return to zero between individual bits.
2.5
2.5.1
Figures of Merit
Eye Diagram
The eye diagram is a fundamental tool in analyzing the performance of an optical
system. An ideal eye diagram is shown in Figure 2.11 for a NRZ modulation format.
The eye diagram is constructed by overlaying plots of a waveform from consecutive
time intervals. The time interval is usually selected as a multiple of a bit period
which produces a shape that closely resembles the human eye. In Figure 2.11 the
time interval is three bit periods, which has produced three separate eyes.
Noise
Logic 1
Eye
Logic 0
Sample Period
Jitter
Figure 2.11: Ideal Eye Diagram of an Optical System for an NRZ Modulation Format
The eye diagram is created by driving the system with a pseudo random bit
sequence (PRBS). As signals are, in reality, random and not deterministic, a test
input signal representing this phenomenon is needed. A maximum length PRBS
signal is the best representation of random data. PRBS signals are generated with
a shift register of length N bits, where the register is tapped and fed back properly
to create a maximum length PRBS signal. The maximum length generated is 2N -1
bits long, where N is the number of registers used. Increasing the register length
CHAPTER 2. BACKGROUND THEORY
26
of the PRBS generator increases the length of the PRBS which also increases the
randomness of the data. Longer register length PRBS signals contain more frequency
components which stresses the system harder creating a more accurate representation
to reality.
The eye diagram contains detailed information about the launched optical signal.
A desirable result of a clean signal is for the eye diagram is to have a large, clear eye
opening. A poor, noisier signal will have a much smaller opening cause by noise and
jitter. The vertical direction of the eye is a measure of power, where the power of a 1
and 0 can be easily read. Noise that is present in the system will thicken the traces in
the eye diagram, which will close the eye vertically and drive down noise margins. By
measuring the thickness of the Sd1 and Sd0 traces, the associated noise can be analyzed
and evaluation of signal to noise ratio (SNR) can be performed. By analyzing the
horizontal direction of the eye diagram, some timing properties of the launched signal
may be extracted. Jitter will manifest itself in the eye diagram through a broadening
of the width of the zero crossing. Therefore jitter measurements can be taken from
the width of traces at the corner of the eye. Finally, the rise and fall times of the
signal can be measured by examining the transition time from the bottom to top and
top the bottom.
2.5.2
Eye Mask
The eye mask is a tool used with the measured eye diagram to determine if the laser
driver will meet the requirements of the intended system. Standards associations such
as the ITU will create an eye mask for given transmitter data rates. The eye mask
for the GPON standard can be seen in Figure 2.12 and the associated levels can be
viewed in Table 2.3. The mask is created based on the maximum amount of signal
noise, jitter, and power level that the system can tolerate. If the eye mask can fit
inside the measured eye diagram the laser driver will be compatible with the system.
27
CHAPTER 2. BACKGROUND THEORY
It is extremely important to meet this requirement as it will guarantee that a receiver
designed to the GPON standard will be able to detect the signal and successfully
recover the data with a low bit error rate (BER).
1+y1
1
y2
0.5
y1
0
-y1
0
x1
x2
0.5
x3
x4
1
1UI
Time
Figure 2.12: Eye Diagram Mask
Table 2.3: Eye Mask Properties for Transmitted Upstream Optical Signal. ITU-T
recommendations G.957, G984.2 and G.987.2 [14]
x3 - x2
y1/y2
x2/x3
2488.32 Mbps
0.2 UI
0.25/0.75
Need not to be equidistant from 0UI and 1UI
Chapter 3
Literature Review
3.1
Introduction
Chapter 2 has provided background information that must be considered for modulating a laser diode at high data rates. The focus of this thesis is the design of the
laser driver stage that would be a key component in an upstream PON burst-mode
transmitter (BM-Tx). The upstream transmitter at an ONU consists of three critical
blocks; the laser diode, the laser driver stage and the APC feedback circuit. The
following discussion will cover the relevant work performed to date on upstream high
speed CMOS PON BM-Txs.
3.2
CMOS Burst-Mode Transmitters
The following works were selected as they reflect the current state of CMOS burst
mode laser drivers for PONs. The literature pertaining to CMOS burst mode laser
drivers is relatively limited, and the works presented here cover the field as a whole
from past to current state.
One of the earliest pieces of research in burst mode laser driver design was performed by E. Sackinger et al. [15]. This work is implemented in 0.5 µm digital
28
29
CHAPTER 3. LITERATURE REVIEW
CMOS, designed to operate at 155 Mbps for APON. The block diagram is shown in
Figure 3.1. The circuit accepts either a low-voltage CMOS or LVPECL input. The
data is pre-distorted by the turn-on delay compensation (TODC) block before driving
the LD with the laser driver stage (LDS). This allows for compensation of the laser
turn on delay, and allows for operation without a bias current. The signal from the
monitor photodiode is fed back into the peak comparator (PC), which compares the
photodiode peak current with a reference value. The digital section (DIG) digitally
controls the on-current of the LDS and also provides end-of-life (EOL) alarm. The
laser diode is DC-coupled to the laser driver IC to avoid the slow response introduced
by AC-coupling.
Delay
Comp.
Set
Power
EOL
Alarm
PD
LD
Laser Driver IC
P
Frame
P
Overhead
P
C
C
TODC
CLK
Data
LDS
DIG
R
PC
C
P/C
PECL to CMOS Converter
TODC Turn-On Delay Compensation
LDS
Laser Driver Stage
PC
Peak Comparator
DIG Digital Block (Counter)
CLK Clock Generator
Figure 3.1: Block Diagram of the Laser Driver IC from [15]
Figure 3.2 shows the conventional and implemented block diagrams for burst mode
APC. The conventional implementation is shown in Figure 3.2a, the photodiode current signal is converted to a voltage signal and its peak value is detected. The current
of the laser is adjusted until the peak voltage reaches a desired value VREF . To implement this, the current-to-voltage (I/V) converter and peak detector must operate
at bit-rate speed, and consume a significant amount of power. An alternative to
30
CHAPTER 3. LITERATURE REVIEW
this configuration is shown in Figure 3.2b. This APC circuit operates in a burst-byburst fashion rather than a bit-by-bit basis and therefore does not require fast and
power-hungry circuits [15].
LD
Data
PD
Driver
IP D
−
Peak
Detector
+
I/V
VREF
(a)
VDD
LD
Data
Driver
PD
CP D
IP D
Up Down u/d
Counter
clk
+
−
clk
VP C
reset
data
IREF
(b)
Figure 3.2: Burst Mode Power Control Block Diagram (a) Conventional, (b) LowPowered Used in [15]
The purpose of this circuit is to equalize the peak value of the photodiode current
IP D to the reference current IREF . The parasitic photo diode capacitance is used as
an integrator and is pre-charged to a known voltage VP C during the first burst. In the
following bursts, the capacitance is charged up by the current from the photodiode
iP D and simultaneously discharged by current pulses generated by the data switch and
the reference current source IREF . At the end of a burst, the voltage on the capacitor
is compared to the pre-charged voltage with a clocked comparator. Depending on the
result, a counter controlling the laser output power is stepped up or down. As the
selected power level is stored by a digital up/down counter, its hold time is infinite.
The counter is updated in between bursts to avoid disturbance of the transmitted
31
CHAPTER 3. LITERATURE REVIEW
data. When compared to the conventional method, the burst-by-burst method adapts
more slowly. However, the change in output power due to temperature changes and
aging should occur slowly, making this adaptation relatively fast [15].
The implemented peak comparator circuit is shown in Figure 3.3. Devices M1 and
M2 constitute a current mirror that replicates IREF at the drain of M2 . The CMOS
switch S1 modulates this current before injecting it into node x. The gate voltage
of the current mirror is also used as recharge voltage VP C and applied to node x
by means of reset switch S2 . The remaining transistors form a clocked comparator
discussed in [16].
VDD
res
IREF
clk
clk
PD
CP D
S2
X
out
eol
res
eol
dat
M1
S1
dat
clk
clk
M2
M1A
Figure 3.3: Peak Comparator Circuit [15]
The chip consumes an area of 2.7 x 2.2 mm2 and operates on a 3.3 V supply
voltage. Measured results were presented for a 155 Mbps burst with a LVPECL
PRBS (223 -1) input to the laser driver. Electrical and optical results were presented.
The laser driver achieved an optical rise/fall time of 0.8 ns and peak-to-peak optical
jitter of 0.3 ns while consuming 15 mW of power (without laser). APC had been
tested by measuring the optical output power while heating and cooling the chip and
laser.
CHAPTER 3. LITERATURE REVIEW
32
In addition to Sackinger’s work, a more recent piece of research was performed
Oh et al. [17], which targets the ITU-T 1.25 Gbps upstream GPON standard. Figure
3.4 shows the block diagram for the laser diode driver, which is an updated version
of earlier works [18, 19, 20].
This work uses analog circuit techniques based on conventional feedback, to control
the bias and modulation current simultaneously. The feedback is based on separating
the monitor photo diode (MPD) current into two independent paths. The laser
driver stage consists of two differential pairs, each biased by a tail transistor sinking
the laser bias and modulation current according to their respective control voltages
ABC ctrl and AMC ctrl. This allows for fast turn on/off times, however, increases
power consumption.
While in burst mode operation, there is no stable average power available and no
power is transmitted between bursts. Therefore, the stabilizing method by variation
of the average photo-current makes it difficult to keep a constant laser operation
in the real burst-mode environment. A transmission enable (TX enable) signal was
used as a reset mechanism to overcome this. The laser diode was DC coupled to the
transmitter in order to get an instantaneous response at the beginning of each high
speed input burst.
For controlling the modulation and bias power, a photocurrent from the MPD is
injected into the high-speed transimpedance type I/V converter. Two single-ended
outputs of the converter retrieve the bias and modulation factors, with VM OD and
VBIAS . During a burst, the peak detection circuit captures and maintains the peak
levels of these two voltages. Each peak voltage is then compared with the reference
that is externally controlled and sets the initial bias and modulation power of the
laser diode. As temperature increases, the lower photocurrent is fed back into the I/V
converter due to a decrease in optical output power. This feedback current generates
increased peak voltage for VBIAS and reduces peak voltage for VM OD . The difference
33
CHAPTER 3. LITERATURE REVIEW
between the captured level by the peak detection circuit and reference level provides
the regulated control voltage at the gate node of the current source transistor in the
laser driving stage. Finally, the feedback loop adjusts the bias and modulation current
driven into the laser diode such that it matches a predefined reference. Therefore,
in this architecture, once the reference voltages of the ABC and AMC circuits are
determined on the outside, the initial bias and modulation currents for the constant
laser output power and ER are automatically installed. The transmitter does not
require any other adjustments except setting the initial laser power and extinction
ratio [17].
RD
DAT A
I/V
Laser
Driver
TX enable
AMC ctrl
ABC ctrl
VBIAS
T X enable
Q
Q
REF1
ABC
QQ
VM OD
DATA
IP D
Top
Holder
Reset creation
circuit
Q
Bottom
Holder
AMC
Q
Q
Q
REF2
Figure 3.4: Burst-Mode Upstream Transmitter with APC Block Diagram [17]
Figure 3.5a shows the simplified laser driver schematic from this work. To achieve
proper DC bias and 50 Ω input matching, the high speed input signal is DC-coupled
to the laser driver through a simple resistive divided LVPECL interface. The predriver is a differential cascode with a source follower buffer. It drives a differential
pair which steers current to or from the laser diode. The magnitude of the modulation
current is controlled by the voltage on the tail transistor of the differential pair. A
34
CHAPTER 3. LITERATURE REVIEW
damping resistor RD is used to make an impedance matched stable load for the laser
driver.
Figure 3.5b shows the peak detection circuit. For burst-mode operation, the circuit
is reset before each input burst. Using the rectifying diode and hold capacitor, the
hold level is fed back in to the negative input of the main cascode amplifier through
the source follower to make a unity gain feedback loop. Detailed operation of the
peak detection circuit is discussed in [21].
LD
Ibias2
RD
TX enable
T X enable
DATA
DAT A
AMC ctrl
ABC ctrl
(a)
VDD
Input
Vbias
Output
Ibias
resetnmos
GND
(b)
Figure 3.5: (a) Simplified Laser Driver Schematic, (b) Peak Detection Circuit (Top
Holder) [17]
This design was fabricated in 0.18 µm CMOS and tested in a chip-on-board (COB)
configuration with a FP laser diode. A power consumption of 200 mW (not including
35
CHAPTER 3. LITERATURE REVIEW
laser diode current) is dissipated in an area of 1.2 x 1.2 mm2 using a single 3.3 V
power supply. Eye diagrams were obtained by providing the input with a 1.25 Gbps
input burst with 215 -1 PRBS data pattern and 32 bits of guard time between burst
packets. An ER of greater than 12 dB, 8 ns rise/fall time and 2 dBm average power
was achieved. Another BM-Tx will now be discussed which operates at a higher bit
rate.
The third work discussed in depth was performed by Li et al [22]. This work
describes a 10 Gbps burst-mode/continuous mode laser driver with dual loop currentmode APC in 0.18 µm CMOS. The block diagram of this driver is shown in Figure
3.6.
IP D
IDGCFN
CDG
Q2
R2
R1
C1
1.8V R2
CDG
1.8V
Q2
R1
BEN
C1
Vth Bottom
Detector
IBIAS
Q1
+
Q1
Data from
Pre-driver
RGC-TIA
−V
L Bottom
Detector
xK
BEN
+
IM OD
−
(1)
(2)
(3)
(4)
(5)
Σ
−V
H Peak
Detector
+
RGC-TIA
VL = R×Rf ×P0 +Vth
VH = R×Rf ×P1 +Vth
VL -Vth =∆V
(VH -VL )/(VL -Vth )=K
ER=P1 /P0 =(VH -Vth )/(VL -Vth )=K+1
Figure 3.6: Laser Driver schematic from [22]
The gain stage of the laser driver is a differential cascode. The cascode employs an
intrinsic drain-gate capacitance feedback network (IDGCFN) which was reported in
[23]. In the typical cascode configuration, Q2 sustains most of the voltage swing due
to the fixed gate voltage. With IDGCFN, the output signal swing is shared between
both transistors Q1 and Q2 in proportion to their breakdown voltages. To generate
a higher output swing, Q2 should be implemented as a high voltage device and Q1 as
36
CHAPTER 3. LITERATURE REVIEW
a low voltage device to reduce the Miller Effect. The key in this design concept is to
properly control the voltage at Vg2 . The resistive feedback network provides the low
frequency drive control, while the capacitive feedback provides the high frequency
part
The APC works as follows. The high and low optical power level, P1 and PO , are
related to the detected levels, VH and VL as (1) and (2) in Figure 3.6, with R the
responsivity, Rf the gain of the regulated-cascode TIA (RGC-TIA) and Vth the offset
level when there is no photodiode (PD) current (Iof f = 0). The idea is to convert the
detected voltage levels into currents and make use of C1 and C2 to implement (3)
and (4) to control IBIAS and IM OD , respectively. ∆V in (3) is a reference value. From
(5), the ER (=K+1) could be independent of process and temperature variations, if
K is implemented by a CMOS current mirror.
Figure 3.7a shows the RGC-TIA with the monitor PD modeled as a parasitic
resistance, a capacitor and a current source. Figure 3.7b shows the voltage-to-current
(V/I) converter used in this work.
1:k
Vref
Vout
KIout
Vin
Iout
CP H
RP D
IP D
Monitor PD
(a)
(b)
Figure 3.7: (a) TIA, (b) V/I converter [22]
The design consumes a layout area of 1038x1040 µm2 and uses power supply rails
of 1.8 and 4.5 V. The driver can supply a modulation current of 20-100 mA and a
CHAPTER 3. LITERATURE REVIEW
37
bias current of 0-80 mA. Peak to peak jitter of 6.23 ps and random jitter of 0.93 ps
was measured using a K28.5 pattern. A 20/80 rise time of 28ps and fall time of 29
ps was achieved in this work. A laser turn on time of less than 3ns was reported. A
power consumption of 0.54 W was reported while operating with a bias current of
25 mA and modulation current of 68 mA.
Li et al. has performed additional research described in [24]. This paper describes
the design of a 3.5 Gbps burst-mode laser driver with APC fabricated in 0.25µm
CMOS. The driver works under a single 3.3 V supply without sacrificing output
headroom. The driver supplies 6 mA to 60 mA modulation current and 0mA to 80mA
bias current. The driver IC consumed 145 mW at 3.3 V supply voltage. Measurements
show electrical eye diagrams operating over a 3.5 Gbps data rate with rise/fall times
(20% to 80%) of 94/97 ps. An optical eye diagram was also demonstrated with a
laser diode operating at 1.25 Gbps. The laser turn on/off time was approximately
30/20 ns.
The last work that will be discussed in depth is a burst mode laser driver presented
in [25]. This work targets the new 10G-EPON standard, IEEE Std. 802.3av. The
10 Gbps burst mode laser driver block diagram is shown in Figure 3.8. The optical
power control system in this work consists of a TIA, a peak detection circuit, a microcontroller, an analog-to-digital converter (ADC) and a two-channel digital-to-analog
converter (DAC). The output voltage of the peak detection circuit is sampled by an
ADC, while the bias current and the modulation current are adjusted by the output
voltage of a two-channel DAC.
Simplified schematics of the burst-mode modulation and bias schematic are shown
in Figures 3.9a and 3.9b, respectively. Pseudo current mode logic (PCML) compatible
differential inputs DATA/DAT A are pre-amplified by a standard 3-stage differential
amplifier which drives a switch mode differential pair at the output. For burst mode
operation, a burst enable signal BEN a/BEN a is used to control an nMOS and
38
CHAPTER 3. LITERATURE REVIEW
VCC
LDD Chip
DATA
DAT A
Modulation Circuit
M OD
MOD
Bias Circuit
BIAS
BEN
BEN
VCC
BIAS
Peak Detection
Circuit
Modulation
SET
DAC
TIA
MONITOR IN
Bias
SET
ADC
On the
Demonstrate Board
Micro-controller
Figure 3.8: Burst-Mode Laser Diode Driver Block Diagram [25]
39
CHAPTER 3. LITERATURE REVIEW
pMOS transistor, which are inserted between the first and second stage of the differential amplifier. When BEN a is high, the output stage sinks modulation current
according to the setting on MOD SET via the MOD output which connects to the
anode of the laser diode. This allows the current through the laser to follow the DATA
signal. When BEN a is low, current is sinked through the M OD output which connects to VCC . Therefore, regardless of the DATA input, the MOD output does not
follow. This control signal allows for fast burst-mode switching.
VCC
BEN a
M OD
MOD
DAT A
DATA
BEN a
MOD SET
(a)
VCC
BEN a
BEN a
BIAS BIAS
BEN
BEN
Bias SET
(b)
Figure 3.9: (a) Simplified Burst-Mode Modulation Circuit Schematic, (b) Simplified
Burst-Mode Bias Circuit Schematic [25]
A differential bias circuit is also used in this design. While using a conventional
40
CHAPTER 3. LITERATURE REVIEW
single ended transistor for biasing, the bias control voltage can be lowered below Vth
to cut off the bias current. However, the RC constant is large. Therefore a short
switching delay is difficult to achieve [25].
The bias circuit is shown in Figure 3.9b, which is very similar to the modulation
circuit. The PCML compatible differential burst enable signals BEN/BEN are preamplified by a two stage differential amplifier to meet the needs of the switched mode
output stage. The two inverters act as buffers for the BEN a/BEN a signals which
control the modulation circuit. The magnitude of the bias current is controlled by
the Bias SET control voltage on the tail transistor of the differential pair.
A simplified schematic of the peak detection circuit is shown in Figure 3.10. This
configuration takes advantage of the weak inversion (or subthreshold) operation of
MOS transistors.
VCC
OpAmp
Startup
Circuit
Output
M1
Input
C
M2
ISS
Figure 3.10: Simplified Peak Detection Circuit Schematic [25]
This circuit has been implemented in 0.18µm CMOS and simulation results have
been presented. The circuit operates under a 1.8 V supply voltage while consuming
76 mA at 1.8 V. It is able to supply a modulation current of 35 mA and a bias current
of 2-20 mA up to a data rate of 10.3125 Gbps. It consumes a total area of 575 µm
by 675µm. The model for the laser diode used in simulation was never discussed.
41
CHAPTER 3. LITERATURE REVIEW
Some additional works will now be briefly discussed.
The first to be discussed is the design of a 2.5 Gbps laser driver in 0.18 µm
CMOS operating with supply voltages of 1.8 V and 3.3 V [26]. The circuit is able to
provide bias currents from 2-30 mA and modulation currents of 2-20 mA. The rise
and fall times are both 300ps. The design takes up 1 mm2 area and the core power
consumption is 90 mW. The device also features burst mode operation. The laser
driver accepts a PECL voltage input. The pre-driver consists of a chain of differential
amplifiers. The number of stages has been optimized such that the required gain
bandwidth was reached. Figure 3.11 shows the schematic of the output stage. The
single AND and NOR gates provide the logic for implementing burst mode.
The circuit was directly bonded to a printed circuit board (PCB) board for testing.
Tests were performed with a PRBS input of 215 -1. An RC network was implemented
in the path of the laser diode to reduce the overshoot of the eye diagram. Due to
the large currents and fast switching, the parasitic inductance was causing overshoot
in the eye diagrams. The RC network had been adjusted to sufficiently reduce the
overshoot.
OUT
INBEIN+
BE+
Modulation
Bias
Figure 3.11: Laser Driver Output Stage Schematic [26]
Additionally, a 2.5 Gbps laser driver was designed in 0.35 µm digital CMOS [27].
CHAPTER 3. LITERATURE REVIEW
42
To overcome the low transconductance of the CMOS device, the circuit implemented
uses preamphasis and inductive peaking. The reported bias current ranges from 510 mA and a modulation current of 20 mA. The circuit operates under a single 3 V
supply and consumes a maximum power of 150 mW. The chip size is 1200 µm x
900µm.
The input to the laser driver is a PECL signal at approximately 300 mV. This
is amplified the preamplifier to drive the current modulator. To drive the highly
capacitive current modulator, the preamplifier is composed of 4 differential pair gain
stages with inductive loads. The inductive loads are implemented as active inductors.
Simulation was performed by modeling the laser diode as a 50 Ω resistor. To
acquire measurements a vertical cavity surface-emitting laser (VCSEL) diode was
directly attached to a PCB board along with the chip. The input for testing was a
223 - 1 PRBS signal at PECL level. The eye opening of the measured diagram met
the OC48 mask.
Finally, a 1.25 Gbps laser driver was fabricated in 0.18µm CMOS for burst-mode
PON[28]. The laser driver consists of a modulation amplifier, APC and bias amplifier.
The modulation amplifier consists of a two stage cascade of amplifiers. The first
stage offers low gain but maximizes bandwidth. It is composed of a differential pair
loaded with active inductors. The active inductor uses a gyrator topology. A source
follower buffer is also used in the first stage. The second stage uses the same topology
as the first stage however, offers a high gain in a limited bandwidth to supply 40 mA
of current to the laser.
The circuit was measured using on-wafer probing and on-board test. Small signal
S-parameters were measured and a DC gain of 17 dB was reported with a -3 dB
bandwidth of 2.49 GHz. The output swing is about 1.5 Vp-p which is enough to
driver a typical laser diode. No rise or fall times were reported, or eye diagram
measured.
CHAPTER 3. LITERATURE REVIEW
43
The research presented in this chapter has been critical in the work performed in
this thesis, which will be presented in the next two chapters.
Chapter 4
2.5 Gbps Laser Driver Design
4.1
Introduction
This chapter presents the design, simulation, fabrication and measurements of a
2.5 Gbps laser driver stage with adjustable bias and modulation currents designed to
meet the requirements of the 2.5 Gbps upstream GPON specification in Table 2.2.
Based on the literature review presented in chapter 3, a pseudo differential topology
was chosen for the LDS design. This minimizes the switching noise in the LDS and
results in less jitter in the transmitted optical signal. The laser driver was designed
to operate with low voltage differential signaling (LVDS).
4.2
Design Goals and Assumptions
The laser driver was designed without a specific DFB laser diode in hand. Additionally an electrical model of a laser diode was also unavailable in the simulation
suit. Implementations of laser diode models based off of the coupled laser rate equations are possible, however, they require intimate knowledge of the device fabrication
details which manufactures are reluctant to divulge. Therefore, some design assumptions were made for modeling the laser diode to allow simulation. Design goals were
44
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
45
also set to ensure the laser driver could operate with a typical DFB laser diode. The
following section outlines assumptions that were made to proceed with the design of
the laser driver.
The typical series resistance of the active region of a laser diode is in the range of
4-7 Ω [29]. Modeling the impedance of the laser diode as a purely resistive component
is an ideal approximation as there will also be some additional parasitic capacitance
present. However, due to the size of the output transistors in the laser driver and
their large capacitance the relatively small parasitic capacitance of the laser diode
would have minimal effect. Therefore, a resistive model was used.
As discussed in chapter 3, a dampening resistor is typically inserted in series with
the laser diode to eliminate current overshoot and undershoot due to the parasitic
inductance associated with bond wires and laser diode packaging. Therefore, it was
assumed that an off chip dampening resistor with a value of 43-46 Ω could be placed
in series with the laser diode to effectively make the laser diode appear as a 50 Ω load.
The selection of this dampening resistance also sets the characteristic impedance of
the transmission lines on and off chip. This is important to note as the width of the
transmission lines are directly related to the characteristic impedance. Therefore, the
laser diode was modeled as a purely resistive 50 Ω load for simulation purposes.
Modeling the laser diode this way ignores the forward voltage drop associated
with the laser diode, parasitic effects of the bond wires, laser packaging, and parasitic
capacitance of the laser diode active region.
Having selected a laser diode model for use in simulation, design goals were set
for the modulation and bias currents. A review of 2.5 Gbps DFB laser diode data
sheet [29] revealed that the typical DFB laser diode has a threshold current in the
range of 9-50 mA. Additionally, a modulation current of 30-60 mA was needed to
meet the required extinction ratio set out in the GPON standard. These design goals
are summarized in Table 4.1.
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
46
Table 4.1: 2.5 Gbps Laser Driver Design Goals
Modulation Current
Bias Current
4.3
0-60mA
0-50mA
Output Stage Topology - CMOS Differential
Pair
As discussed in section 2.3, the optical output power of a laser diode is exponentially
related to the current injected into the laser’s active region. A CMOS differential
pair, which is also known as a source coupled pair, may be used as a current switch.
This arrangement provides low jitter, small turn-on delay, low power-supply noise,
and differential inputs [15]. This makes it an ideal topology for the output stage of
the laser driver. Another alternative for the output stage is the differential cascode.
The cascode would require a larger supply voltage and consume more power than the
differential pair. It also does offer increased performance through the reduction of
the miller capacitance. However, it was determined that the differential pair could
meet the performance requirements at 2.5 Gbps and it was selected as the topology
for the outputs stage. This decision is reflected in the research presented in section
3.2 where similar drivers operating at this data rate implement their output stage as
a differential pair.
Figure 4.1 shows the schematic of a differential pair. The sources of transistors
Q1 and Q2 were connected together and were biased from a current source (I). With
equal bias voltages (VBIAS ) on the gates of Q1 and Q2 , the current I splits equally
between Q1 and Q2 , biasing the transistors. The source connection of Q1 and Q2 can
now be considered an AC virtual ground. With appropriate drain and gate voltages,
the differential pair may act as a current switch.
The following voltage levels will be defined where vCM is the common mode input
voltage, vid is the differential input voltage and vGS1 /vGS2 are the gate to source
47
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
iD1 =
I
2
+ iid
iD2 =
Q1
vid
I
2
vGS1 = VBIAS +
Q2
vGS1
- iid
vGS2 = VBIAS -
vGS2
vid
2
vid
2
I
Figure 4.1: CMOS Differential Pair
voltage for Q1 and Q2 respectively.
vid
2
vid
−
2
vGS1 = VBIAS +
(4.1)
vGS2 = VBIAS
(4.2)
vid = vG1 − vG2
(4.3)
vcm = vG1 + vG2
(4.4)
In the event the input to the laser driver would be the rising edge of a 1, vGS1 would
be presented with a positively increasing vid . vGS1 would increase while vGS2 would
decrease. This increases iD1 while decreasing iD2 . Throughout this whole process iD1
and iD2 sum to the bias current I. When the voltages at vGS1 and vGS2 experience a
transition from a 1 to a 0, vGS2 would increase while vGS1 decreases. The current iD2
would then increase while iD1 decreases. This property allows for the differential pair
to act as a current switch. The individual arms of the differential pair can potentially
switch from 0-I mA if they are provided with enough differential input voltage and
enough head room.
Due to the magnitude of the required modulation current, the differential pair will
be driven with a large signal. Therefore the small signal approximations usually used
48
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
while working with transistors will not always be valid. The following will discuss the
large signal operation of the differential pair.
4.3.1
Large Signal Operation
The large signal expression for the drain currents iD1 and iD2 will be discussed in terms
of the input differential signal vid . The load of the differential pair can be ignored for
the time being if the following assumptions are made: the circuit maintains Q1 and
Q2 out of the triode region of operation at all times, the differential pair is perfectly
matched, there is no channel-length modulation (λ=0) and no body effect [30]. Since
this example is for illustrative purposes the simple long channel approximations will
be used in this analysis. The equations for the drain currents while Q1 and Q2 are
biased at the quiescent point (vid =0, vG1 = vG2 = VBIAS ) are as follows [30],
iD1
I
= +
2
iD2
I
= −
2
I
vid 2
vid 2
VOV
I
VOV
s
1−
s
1−
vid /2
VOV
2
vid /2
VOV
2
(4.5)
(4.6)
where
I
1 W
1 W 2
= kn0
(VGS − Vt )2 = kn0
V
2
2 L
2 L OV
(4.7)
where I is the bias current, W the transistor width, L the transistor length, k’n a
constant that is technology dependent, Vt is the threshold voltage of the transistor
and VOV is the overdrive voltage (VOV = VGS - Vt = VBIAS - VS - Vt ). These two
equations describe the large signal effect of applying a differential input signal on the
currents iD1 and iD2 . A normalized plot of these equations are shown in Figure 4.2
49
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
1
0.9
iD1
I
Normalized Drain Current ( iId )
0.8
iD2
I
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
−1.5
−1
−0.5
0
0.5
1
1.5
id
Normalized Differential Input Voltage ( VvOV
)
Figure 4.2: Normalized Plots of the Currents in a CMOS Differential Pair
These normalized results contain valuable information. First, it can be noted from
Figure 4.2 that the current I is entirely steered into Q1 when vid reaches the value
√
2VOV [30]. For Q2 , the entire current I is steered into it when vid reaches the
√
√
value of - 2VOV . Therefore, a differential input of ± 2VOV is needed to fully switch
current I between both arms of the differential pair. This is a significant result as it
allows for a design target to be set for the voltage output swing of the pre-amplifier.
Ideally, the LDS would provide a large current. There is however, a trade-off as
the current I is increased. From Equation 4.7 there are two options available to the
designer to increase current I. First, VOV can be increased. To increase VOV the gate
bias voltages of the differential pair transistors must increase. Increasing the drive
current using this method will place greater demand on the pre-amplifier as it will
require an increased differential swing into the differential pair for full switching. The
second option is to increase
W
.
L
Increasing the width to length ratio of the transistors
in the differential pair will increase both the input and output capacitance. The
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
50
dominant pole restricting the bandwidth of the laser driver stage is typically at the
input to these large transistors. Therefore, there is an upper limit to the size of these
transistors due to bandwidth requirements.
This information was critical in the optimization of the differential pair. The
following will discuss the design of the pre-driver designed for the LDS.
4.4
Pre-Driver Topology
Having selected an appropriate output stage for the laser driver, a pre-driver was
required to amplify the input LVDS signal to the voltage level required for driving
the differential pair. The input LVDS voltages are listed in Table 4.2, where VCM is
the common mode voltage, VH is the voltage level of a 1 and VL is the voltage level
of a 0.
Table 4.2: LVDS Volage Levels
VCM
VH
VL
1.2 V
1.4 V
1.0 V
The LDS pre-amplifier is responsible for amplifying the small input voltage signal
to the voltage level required to fully switch the LDS output stage. Since the transistors
in the LDS output stage are very large, the pre-amplifier must also provide a large
amount of current to charge the resulting parasitic capacitance. For this reason a two
stage topology has been selected. The first stage uses small transistors to produce
the required voltage gain. The second stage uses larger transistors to provide the
required current to charge the large parasitic capacitance of the LDS output stage.
The pre-amplifier is shown in Figure 4.3.
Potential topology choices for the first stage include a differential pair and a differential cascode configuration. The differential cascode topology was selected as it
51
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
provides a lower input capacitance, resulting in a larger bandwidth than the differential pair. The differential cascode stage is followed by a source follower buffer to
isolate the first stage from the large input capacitance of the second stage.
vOU T
vIN
Stage 1
Stage 2
Figure 4.3: 2.5 Gbps LDS Pre-Driver Topology
Stage two of the pre-amplifier needed to provide enough drive current to switch
the output stage of the laser driver. This stage does not have a large DC gain
which means there is little advantage to using a cascode topology. Therefore, the
second stage was implemented as a differential pair. Diode connected transistors
were used to implement active loads instead of resistors. Active loads offer space
savings and improved tolerances. They however are nonlinear, and introduce some
additional parasitic capacitance. To meet the bandwidth requirements for the driver,
shunt inductive peaking was also used. The peaking was implemented with active
inductors in an effort to save space. The inductor is used to resonate with the large
input capacitance of the following stage. This technique is widely used to extend the
bandwidth in cascaded amplifiers.
The schematic of an active inductor is shown in Figure 4.4 [27, 31]. For Zin to
52
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
appear inductive it is required that gm1 >
1
R
[31], where gm1 is the transconductance
of Q1. To benefit from the inductive peaking, the self resonant frequency of the active
inductor should also cover the bandwidth of the pre-amplifier [27]. As an alternative
to the active inductor, a monolithic spiral inductor may have been used in the CMOS
process. Monolithic inductors are typically large, therefore, the active inductor was
used to save space which reduces cost. The drawbacks to using an active inductor
is increased voltage headroom consumption and added noise. Additionally, active
inductors are nonlinear. While under large signal operation their bias conditions
can change altering their behavior. In contrast, spiral inductors remains inductive
regardless of voltage across the device.
vg
R
R
Cgs
Gm1 (vg -vo )
Q1
Io
Zin
vo
Zin =
1+SRCgs
1
gm1 1+SCgs g 1
m1
Figure 4.4: Active Inductor
With the topology of the pre-driver chosen, final optimization with the output
current switch was then performed.
4.5
2.5 Gbps Laser Driver Design
The previous two sections discussed the topologies for the pre-amplifier and output
stage of the LDS. The two stages of the laser driver were brought together in Agilent’s
ADS and optimized. Some additional components were also added to the LDS which
53
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
enabled it to be fully functional.
The completed output stage is shown Figure 4.5. An additional transistor Q4
was included on the output arm of the LDS that would connect to the laser diode.
Transistor Q4 provided the bias current IBias , to ensure the laser remains biased
above Ith . The magnitude of the bias current is controlled with voltage VBias . A
single transistor was used to minimize complexity. A differential biasing network
could be examined in the future while designing for burst mode. A tail transistor Q3
was added to function as a variable current source to provide the modulation current
IM od . It is controlled by the voltage VM od . The two currents sum together to produce
IOut which will drive the laser diode.
Terminated Off Chip
IOut
VIN +
Q1
IBias
Q2
Q4
VBias
VIN −
VM od
Q3
IM od
Figure 4.5: 2.5 Gbps LDS Output Schematic
All transistors were laid out in deep N-wells. The deep N-wells allow the source
of the transistor to be connected directly to the body of the transistors to reduce the
body effect. 2.5 µm gate finger widths were used and gates were double connected to
reduce transistor input resistance. The transistors implemented were 1.8 V devices
which was a design oversight. The design kit used also includes 3.3 V thick oxide
devices. The implications of this choice will be discussed later in the chapter. The
54
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
final schematic of the laser driver will now be discussed.
4.5.1
Final Schematic
The final schematic for the 2.5 Gbps laser driver is shown in Figure 4.6. The driver
output operated as an open drain with the laser diode, therefore no matching network
was placed in the output. An input matching network was omitted due to design
oversight. For testing a truly differential broadband resistive matching network should
be used. In a fully implemented system matching potentially would be unnecessary
as most of the electronics would be integrated and the proximity of devices would be
close enough to ignore transmission line effects.
I2
RD1
RD1
M1 M1
M1
M1
RD2
RD2
M1
M3
M3
M3
M3
M3
M3
Terminated Off Chip
M4
IN+
M1
M1
M1
I3
M4
M4
I3
M2
M2
IN−
M4
VM od
I1
I4
Figure 4.6: 2.5 Gbps LD Final Schematic
Table 4.3: 2.5 Gbps LDS Component Values
Transistor Sizes
Component
M1
M2
Value (2.5 µm Fingers)
4
20
Resistor Values
Component
Value
Current Source Values
Component
I1
I2
Value
0.9 mA 1.4 mA
M3
60
M4
120
RD1
1.85 kΩ
RD2
400 Ω
I3
2.16 mA
I4
10 mA
VBias
55
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
Table 4.3 contains the component values used including transistor sizes, resistor
values, and bias current values for each stage. Current sources were implemented
using current mirrors, which were omitted from Figure 4.6. Figure 4.7 shows the
topology used for the nMOS and pMOS current mirrors which were omitted from
Figure 4.6.
Rbias
Iout
Iout
Rbias
(a)
(b)
Figure 4.7: Current Mirrors (a) nMOS (I1 ,I3 ,I4 ), (b) pMOS (I2 )
The final 2.5 Gbps LDS was laid out in 0.18 µm CMOS. The final layout can be
seen in Figure 4.8. The layout is as symmetrical as possible, which is important in
a differential design for noise rejection. Even though the output is single ended, the
differential layout aided in rejecting common mode noise through the pre-amplifier.
Metal-insulator-metal (MiM) capacitors were also used to provide decoupling to the
DC lines. They were placed as close as possible to the transistors they were biasing.
This provided the transistors with a more stable AC ground. Additional probing pads
were placed in the layout to provide substrate connections. These connections could
be used to measure the coupled substrate noise injected into the substrate by the
laser driver. The layout consumes an area of 0.8 x 0.7 mm2 . The completed layout is
shown in Figure 4.8.
56
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
Substrate contacts
VIN −
VIN +
VOU TDummy
VOU TLaser
Substrate contacts
VM od VDD VCC VBias
Figure 4.8: Layout of 2.5 Gbps CMOS Laser Driver Stage
4.6
Simulation Results
Upon layout completion it is extremely important to confirm the circuit is still meeting the desired design parameters. Post layout simulations were performed to ensure
the circuit’s performance under the influence of layout parasitics. Cadence was used
to extract the parasitic capacitance associated with the layout, excluding the input
and output transmission lines and pads. The altered layout is shown in Figure 4.9.
The fully extracted layout was then imported into Agilent’s Advanced Design System
(ADS) via the ADS dynamic link from Virtuoso. The transmission lines and pads
were imported into Agilent’s Momentum simulator. This was used to perform electromagnetic (EM) simulations to model their parasitic effects. Ports were placed on
the pads and at the ends of the transmission lines where the active components could
be connected and co-simulation performed. The momentum simulation setup can be
seen in Figure 4.10.
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
Figure 4.9: Altered Layout for Extraction
Figure 4.10: Momentum simulation setup for top metal layer
57
58
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
To compare the schematic versus extracted layout an identical test bench was
set up in ADS, shown in Figure 4.11. The differential input signal was provided
by the VtPRBS component in ADS. This component provides a pseudo random
bit sequence (PRBS) voltage source with a variable register length. Using a longer
register length increases the randomness of the input signal, which represents a more
accurate representation of how the driver would operate in the field. However, due
to the nature of the transient simulation a register length of 8 was chosen to produce
simulation results in a reasonable amount of time, and to limit the size of the resulting
data files. A PRBS signal with a register length of 8 will begin to repeat itself after
102 ns, therefore, all simulations were performed for this length of time.
50Ω
VDD
PRBS
Laser Driver
50Ω
Iprobe
VM OD
VBIAS
Figure 4.11: ADS Transient Simulation Setup
The outputs of the laser drivers were terminated in 50 Ω to model the laser, this
assumption was discussed in section 4.2. A current probe was placed in series with
the resistor that was modeling the laser to measure the drive current. Transient simulations were then performed for the schematic, and extracted layout with parasitic.
Figure 4.12 contains the transient simulation results for the maximum achievable
modulation current. Figure 4.12a shows a single ended input of the the LVDS PRBS
signal. Figure 4.12b shows the output current for the schematic, while Figure 4.12c
shows the output of the laid out driver with parasitic effects present. For simulation
the following inputs were used: the rise and fall time of the input signal was set to
10% of the bit period (40 ps), a VDD of 3.3 V, VBIAS of 0 V and a VM OD of 1.0 V.
59
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
1.5
Voltage (V)
1.4
1.3
1.2
1.1
1
0.9
0
10
20
30
40
50
60
Time (ns)
70
80
90
100
70
80
90
100
70
80
90
100
(a)
Current (mA)
50
40
30
20
10
0
0
10
20
30
40
50
60
Time (ns)
(b)
Current (mA)
50
40
30
20
10
0
0
10
20
30
40
50
60
Time (ns)
(c)
Figure 4.12: Transient Simulation Results (a) Single ended Input Voltage, (b)
Schematic Output Current, (c) Extracted Output Current
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
60
Interestingly, the simulation with extracted parasitic achieved a higher maximum
current for the same input voltages. It was able to achieve a maximum modulation
current swing of approximately 50 mA, while the schematic simulation was operating
with a maximum swing of approximately 47 mA. Also observable in the extracted
simulation results, the driver was on the verge of having the current level of a 0 raise
above 0 mA. This indicates the driver has reached the maximum modulation current
achievable with a VM OD control voltage of only 1.0 V. This will be discussed in the
conclusions.
Figures 4.13a and 4.13b depict the voltage input and output current for the extracted layout simulation on a time scale from 70 - 80 ns. This was included to
demonstrate that the output is following the voltage input.
Finally, eye diagrams of both simulations were created and are shown in Figure
4.14. It can be observed that the rise/fall time of the extracted with parasitic simulation is slightly longer than that of the schematic. This was expected as the parasitic
capacitance of interconnects would be included in the extracted simulation. These
parasitics would increase the capacitance at critical nodes limiting the speed of the
LDS. Both results still exhibit open eyes. Based on these results it was determined
that the parasitic of the layout had minimal effect on the output current and that
the layout was ready to be fabricated.
4.7
Measured Results
Due to the limitations of the accuracy of simulation software for integrated circuits
(IC), measurements of the physical device are needed. A prototype of the 2.5 Gbps
LDS circuit was fabricated in 0.18 µm CMOS through TSMC. This process offers 6
metal layers, 1 polysilicon layer, 1.8 V and 3.3 V devices and a thick top metal layer.
A die photograph of the manufactured chip is shown in Figure 4.15.
The following section outlines the measurements performed and compares them
61
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
1.5
Voltage (V)
1.4
1.3
1.2
1.1
1
0.9
70
71
72
73
74
75
76
Time (ns)
77
78
79
80
77
78
79
80
(a)
Current (mA)
50
40
30
20
10
0
70
71
72
73
74
75
76
Time (ns)
(b)
Figure 4.13: Transient Simulation Results From 70-80 ps (a) Single Ended Input, (b)
Extracted Output Current
62
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
Current (mA)
50
40
30
20
10
0
0
100
200
300
400
Time (ps)
500
600
700
800
500
600
700
800
(a)
Current (mA)
50
40
30
20
10
0
0
100
200
300
400
Time (ps)
(b)
Figure 4.14: Simulated Eye Diagrams a) Schematic b) Extracted
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
63
Figure 4.15: Die photograph of 2.5 Gbps LDS
to extracted simulation results. To characterize the chip two measurements were
taken. S-parameter and time domain electrical eye diagram measurements were performed in the Advanced Photonics Systems Lab (APSL) at Queen’s University. All
measurements were performed using on wafer probing.
4.7.1
Small Signal Measurements
The complete four port S-parameters for the 2.5 Gbps LDS were measured using
on-wafer probing with a four port Agilent N5230A PNA-L network analyzer. Sparamater measurements are only valid while the device being measured is operating
in the linear region. 20 dB attenuators were used on the LDS inputs to ensure linear
operation. The measurement setup can be seen in Figure 4.16.
A four port short, open, load and thru (SOLT) calibration was performed as
outlined in [32] with a GGB CS-2-150 calibration substrate. The following settings
64
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
Agilent N5230A PNA-L Network Analyzer
Port 2
Port 1
Port 3
20dB Attenuator
DC PSU
Bias Tee
Bias Tee
Port 4
20dB Attenuator
DC PSU
Bias Tee
Bias Tee
Coax Cable
DC PSU
Coax Cable
Coax Cable
Coax Cable
GSGGSG Probe
GSGGSG Probe
DC Probe Array
DC PSU
DC PSU
Figure 4.16: Four Port S-parameter Test Setup
65
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
on the PNA-L were: port power was set to -30 dBm, IF bandwidth to 1 kHz and
401 measurement points were used. The validity of the calibration was confirmed by
remeasuring the calibration standards for open, short and load. The measurement
was displayed on smith chart and observed moving from the corresponding open,
short, and matched locations in a fine point. Following a successful calibration the
four port S-parameters were measured using the bias and control voltages in Table
4.4.
Table 4.4: Bias voltages for S-parameter Measurements
Voltage
Value
Vg
1.2 V
Vd
2.6 V
Vcc
3.3 V
Vdd
3.3 V
Vmod
0.5-1.8 V
Vbias
0.5 V
The measured four port S-parameters were post processed in ADS to obtain the
LDS single ended output to differential input gain. Figure 4.17 shows the ADS
simulation setup to obtain the mixed mode S21. This measurement represents how
the device would be operating in reality. Extracted layout simulations were also
performed in the same manner to compare to the measured results. Figure 4.18
contains the simulated and measured S21 plots obtained for the various modulation
voltage settings. Simulation results were obtained using the typical/typical corner
model provided by TSMC.
Table 4.5 contains the numerical measured and simulation results obtained from
the plots in Figure 4.18.
Table 4.5: 2.5 Gbps Measured and Simulated Gain and Bandwidth Results
Vmod (V)
1.8
1.5
1.2
0.9
0.7
0.5
Simulated
Gain (dB) BW (GHz)
35.639
1.397
35.748
1.384
35.823
1.372
35.146
1.422
32.000
1.422
16.796
2.133
Measured
Gain (dB) BW (GHz)
35.38
0.885
35.155
0.885
34.842
0.898
34.106
0.898
29.467
1.185
14.393
1.609
66
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
50 Ω
Port 1
Port 2
4 Port
Measured
S Parameters
100Ω
Port 1
Port 3
Port 4
50 Ω
Port 2
Figure 4.17: ADS Simulation Setup for S21
The measured gain appears to agree very will with the simulated gain. However,
there is a fair bit of discrepancy between the measured and simulated bandwidths.
One potential causes is possible the extraction method used in the 0.18 µm CMOS
process. The user only has the ability to extract either the parasitic resistance or
capacitance from the layout. The simulated gain was performed with parasitic capacitance extracted, ignoring the parasitic resistance could effect the simulated bandwidth. The measured bandwidth is also much lower than the desired bit rate, however,
this a small signal measurement. Large signal time domain measurements will now
be presented in the next section.
4.7.2
Time Domain Measurements
An attempt at integrating the 2.5 Gbps CMOS LDS chip with a commercial laser
diode was performed. A PCB board was manufactured in an effort to integrate the
CMOS chip and the laser diode. This would have allowed for chip on board testing
to be performed and the collection of optical results. However, complications were
encountered while wire bonding the CMOS chip to the PCB which are discussed
67
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
40
40
Measured
Simulated
35
35
30
30
25
25
S21 (dB)
S21 (dB)
Measured
Simulated
20
20
15
15
10
10
5
7
10
8
9
10
10
5
7
10
10
10
8
9
10
Frequency (Hz)
10
(a)
(b)
40
40
Measured
Simulated
35
35
30
30
25
25
S21 (dB)
S21 (dB)
Measured
Simulated
20
20
15
15
10
10
5
7
10
10
10
Frequency (Hz)
8
9
10
10
5
7
10
10
10
8
9
10
Frequency (Hz)
10
10
10
Frequency (Hz)
(c)
(d)
35
20
Measured
Simulated
Measured
Simulated
30
15
25
20
S21 (dB)
S21 (dB)
10
15
5
0
10
−5
5
0
7
10
8
9
10
10
Frequency (Hz)
(e)
10
10
−10
7
10
8
9
10
10
10
10
Frequency (Hz)
(f)
Figure 4.18: Measured and Simulated S21 a) Vmod = 1.8 b) Vmod = 1.5 c) Vmod
= 1.2 d) Vmod = 0.9 e) Vmod = 0.7 f) Vmod = 0.5
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
68
in appendix A. These complications limited time domain testing to the electrical
domain.
Electrical eye diagram measurements were performed to characterize the time
domain performance of the 2.5 Gbps LDS. The eye diagram measurements were performed with an Agilent digital communications analyzer (DCA), which presented the
output of the LDS with a 50 Ω load. Figure 4.19 shows the full transient eye diagram
measurement setup down to the probe level. Picosecond Pulse Labs 5545 bias tees
were used to provide DC bias voltages for the input and output of the laser driver.
Additionally, Fairchild SMA attenuators were placed at the input of the DCA. The
attenuators provided 16 dB of attenuation, which was required to adhere to the input
voltage limit of the DCA.
The electrical eye diagram measurements were AC-coupled. The output of the
LDS needed to be supplied with a bias voltage and a bias tee was required. This
restricted testing to measurements of the modulation current capabilities, as the
bias current was a DC source, and had no impact on the AC-coupled measurement.
Bias currents greater than 50 mA were obtained under DC testing. The following
measurements compare measured continuous time performance to simulated results.
First, a measurement of the voltage output of the MP1700A PRBS generator was
taken by the DCA. This was conducted so accurate comparison of simulated and
measured results could be performed. A screen capture of this measurement is shown
in Figure 4.20. This allowed for the differential input to be fully characterized in ADS
for simulation purposes. The values in Table 4.6 were recorded from the DCA and
used for simulation.
Table 4.6: Measured PRBS Characteristics Used in ADS for Simulation
Rise Time
Fall Time
Transit Reference
RMS Jitter
37.8 ps
33.3 ps
10%-90%
2.14 ps
69
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
Anritsu MP1701A
Pulse Pattern Generator
Bias Tee
DC PSU
Bias Tee
Coax Cable
Coax Cable
GSGGSG Probe
GSGGSG Probe
DC Probe Array
DC PSU
DC PSU
Coax Cable
Coax Cable
Bias Tee
DC PSU
16dB Attenuator
Bias Tee
16dB Attenuator
Agilent Digital Communications
Analyser 86100C
Figure 4.19: Transient Measurement Test Setup
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
70
Figure 4.20: Measured 2.5 Gbps input signal
Figure 4.21 contains plots of the measured and simulated differential input voltage
signals. The dotted lines are the measured results from the DCA; they form the eye
diagram from the measurement. The solid lines are the simulated results from ADS.
Two separate eyes are present in this result; it was determined that there was a
phase delay of 150 ps between the differential inputs which could be caused due to
unmatched cables. This could be caused by a phase miss match in the coax cables
used during measurement. It must also be noted the magnitude of the peak to peak
differential input voltage was greater than 400 mv which was outlined in the LVDS
standard. The MP1701A signal generator had a minimum peak to peak output swing
of 500 mv. This voltage input provided the basis of comparison between measured
and simulated results.
The PRBS signal from the MP1701A was AC-coupled to the input of the LDS,
with a bias voltage of 1.2 V. The pre-amplifier of the LDS was supplied with a VDD
and VCC of 3.3 V. The output of the LDS was AC-coupled to the DCA, and a bias
71
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
0.3
Voltage (V)
0.2
0.1
0
−0.1
−0.2
0
100
200
300
400
Time (ps)
500
600
Figure 4.21: Measured and Simulated 2.5 Gbps Input Signal
voltage of 2.0 V was applied to the open drains of the LDS output. All measurements
were performed with a PRBS input of 28 -1 unless otherwise stated in the figure
caption.
Transient simulations were performed in ADS using extracted parasitics and EM
simulations which reproduced the measurement. The typical/typical corner model
was used in simulation. Measured results from the DCA and simulated results from
ADS were taken and eye diagrams were plotted in Matlab and overlaid. Figures
4.22-4.26 contain a screen capture of the measurement and overlaid simulated and
measured eye diagrams for various modulation voltage settings at 2.5 Gbps.
In addition to the measurements performed at 2.5 Gbps, measurements at other
data rates were performed.
Figures 4.27 - 4.30 contain measurements taken at
625 Mbps, 1.25 Gbps, 3 Gbps and 4 Gbps respectively with a modulation voltage
of 0.9 V. Again a screen capture of the measurement and overlaid simulated and
measured eye diagrams are presented.
72
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
0.6
Voltage (V)
0.4
0.2
0
−0.2
−0.4
−0.6
0
100
200
300
400
Time (ps)
500
600
(a)
(b)
Figure 4.22: (a) Simulated vs. Measured Eye Diagram at 2.5 Gbps vmod = 0.7 V,
(b) Measurement Screen Capture
73
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
Voltage (V)
0.5
0
−0.5
0
100
200
300
400
Time (ps)
500
600
(a)
(b)
Figure 4.23: (a) Simulated vs. Measured Eye Diagram at 2.5 Gbps vmod = 0.8 V,
(b) Measurement Screen Capture
74
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
Voltage (V)
1
0.5
0
−0.5
−1
0
100
200
300
400
Time (ps)
500
600
(a)
(b)
Figure 4.24: (a) Simulated vs. Measured Eye Diagram at 2.5 Gbps vmod = 0.9 V,
(b) Measurement Screen Capture
75
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
1.5
Voltage (V)
1
0.5
0
−0.5
−1
−1.5
0
100
200
300
400
Time (ps)
500
600
(a)
(b)
Figure 4.25: (a) Simulated vs. Measured Eye Diagram at 2.5 Gbps vmod = 1.0 V,
(b) Measurement Screen Capture
76
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
2
Voltage (V)
1
0
−1
−2
0
100
200
300
400
Time (ps)
500
600
(a)
(b)
Figure 4.26: (a)Simulated vs. Measured Eye Diagram at 2.5 Gbps Input PRBS of
231 -1, vmod = 1.3 V, (b) Measurement Screen Capture
77
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
Voltage (V)
1
0.5
0
−0.5
−1
0
500
1000
1500
Time (ps)
2000
2500
(a)
(b)
Figure 4.27: (a) Simulated vs. Measured Eye Diagram at 625 Mbps vmod = 0.9 V,
(b) Measurement Screen Capture
78
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
Voltage (V)
1
0.5
0
−0.5
−1
0
200
400
600
800
Time (ps)
1000
1200
(a)
(b)
Figure 4.28: (a)Simulated vs. Measured Eye Diagram at 1.25 Gbps Input (b) Measurement Screen Capture
79
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
Voltage (V)
1
0.5
0
−0.5
−1
0
50
100
150
200
250
300
Time (ps)
350
400
450
500
550
(a)
(b)
Figure 4.29: (a)Simulated vs. Measured Eye Diagram at 3.0 Gbps Input (b) Measurement Screen Capture
80
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
Voltage (V)
1
0.5
0
−0.5
−1
0
50
100
150
200
250
Time (ps)
300
350
400
(a)
(b)
Figure 4.30: (a)Simulated vs. Measured Eye Diagram at 4.0 Gbps Input PRBS of
231 -1 (b) Measurement Screen Capture
81
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
From these measurements some figures of merit were selected to compare simulated
and measured results. Table 4.7 compares the approximate simulated and measure
voltage level for a zero (V0 ), a one (V1 ) and the voltage difference between a one and
a zero (∆V).
Table 4.7: 2.5 Gbps Approximate Measured and Simulated Eye Diagram Voltages
Data Rate
2.5 Gbps
2.5 Gbps
2.5 Gbps
2.5 Gbps
2.5 Gbps
0.625 Gbps
1.25 Gbps
3.0 Gbps
4.0 Gbps
Vmod
0.7
0.8
0.9
1.0
1.3
0.9
0.9
0.9
0.9
V
V
V
V
V
V
V
V
V
V0
-0.46
-0.75
-1.02
-1.25
-1.40
-1.03
-1.03
-1.03
-1.03
Simulated
V1
V 0.37 V
V 0.64 V
V 0.95 V
V 1.24 V
V 1.50 V
V 0.95 V
V 0.95 V
V 0.95 V
V 0.95 V
∆V
0.83 V
1.39 V
1.97 V
2.49 V
2.90 V
1.98 V
1.98 V
1.98 V
1.98 V
V0
-0.39 V
-0.56 V
-0.85 V
-1.05 V
-1.40 V
-0.9 V
-0.85 V
-0.85 V
-0.80 V
Measured
V1
0.34 V
0.57 V
0.93 V
1.15 V
1.50 V
0.95 V
0.87 V
0.85 V
0.90 V
∆V
0.73 V
1.13 V
1.78 V
2.20 V
2.90 V
1.85 V
1.72 V
1.70 V
1.70 V
Table 4.8 compares the simulated and measured approximate rise and fall times
obtained. The measured rise and fall times are much larger than the simulated times.
This could occur for a variety of reasons such as; models of the passive structures
may be inaccurate for simulation, any parasitics of the measurement equipment are
not modeled in the simulation, bias tee models used in simulation could be inaccurate
and the deviation of the manufactured CMOS transistors from the models used in
simulation could attribute to this difference.
From Table 4.7 the expected modulation current can be calculated for the simulated and measured results. The calculation works with the assumption made previously in the chapter where the laser diode is modeled as a 50 Ω load. Therefore, the
modulation current is calculated as IM OD = ∆V/50. Table 4.9 contains the simulated
and measured modulation currents at 2.5 Gbps for various modulation voltages.
The LDS pre-driver 3.3 V power supplies VDD and VCC consumed 15.6 mA and
5.16 mA respectively. This consumes a power of 68.5 mW. At a maximum modulation
82
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
Table 4.8: 2.5 Gbps Approximate Measured and Simulated Rise and Fall Times
Data Rate
Vmod
2.5 Gbps
2.5 Gbps
2.5 Gbps
2.5 Gbps
2.5 Gbps
0.625 Gbps
1.25 Gbps
3.0 Gbps
4.0 Gbps
0.7
0.8
0.9
1.0
1.3
0.9
0.9
0.9
0.9
V
V
V
V
V
V
V
V
V
Simulated
Rise Time Fall Time
127 ps
91 ps
115 ps
99 ps
117 ps
125 ps
136 ps
157 ps
130 ps
178 ps
110 ps
125 ps
114 ps
126 ps
116 ps
125 ps
121 ps
126 ps
Measured
Rise Time Fall Time
183 ps
244 ps
190 ps
205 ps
202 ps
181 ps
205 ps
210 ps
260 ps
290 ps
230 ps
260 ps
240 ps
260 ps
210 ps
196 ps
190 ps
160 ps
Table 4.9: 2.5 Gbps Approximate Measured and Simulated Modulation Currents
VM OD
0.7
0.8
0.9
1.0
1.3
V
V
V
V
V
Simulated
∆V
IM OD
0.83 V 16.6 mA
1.39 V 27.8 mA
1.97 V 39.4 mA
2.49 V 49.8 mA
2.9 V
58 mA
Measured
∆V
IM OD
0.73 V 14.6 mA
1.13 V 22.6 mA
1.78 V 35.6 mA
2.2 V
44 mA
2.9 V
58 mA
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
83
current of 58 mA, the output stage of the driver consumed 116 mW of power. The
power consumed in the output stage is dependent upon the modulation and bias
currents selected and the voltage rail used. Typically this power is not included when
stating the power consumed by the laser driver because of the dynamic nature.
4.8
Conclusion and Discussion
A 2.5 Gbps high speed analog LDS has been presented in this chapter. The LDS used
a differential pair as the output stage and was able to provide variable modulation and
bias currents. The LDS pre-driver was comprised of two stages; a cascode differential
pair with source follower buffer, and a shunt inductive peaked differential pair using
active inductors for bandwidth enhancement. The LDS was designed to accept a
differential input signal to reduce power supply switching noise. Additionally, the
differential structure should help reduce common mode input noise. Even though the
laser was driven single ended from the output of the driver it should benefit from the
differential nature of the circuit.
Electrical eye diagram measurements have been presented which demonstrate the
LDS is able to provide a modulation current of 14.6-58 mA to a 50 Ω load. A 10%90% approximate rise/fall time of 200 ps was obtained for modulation currents below
44 mA, while a rise/fall time of 230/260 ps was obtained for a modulation current of
58 mA. Power consumption of the core was determined to be 68.5 mW. Bias currents
greater than 50 mA were achieved under DC testing.
As an example a commercial laser diode LI curve is shown in Figure 4.31. This plot
was formed with information taken from [29]. With the LDS providing a modulation
current of approximately 14.6-58 mA, the output power from the laser diode should
achieve an ER of 10 dB over the temperature range of 25-85o C, which would satisfy
the G.984.2 GPON standard [14].
Finally the eye mask outlined in Figure 2.12 and table 2.3 was overlaid on the
84
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
40
25°C
°
85 C
35
Optical Power (mW)
30
25
20
15
10
5
0
0
50
100
150
Current (mA)
Figure 4.31: 2.5 Gbps Commercial Laser Diode LI Curve
measured eye diagram obtained for a modulation voltage of 1.3 V (modulation current
of 58 mA). This is shown in Figure 4.32. The exterior horizontal lines presented in
this diagram represent the voltage level of V0 and V1 , while the inner lines are the
25, 50 and 75% levels of the measured eye. The outer vertical lines represent the the
defined bit period which is 400 ps for a 2.5 Gbps data rate. The inner lines represent
a difference of 20% of the bit period. The rectangle formed by the dashed lines inside
the eye in Figure 4.32 represents the optical eye mask requirements at 2.5 Gbps. This
indicates that the worst case electrical measurement presented in Figure 4.32 meets
the required GPON eye mask. This does not ensure proper optical performance,
however, it is still a possibility that an optical signal could meet the requirements of
the eye mask.
The LDS performance is compared to other laser drivers operating at similar
bit rates in Table 4.10. The electrical measured results obtained are comparable
with results found in literature. The modulation and bias current generated by the
2.5 Gbps LDS are larger than most other works and line up well beside the work
performed in [24]. The rise/fall time lines up well with those reported in [17] and [26],
however, both of those works report optical results. Finally, the power consumption
85
CHAPTER 4. 2.5 GBPS LASER DRIVER DESIGN
2
Voltage (V)
1
0
−1
−2
0
100
200
300
Time (ps)
400
500
600
Figure 4.32: Measured Eye Diagram with Eye Mask
of this work appears to be very reasonable. It consumes less power than the other
reported works, however, it does not have full functionality such as APC like some of
the reported work. This would cause the power consumption to increase.
Table 4.10: 2.5 Gbps Laser Driver Performance Comparison (O - Tested optically, E
- Tested Electrically
Technology
Data Rate
Imod
Ibias
Rise/Fall
Power Supply
Power
APC
[17]-O
0.18 µm CMOS
1.25 Gbps
-
-
< 200 ps
3.3 V
200 mW
Yes
[26]-O
0.18 µm CMOS
2.5 Gbps
20 mA
30 mA
300/300 ps
3.3 / 1.8 V
90 mW
Yes
[24]-E
0.25 µm CMOS
3.5 Gbps
6-60 mA
30 mA
84/97 ps
3.3
145.2 mW
No
This Work-E
0.18 µm CMOS
2.5 Gbps
16-58 mA
0-50 mA
230/260 ps
3.0/3.3 V
68.5 mW
No
Chapter 5
10 Gbps Laser Driver Design
5.1
Introduction
This chapter presents the design of a pseudo differential CMOS 10 Gbps LDS with
adjustable bias and modulation currents. In addition, the LDS is compatible with the
IEEE standard for LVPECL. There were no standards drawn up for 10 Gbps PON
at the time of design. The LDS was designed to be part of an integrated transceiver
in a XG-PON.
5.2
Design Goals and Assumptions
The laser driver was designed without a specific DFB laser diode in hand. Additionally an electrical model of a laser diode was also unavailable in the simulation
suit. Implementations of laser diode models based off of the coupled laser rate equations are possible, however, they require intimate knowledge of the device fabrication
details which manufactures are reluctant to divulge. Therefore, some design assumptions were made for modeling the laser diode to allow simulation. Design goals were
also set to ensure the laser driver could operate with a typical DFB laser diode. The
following section outlines assumptions that were made to proceed with the design of
86
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
87
the laser driver.
The typical series resistance of the active region of a laser diode is in the range of
4-7 Ω [33]. Modeling the impedance of the laser diode as a purely resistive component
is an ideal approximation as there will also be some additional parasitic capacitance
present. However, due to the size of the output transistors in the laser driver and
their large capacitance the relatively small parasitic capacitance of the laser diode
would have minimal effect. Therefore, a resistive model was used.
As discussed in chapter 3, a dampening resistor is typically inserted in series with
the laser diode to eliminate current overshoot and undershoot due to the parasitic
inductance associated with bond wires and laser diode packaging. Therefore, it was
assumed that an off chip dampening resistor with a value of 43-46 Ω could be placed
in series with the laser diode to effectively make the laser diode appear as a 50 Ω load.
The selection of this dampening resistance also sets the characteristic impedance of
the transmission lines on and off chip. This is important to note as the width of the
transmission lines are directly related to the characteristic impedance. Therefore, the
laser diode was modeled as a purely resistive 50 Ω load for simulation purposes.
Modeling the laser diode this way ignores the forward voltage drop associated
with the laser diode, parasitic effects of the bond wires, laser packaging, and parasitic
capacitance of the laser diode active region.
Having selected a laser diode model for use in simulation, design goals were set for
the modulation and bias currents. A review of 10 Gbps DFB laser diode data sheet
[33] revealed that the typical DFB laser diode has a threshold current in the range of
9-50 mA. Additionally, a modulation current of 20-60 mA is needed to achieve an ER
of 10 dB. These design goals are summarized in Table 5.1, for driving a 50 Ω load.
Table 5.1: 10 Gbps Laser Driver Design Goals
Modulation Current
Bias Current
20-60mA
0-50mA
88
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
5.3
Output Stage - The Differential Cascode
The work discussed in chapter 4 utilized a differential pair as the output stage for an
analog LDS. The transistors in the output stage are very large due to the required current they must handle. These large transistors result in large parasitic capacitances
being present. The differential pair is typically used for data rates under approximately 5 Gbps, which is reflected in the literature review performed in chapter 3. At
higher data rates where obtaining the required bandwidth is challenging, the differential cascode can be used. Moving to this topology from the differential pair trades
off power consumption for bandwidth. The choice of this topology is supported by
the work performed by Li et al [22] which is one of the only CMOS PON laser drivers
operating at 10 Gbps. Therefore the topology selected for the 10 Gbps LDS output
stage was the differential cascode. The schematic of the differential cascode is shown
in Figure 5.1.
iD
iD
vG2
Q2
vG1
Q2
Q1
Q1
vG1
I
Figure 5.1: Differential Cascode
The cascode is composed of a cascaded amplifier, consisting of a common source
stage and a common gate stage. The transistors Q2 are provided with a DC bias
voltage labeled VG2 . No signal voltage is applied to this gate, therefore it operates
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
89
as a CG amplifier. The transistors labeled Q1 are provided with a bias voltage
and the signal voltage. They operate as a CS amplifier, and can be thought of as
the differential pair discussed in the previous chapter. With the transistors biased
appropriately to ensure they stay in saturation, the differential input to Q1 steers the
current between both arms. The signal that appears at the drain of Q1 is passed from
the source of Q2 to the drain of Q2 and is presented to the load of Q2 which is 50 Ω
in this case. The transistor Q2 acts as a buffer in this configuration by presenting a
low input resistance to the drain of Q1 and providing a high resistance at the output
[30].
The major advantage of the cascode is the reduced effect of the gate to drain
capacitance CGD (Miller capacitance) on the input of the amplifier [34, 30, 35]. Due
to the large transistors which are needed to steer the drive currents in the output
stage, the large parasitic capacitance at the input to this stage makes pre-driver design
challenging and can potentially limit amplifier bandwidth. Reducing this capacitance
allows for the pre-driver to be more freely designed. However, a disadvantage of the
cascode is that it requires more headroom which in turn requires a higher supply
voltage. This will increase power consumption which is also a concern as the LDS
may have to operate on a battery during power outages while in the field. The CG
transistor which acts as a buffer will also contribute a small amount of noise and can
show up as jitter which is unwanted.
5.4
Pre-Driver
Having selected an appropriate output stage for the LDS, a pre-driver was required
to amplify the input LVPECL signal to the voltage level needed for driving the differential cascode. The input LVPECL voltages are listed in Table 5.2, where VCM is
the common mode voltage, VH is the voltage level of a Sd1 and VL is the voltage level
of a Sd0 .
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CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
Table 5.2: LVPECL Voltage Levels
VCM
VH
VL
2.0 V
2.4 V
1.6 V
The pre-driver must be differential in nature and provide enough gain to the
LVPECL signal to drive the large transistors of the output stage. A number of
topologies could have been selected which could have been single stage or multistage amplifiers. It was determined that a single stage differential pair could meet
these needs and therefore it was selected as the topology for the pre-amplifier. The
schematic is shown in Figure 5.2. Load resistances were kept to a minimum in an
attempt to minimize the RC time delay between the pre-amplifier and the large
parasitic input capacitance to the output stage.
R
R
VOU T
VIN
I
Figure 5.2: Schematic of the 10 Gbps LDS Pre-Amplifier
With the topology of the pre-driver chosen, final optimization of the full LDS was
then performed in ADS.
91
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
5.5
10 Gbps Laser Driver Design
The previous two sections discussed the topologies for the pre-amplifier and output
stage of the LDS. To enable the output stage to produce variable modulation and bias
currents additional transistors were needed. Two additional transistors were included
on the laser diode output arm of the LDS. Transistor Q7 provided the bias current
IBias , to ensure the laser remained biased above IT H . The magnitude of the bias
current was controlled with voltage VBias . A tail transistor Q8 was added to function
as a variable current source to provide the modulation current IM od . It was controlled
by the voltage VM od . The two currents sum together to produce Iout which will drive
the laser diode.
Terminated Off Chip
Q3
Q4 VCascode
Q6
IN
Q1
Q2
Q7
VBIAS
IN
VM OD
Q8
Figure 5.3: Schematic of the 10 Gbps Output Stage
Initial simulations of the LDS lacked the bandwidth required for operation at
10 Gbps. The bandwidth extension technique of inductive peaking was investigated
in ADS. It was determined that a series inductor placed between the pre-amplifier and
the output stage provided the bandwidth extension needed for operation at 10 Gbps.
This method is known as series inductive peaking.
92
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
This allowed for the schematic of the 10 Gbps LDS to be finalized.
5.5.1
Final Schematic
The final schematic for the 10 Gbps LDS is shown in Figure 5.4. The driver output
operated as an open drain with the laser diode, therefore no matching network was
placed at the output. Shunt 50 Ω resistors were also placed at the input of the preamplifier for matching to test equipment. A diode ladder was also used to provide
the cascode DC bias voltages. The intent of this ladder was to share a voltage rail
between the output stage and the bias of the cascoding transistors. This would limit
the number of bias voltages needed.
Terminated Off Chip
RD1
RD1
M4
L1
M2
M2
RG2
RG1
M1
IN
M1
M2
CG1
M2
M5
IN
RG1
M4
M3
L1
I1
VBIAS
M4
M4
M4
VM OD
M2
M4
M4
Figure 5.4: 10 Gbps LDS schematic
The final schematic was then laid out in Cadence Virtuoso. The final layout is
shown in Figure 5.5. It consumes an area of 0.79 x 0.7 mm2 . An octagonal spiral
inductor was used to implement the series peaking inductance. The spiral inductor
layout is shown in Figure 5.6.
93
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
Table 5.3: 10 Gbps LDS Component Values
Transistor Sizes
Component
M1 M2
M3
Value (2.5 µm Fingers) 40 72
42
Resistor Values
Component
RG1
Value
50 kΩ
Inductor Values
Component
Value
Capacitor Values
Component
Value
Current Source Values
Component
Value
M4
4
M5
32
RD1
72 Ω
RG2
112 Ω
L1
1.5nH
C1
950fF
I1
30 mA
Figure 5.5: Layout of 10 Gbps CMOS Laser Driver Stage
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
94
Figure 5.6: 1.5 nH inductor
5.6
Simulation Results
The final 10 Gbps LDS was simulated with Agilent’s ADS using transistor models
provided by TSMC. To account for transmission line effects, pad capacitance and
monolithic inductors, Agilent’s Momentum simulator was used to perform an EM
simulation of the top level metal layers. Figure 5.7 shows the adjusted layout used to
perform co-simulation. Pads and transmission lines were removed from the layout up
to the input and output transistors. The series peaking inductors were also removed.
Shape pins were placed accordingly in Cadence to all removed connections. The
circuit was extracted to include resistive and capacitive parasitic effects.
Transmission lines and inductors were imported into momentum and EM simulations were performed. Figure 5.8 shows the port configuration for the top metal
layer simulation. A two port EM simulation of the spiral inductor was performed.
The extracted active components were then connected to the simulated S-parameter
blocks and co-simulation of the LDS was performed.
To compare the schematic versus extracted layout an identical test bench was
set up in ADS, shown in Figure 5.9. The differential input signal was provided
by the VtPRBS component in ADS. This component provides a pseudo random
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
Figure 5.7: Extracted layout for simulation
Figure 5.8: Momentum simulation of top metal layer
95
96
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
bit sequence (PRBS) voltage source with a variable register length. Using a longer
register length increases the randomness of the input signal, which represents a more
accurate representation of how the driver would operate in the field. However, due
to the nature of the transient simulation a register length of 8 was chosen to produce
simulation results in a reasonable amount of time and to limit the size of the resulting
data files. A PRBS signal with a register length of 8 will begin to repeat itself after
25.5 ns, therefore, all simulations were performed for this length of time.
50Ω
VDD
PRBS
Laser Driver
50Ω
Iprobe
VM OD
VBIAS
Figure 5.9: ADS Transient Simulation Setup
The outputs of the laser drivers were terminated in 50 Ω to model the laser, this
assumption was discussed in section 5.2. A current probe was placed in series with
the resistor that was modeling the laser to measure the drive current. Transient simulations were then performed for the schematic, and extracted layout with parasitics.
Figure 5.10 contains the transient simulation results for the maximum achievable
modulation current. Figure 5.10a shows a single ended input of the the LVPECL
PRBS signal. Figure 5.10b shows the output current for the schematic, while Figure
5.10c shows the output of the laid out driver with parasitic effects present.
As expected, the simulation of the schematic achieved a higher maximum current
for the same input voltages. It was able to achieve a maximum modulation current
swing of approximately 58 mA, while the schematic simulation was operating with a
maximum swing of approximately 57 mA. Also observable in the extracted simulation
results, the driver was on the verge of having the current level of a 0 raise above 0 mA.
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CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
Voltage (V)
2.5
2
1.5
0
5
10
15
20
25
15
20
25
15
20
25
Time (ns)
(a)
60
Current (mA)
50
40
30
20
10
0
0
5
10
Time (ns)
(b)
60
Current (mA)
50
40
30
20
10
0
0
5
10
Time (ns)
(c)
Figure 5.10: Transient Simulation Results (a) Single ended Input Voltage, (b)
Schematic Output Current, (c) Extracted Output Current
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CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
This indicates the driver has reached the maximum modulation current achievable
with a VM OD control voltage of 1.8 V.
Figures 5.11a and 5.11b depict the voltage input and output current for the extracted layout simulation on a time scale from 17.5 - 20 ns. This was included to
demonstrate that the output is following the voltage input.
Voltage (V)
2.5
2
1.5
17.5
18
18.5
19
19.5
20
19
19.5
20
Time (ns)
(a)
60
Current (mA)
50
40
30
20
10
0
17.5
18
18.5
Time (ns)
(b)
Figure 5.11: Transient Simulation Results From 70-80 ps (a) Single Ended Input, (b)
Extracted Output Current
Finally, eye diagrams of both simulations were created and are shown in Figure
5.12. It can be observed that the rise/fall time of the extracted with parasitic simulation is slightly longer than that of the schematic. This was expected as the parasitic
capacitance of interconnects would be included in the extracted simulation. These
parasitics would increase the capacitance at critical nodes limiting the speed of the
99
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
LDS. Both results still exhibit open eyes. Based on these results it was determined
that the parasitic of the layout had minimal effect on the output current and that
the layout was ready to be fabricated.
60
Current (mA)
50
40
30
20
10
0
0
20
40
60
80
100
120
Time (ps)
140
160
180
200
140
160
180
200
(a)
60
Current (mA)
50
40
30
20
10
0
0
20
40
60
80
100
120
Time (ps)
(b)
Figure 5.12: Simulated Eye Diagrams a) Schematic b) Extracted
5.7
Measured Results
As was discussed in section 4.7, an important aspect of integrated circuit design is
obtaining measured results that agree with simulated results. A prototype of the
10 Gbps LDS circuit was fabricated in 0.18 µm CMOS via TSMC through the CMC.
This process offers 6 metal layers, 1 polysilicon layer, 1.8 V and 3.3 V devices and
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
100
a thick top metal layer. A die photograph of the manufactured chip can be seen
in Figure 5.13. The thick metal option for the top metal layer was selected which
provides improved performance for the passive inductors used in this design.
Figure 5.13: 10 Gbps Laser Driver Stage Chip Photo
While performing initial measurements of the 10 Gbps LDS a layout error was
detected. After a review of the fabricated layout, it was determined that the spiral
inductor which is shown in Figure 5.6 was fabricated incorrectly. The layout of the
inductor was missing vias. This error was corrected using a finite ion beam (FIB) on
campus. Figure 5.14 shows where the layout error occurred.
Due to the design of the planar octagonal spiral inductor, the use of two metal
layers is required. The inductor is laid out primarily on the top thick metal layer
with a bridge located at the output. The bridge is formed on the metal layer below
the top metal layer and allows the signal to be coupled out of the inductor. The vais
which would have connected the top metal 6 layer to the metal 5 had been omitted.
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
101
Figure 5.14: FIB of 10 Gbps LDS
The layout error was corrected on Queen’s campus by Dr. Brad Diak of the
Mechanical and Materials Engineering department. Dr. Diak utilized the FIB for
two purposes. First he removed the materials above the layout error exposing the
metal 5. He then deposited tungsten to create a connection between metal 5 and 6
of the CMOS chip. Chips were then tested which confirmed the success of the FIB.
Electrical measurements of the 10 Gbps LDS were then carried out. The performance implications of the FIB will be discussed as they arise in the following sections.
5.7.1
Small Signal Measurements
Having completed the FIB of the 10 Gbps LDS, the complete four port S-parameters
for the 10 Gbps LDS were measured using on-wafer probing with a four port Agilent
N5230A PNA-L network analyzer. The measurement setup is shown in Figure 5.15.
A four port short, open, load and thru (SOLT) calibration was performed as is
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CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
Agilent N5230A PNA-L Network Analyzer
Port 2
DC PSU
Bias Tee
Port 1
Bias Tee
Port 3
DC PSU
Port 4
Bias Tee
Bias Tee
Coax Cable
DC PSU
Coax Cable
Coax Cable
Coax Cable
GSGGSG Probe
GSGGSG Probe
DC Probe Array
DC PSU
DC PSU
Figure 5.15: Four Port S-parameter Test Setup
103
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
outlined in [32] with a GGB CS-2-150 calibration substrate. The following settings
were set on the PNA-L: frequency range of 300 kHz-13 GHz, port power was set to
-30 dBM, IF bandwidth to 1 kHz and 801 measurement points was selected. The
validity of the calibration was confirmed by remeasuring the calibration standards for
open, short and load. The measurement was displayed on Smith Chart and observed
moving from the corresponding open, short, and matched locations in a fine point.
Following a successful calibration, the four port S-parameters were measured using
the bias and control voltages in Table 5.4.
Table 5.4: Bias voltages for S-parameter Measurements
Voltage
Value
Vg
2.0 V
Vd
3.0 V
Vcc
2.9 V
Vdd
3.8 V
Vmod
0.7-1.8 V
Vbias
0.5 V
The measured four port S-parameters were post processed in ADS to obtain the
LDS single ended output to differential input gain. Figure 5.16 shows the ADS simulation setup to obtain the mixed mode S21 gain of the amplifier. This measurement
represents how the device would be operating in reality. Extracted layout simulations
were also performed in the same manner to compare to the measured results. The extracted netlist was altered due to observations made while testing. It was determined
that the fabricated resistors were approximately 20% larger than the originally laid
out resistors. The netlist was altered to reflect this. Also a resistance of 15 Ω was
placed in series with the peaking inductors that were repaired by the FIB. This was
implemented to reflect the parasitics potentially introduced by the FIB. Small signal
and time domain measurements agree better with simulated results with this resistance in place. Figure 4.18 contains the simulated and measured S21 plots obtained
for the various modulation voltage settings. Simulation results were obtained using
the slow/slow corner model provided by TSMC.
Table 5.5 contains the numerical measured and simulation results obtained from
the plots in Figure 5.17.
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CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
50 Ω
Port 1
Port 2
4 Port
Measured
S Parameters
100Ω
Port 1
Port 3
Port 4
50 Ω
Port 2
Figure 5.16: ADS Simulation Setup for S21
Table 5.5: 10 Gbps Measured and Simulated Gain and Bandwidth Results
Vmod (V)
1.8
1.5
1.2
0.9
0.7
Simulated
Gain (dB) BW (GHz)
15.897
2.535
15.772
2.567
15.327
2.6
13.458
2.665
7.762
2.535
Measured
Gain (dB) BW (GHz)
14.143
2.762
14.093
2.957
13.901
3.055
12.02
3.542
7.625
2.762
105
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
20
20
Measured
Simulated
15
15
10
10
5
5
S21 (dB)
S21 (dB)
Measured
Simulated
0
0
−5
−5
−10
−10
−15
5
10
6
10
7
10
8
9
10
Frequency (Hz)
10
10
10
−15
5
10
11
10
6
7
10
8
10
10
Frequency (Hz)
(a)
9
10
10
10
11
10
(b)
20
15
Measured
Simulated
Measured
Simulated
15
10
10
S21 (dB)
S21 (dB)
5
5
0
0
−5
−5
−10
−10
−15
5
10
6
10
7
10
8
9
10
Frequency (Hz)
10
10
10
−15
5
10
11
10
6
7
10
8
10
10
Frequency (Hz)
(c)
9
10
10
10
11
10
(d)
10
Measured
Simulated
5
S21 (dB)
0
−5
−10
−15
−20
5
10
6
10
7
10
8
10
Frequency (Hz)
9
10
10
10
11
10
(e)
Figure 5.17: Simulated and Measured Gain a) Vmod = 1.8 b) Vmod = 1.5 c) Vmod
= 1.2 d) Vmod = 0.9 e) Vmod = 0.7
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
106
The measured gain obtained is approximately 1 dB less than the simulated gain.
This result was not a surprise as the FIB would have introduced parasitics which
would be hard to model. The reduction in gain however has increased the 3 dB bandwidth of the LDS. The measured bandwidths appear to be larger than the simulated
bandwidth across the board. The measured small signal bandwidth is again much
lower than the desired bit rate. One would expect the simulated and measured 3 dB
bandwidths in Table 5.5 to be much closer to 10 GHz. However, bandwidths in the
range of 3 GHz were achieved. Since the laser driver is a nonlinear device operating in
the large signal domain, the small signal results give little information about the final
large signal performance of the driver. Small signal measurements are best suited for
characterizing linear devices. Small signal measurements were included because it is
one tool a designer can use to determine if the fabricated device is operating as it
was simulated. A better characterization of this device are larger signal time domain
measurements, which will now be presented in the following section.
5.7.2
Electrical Eye Diagram Measurements
Electrical eye diagram measurements were performed to characterize the time domain
performance of the 10 Gbps LDS. The eye diagram measurements were performed
with an Agilent DCA which presented the output of the LDS with a 50 Ω load. Figure
5.18 shows the full measurement setup down to the probe level. Picosecond Pulse
Labs 5545 bias tees were used to provide DC bias voltages for the input and output
of the LDS. Additionally, Fairchild SMA attenuators were placed at the input of the
DCA. The attenuators provided 16 dB of attenuation which was required to adhere
to the input voltage limit of the DCA.
The electrical eye diagram measurements were AC-coupled. The output of the
LDS needed to be supplied with a bias voltage and a bias tee was required. This restricted eye diagram testing to measurements of the modulation current capabilities,
107
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
Anritsu MP1701A
Pulse Pattern Generator
Bias Tee
DC PSU
Bias Tee
Coax Cable
Coax Cable
GSGGSG Probe
GSGGSG Probe
DC Probe Array
DC PSU
DC PSU
Coax Cable
Coax Cable
Bias Tee
DC PSU
16dB Attenuator
Bias Tee
16dB Attenuator
Agilent Digital Communications
Analyser 86100C
Figure 5.18: Transient Measurement Test Setup
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
108
as the bias current was a DC source and had no impact on the AC-coupled measurement. The following measurements compare measured continuous time performance
to simulated.
The PRBS signal from the MP1701A was AC-coupled to the input of the LDS,
with a bias voltage of 2.0 V. The pre-amplifier of the LDS was supplied with a VDD
of 2.9 V. The diode ladder was supplied with a VCC of 3.8 V to bias the cascoding
transistors. The output of the LDS was AC-coupled to the DCA, a bias voltage (Vd)
of 3.0 V was applied to the open drains of the LDS output. All measurements were
performed with a PRBS input of 28 -1.
Transient simulations were performed in ADS which reproduced the measurement.
Measured results from the DCA and simulated results from ADS were taken for like
conditions and eye diagrams were plotted in Matlab and overlaid. Figures contain a
screen capture of the performed measurement in addition to the eye diagram overlaid
plots at a bit rate of 10 Gbps.
Transient simulations were performed in ADS using extracted parasitics and EM
simulations to reproduced the measurement. The slow/slow corner model and altered
netlist as discussed in section 5.7.1 was used in simulation. Measured results from
the DCA and simulated results from ADS were taken, eye diagrams were plotted in
Matlab and overlaid. Figures 5.19-5.22 contain a screen capture of the measurement
and the overlaid simulated/measured results for various modulation voltage settings
at 10 Gbps.
In addition to the measurements performed at 10 Gbps, measurements at other
data rates were performed.
Figures 5.23 - 5.25 contain measurements taken at
2.5 Gbps, 5 Gbps and 7 Gbps respectively with a vmod of 1.8 V. Again a screen
capture of the measurement and overlaid simulated/measured eye diagrams are presented.
109
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
0.6
Voltage (V)
0.4
0.2
0
−0.2
−0.4
−0.6
0
20
40
60
80
100
Time (ps)
120
140
160
(a)
(b)
Figure 5.19: (a) Simulated vs. Measured Eye Diagram at 10 Gbps vmod = 0.9 V,
(b) Measurement Screen Capture
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CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
Voltage (V)
1
0.5
0
−0.5
−1
0
20
40
60
80
100
Time (ps)
120
140
160
(a)
(b)
Figure 5.20: (a) Simulated vs. Measured Eye Diagram at 10 Gbps vmod = 1.2 V,
(b) Measurement Screen Capture
111
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
2
Voltage (V)
1
0
−1
−2
0
20
40
60
80
100
Time (ps)
120
140
160
(a)
(b)
Figure 5.21: (a) Simulated vs. Measured Eye Eiagram at 10 Gbps vmod = 1.5 V, (b)
Measurement Screen Capture
112
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
Voltage (V)
2
1
0
−1
−2
0
20
40
60
80
100
Time (ps)
120
140
160
(a)
(b)
Figure 5.22: (a) Simulated vs. Measured Eye Diagram at 10 Gbps vmod = 1.8 V,
(b) Measurement Screen Capture
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CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
Voltage (V)
2
1
0
−1
−2
0
100
200
300
400
Time (ps)
500
600
(a)
(b)
Figure 5.23: (a) Simulated vs. Measured Eye Diagram at 2.5 Gbps vmod = 1.8 V,
(b) Measurement Screen Capture
114
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
2
Voltage (V)
1
0
−1
−2
0
50
100
150
200
Time (ps)
250
300
(a)
(b)
Figure 5.24: (a) Simulated vs. Measured Eye Diagram at 5.0 Gbps vmod = 1.8 V,
(b) Measurement Screen Capture
115
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
2
Voltage (V)
1
0
−1
−2
0
20
40
60
80
100
120
Time (ps)
140
160
180
200
(a)
(b)
Figure 5.25: (a) Simulated vs. Measured Eye Diagram at 7.0 Gbps vmod = 1.8 V,
(b) Measurement Screen Capture
116
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
From these measurements some figures of merit were selected to compare simulated
and measured results. Table 5.6 compares the simulated and measure voltage level
for a zero (V0 ), a one (V1 ) and the voltage difference between a one and a zero (∆V).
Table 5.6: 10 Gbps Approximate Measured and Simulated Eye Diagram Voltage
Results
Data Rate
Vmod
10 Gbps
10 Gbps
10 Gbps
10 Gbps
2.5 Gbps
5 Gbps
7 Gbps
0.9
1.2
1.5
1.8
1.8
1.8
1.8
V
V
V
V
V
V
V
Simulated
V1
V1
-0.48 V 0.44 V
-0.125 V 1.2 V
-1.6 V
1.67 V
-1.6 V
1.7 V
-1.6 V
1.7 V
-1.6 V
1.7 V
-1.6 V
1.7 V
∆V
0.93 V
2.45 V
3.27 V
3.3 V
3.3 V
3.3 V
3.3 V
V0
-0.6 V
-1.05 V
-1.45 V
-1.55 V
-1.6 V
-1.6 V
-1.6 V
Measured
V1
0.53 V
0.99 V
1.4 V
1.55 V
1.6 V
1.6 V
1.6 V
∆V
1.13 V
2.04 V
2.85 V
3.1 V
3.2 V
3.2 V
3.2 V
Table 5.7 compares the simulated and measured approximate rise and fall times
obtained.
Table 5.7: 10 Gbps Approximate Measured and Simulated Eye Diagram Timing
Results
Data Rate
10 Gbps
10 Gbps
10 Gbps
10 Gbps
2.5 Gbps
5 Gbps
7 Gbps
Vmod
0.9
1.2
1.5
1.8
1.8
1.8
1.8
V
V
V
V
V
V
V
Simulated
Rise Time Fall Time
55 ps
31 ps
57 ps
42 ps
56 ps
56 ps
55 ps
62 ps
65 ps
72 ps
62 ps
72 ps
56 ps
66 ps
Measured
Rise Time Fall Time
85 ps
42 ps
72 ps
56 ps
67 ps
78 ps
81 ps
75 ps
83 ps
87 ps
87 ps
89 ps
74 ps
78 ps
From Table 5.6 the expected modulation current can be calculated for the simulated and measured results. The calculation works with the assumption made previously in the chapter where the laser diode is modeled as a 50 Ω load. Therefore, the
modulation current is calculated as IM OD = ∆V/50. Table 5.8 contains the simulated
and measured modulation currents at 10 Gbps for various modulation voltages.
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
117
Table 5.8: 10 Gbps Approximate Measured and Simulated Modulation Currents
VM OD
0.9
1.2
1.5
1.8
V
V
V
V
Simulated
∆V
IM OD
0.92 V 18.4 mA
2.45 V 49 mA
3.27 V 65.4 mA
3.3 V
66 mA
Measured
∆V
IM OD
1.13 V 22.6 mA
2.04 V 40.8 mA
2.85 V 57 mA
3.1 V
62 mA
The LDS pre-driver power consumption is large due to the shunt resistive matching network used. The supply voltage Vg biasing the inputs at 2.0 V draws 100 mA
for a power consumption of 200 mW. If a truly differential resistive matching network
was used, the power consumption attributed from this source could be limited approximately to 0 mW. The 2.9 V supply VC C draws a current of 30 mA for a power
consumption of 87 mW. The 3.8 V power supplies VDD used to bias the diode ladder
consumes less than 1 mA of bias current and is therefore negligible. At a maximum
modulation current of 62 mA, the output stage of the driver consumed 116 mW of
power. The power consumed in the output stage is dependent upon the modulation
and bias currents selected and the voltage rail used. Typically this power is not included when stating the power consumed by the laser driver because of the dynamic
nature.
5.8
Conclusion and Discussion
A 10 Gbps high speed analog LDS has been presented in this chapter. The LDS used
a differential cascode as the output stage and was able to provide variable modulation
and bias currents. The LDS pre-driver was comprised of a single stage differential
pair. Series inductive peaking was used for bandwidth extension. The 10 Gbps LDS
was designed differentially for the same reasons as the previously discussed 2.5 Gbps
LDS.
An attempt at integrating the 10 Gbps CMOS LDS chip with a commercial laser
118
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
diode was attempted. A PCB board was manufactured in an attempt at chip on
board testing. The CMOS chip was to be epoxied to the PCB and a commercial laser
diode attached for optical testing. However, complications were encountered while
wire bonding the CMOS chip to the board which are discussed in appendix A. These
complications limited testing to the electrical domain.
Electrical eye diagram measurements have been presented which demonstrate the
LDS is able to provide a modulation current of 22.6-62 mA. A 10%-90% rise/fall
time of 87 ps and 75 ps has been respectively obtained while operating at maximum
modulation current. The core of the LDS consumes a power of 287 mW which could
be reduced with proper differential input matching networks. Bias currents greater
than 50 mA were obtained while performing DC testing.
As an example a commercial laser diode LI curve is shown in Figure 5.26. This plot
was formed with information taken from [33]. With the LDS providing a modulation
current of approximately 22.6-62 mA, the output power from the laser diode should
achieve an ER of 8.2 dB over the temperature range of 25-85o C, which would satisfy
the G.987.2 GPON standard [14].
40
25°C
85°C
35
Optical Power (mW)
30
25
20
15
10
5
0
0
50
100
150
Current (mA)
Figure 5.26: 10 Gbps Comercial Laser Diode LI Curve
Finally the eye mask outlined in Figure 2.12 and table 2.3 was overlaid on the
119
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
measured eye diagram obtained for a modulation voltage of 1.8 V (modulation current
of 62 mA). This is shown in Figure 5.27. The exterior horizontal lines presented in
this diagram represent the voltage level of V0 and V1 , while the inner lines are the
25, 50 and 75% levels of the measured eye. The outer vertical lines represent the the
defined bit period which is 100 ps for a 10 Gbps data rate. The inner lines represent
a difference of 20% of the bit period. The rectangle formed by the dashed lines inside
the eye in Figure 5.27 represents the optical eye mask requirements at 10 Gbps.
This indicates that the worst case electrical measurement presented in Figure 5.27
meets the required XG-PON eye mask. This however does not ensure proper optical
performance, however, it is still a possibility that an optical signal could meet the
requirements of the eye mask.
2
Voltage (V)
1
0
−1
−2
0
20
40
60
80
Time (ps)
100
120
140
160
Figure 5.27: Measured Eye Diagram with Eye Mask
The LDS performance is compared to other laser drivers operating at similar bit
rates in Table 5.9. The work performed in this chapter utilized the same output
stage topology as the work performed in [22]. It is significant that the electrical
results obtained were comparable to those found in literature as a FIB was required
to correct a layout error. The modulation and bias currents obtained were lower than
those found in [22], this is mainly due to the 1.8 V transistors used in this work. The
rise and fall times obtained are approximately three times slower than those found
in [22], however, 20%/80% rise/fall times were reported in [22]. Finally, the power
120
CHAPTER 5. 10 GBPS LASER DRIVER DESIGN
consumption reported in this work appears to be very reasonable, but a direct laser
driver comparison is illogical as APC was not implemented in this work which would
consume more power.
Table 5.9: 10 Gbps Laser Driver Performance Comparison ( O - Tested Optically, E
- Tested Electrically, S - Simulated
Technology
Data Rate
Imod
Ibias
Rise/Fall
Power Supply
Power
APC
[22]-O
0.18 µm CMOS
10 Gbps
20-100 mA
0-80 mA
28/29 ps
1.8/4.5 V
540 mW
Yes
[25]-S
0.18 µm CMOS
10 Gbps
0-35 mA
2-20 mA
-
1.8 V
136.8 mW
Yes
This Work-E
0.18 µm CMOS
10 Gbps
22.6-62 mA
0-50 mA
87/75 ps
2.9/3 V
287 mW
No
Chapter 6
Conclusions and Future Work
6.1
Conclusions
This thesis presents the design and analysis of two high speed analog LDS for use
in a PON upstream BM-Tx using low cost CMOS technology. The maturation of
CMOS technology has lead to aggressive scaling of device sizes which has made it
an increasingly attractive technology for high speed analog design. CMOS provides
high levels of integration as it is the industry standard for digital circuits, analog and
digital systems can share one substrate reducing costs. Additionally CMOS is a more
cost effective solution than traditional expensive high speed analog substrates. The
highly integrated solution using low-cost CMOS has the potential to reduce system
costs, which is important in this highly cost sensitive area.
A 2.5 Gbps LDS intended to meet the GPON specifications has been presented
in chapter 4. The LDS uses a two stage pre-driver and a differential pair for the
output stage. The pre-driver accepts an LVDS input voltage while the output is able
to provide variable bias and modulation currents. The first stage of the pre-driver is
comprised of a differential cascode and a source follower buffer. The second stage is a
differential pair which uses active inductors for shunt inductive peaking. The peaking
was used to extend the bandwidth of the pre-amplifier. A differential topology was
121
CHAPTER 6. CONCLUSIONS AND FUTURE WORK
122
used to reduce the effects of power supply switching noise and common mode noise
rejection. The common mode noise rejection is important as the LDS is intended to
be used in an integrated transceiver.
Electrical eye diagram measurements have been presented which demonstrate the
LDS is able to provide a modulation current of 14.6-58 mA to a 50 Ω load. A 10%90% approximate rise/fall time of 200 ps was obtained for modulation currents below
44 mA, while a rise/fall time of 230/260 ps was obtained for a modulation current of
58 mA. Power consumption of the core was determined to be 68.5 mW. Bias currents
greater than 50 mA were achieved under DC testing.
Next, a 10 Gbps LDS was presented. To increase the bandwidth of the LDS, a
differential cascode was used for the output stage. A differential pair was used for
the pre-amplifier, which accepted an input LVPECL voltage signal. Series inductive
peaking was used between the pre-amplifier and output stage to extend the bandwidth
of the LDS. The output of the 10 Gbps LDS can provide variable bias and modulation
currents. A differential topology was for the 10 Gbps LDS for the same reasons as
discussed above for the 2.5 Gbps LDS.
Electrical eye diagram measurements have been presented which demonstrate the
LDS is able to provide a modulation current of 22.6-62 mA. A 10%-90% rise/fall
time of 87 ps and 75 ps has been respectively obtained while operating at maximum
modulation current. The core of the LDS consumes a power of 287 mW which could
be reduced with proper differential input matching networks. Bias currents greater
than 50 mA were obtained while performing DC testing.
The measured electrical eye diagrams for the 2.5 Gbps and the 10 Gbps meet the
timing requirements for the GPON standard. Further work is needed to investigate
weather or not the timing requirements would still be met once the CMOS chips were
integrated with commercial laser diodes.
An attempt at integrating the CMOS LDS chips with commercial laser diodes was
CHAPTER 6. CONCLUSIONS AND FUTURE WORK
123
attempted. PCB boards were manufactured in an attempt to perform chip on board
testing. The CMOS chips were to be epoxied to the PCBs and a commercial laser
diode attached for optical testing. However, complications were encountered while
wire bonding the CMOS chip to the board which are discussed in appendix A. These
complications limited testing to the electrical domain.
On a final note, the resulting modulation currents obtained are based upon the
laser diode model assumptions made at the beginning of this chapters 4 and 5. The
author would like to note that typically a laser diode has a built in forward voltage.
This voltage is typically on the range of 1.1-1.4 V for a DFB laser diode. This
forward voltage would actually limit the maximum achievable modulation current if
this design was integrated with a commercial laser diode. However, using a lower
series resistance to match the laser diode too could also increase the modulation
current, in this case all output transmission lines would need to be adjusted to match
the new characteristic impedance of the output.
6.2
Future Work
The work completed in this thesis offers several opportunities for areas of further
study. For both LDSs, future work includes integration of the LDS and a laser diode
with a laser diode for optical characterization. Optical characterization of the LDS
would greatly benefit this research as it is needed to accurately conclude the LDS
would work in the field.
Further optimization of both output stages is also needed to perform burst mode
measurements. The 3.3 V thick gate oxide transistors should have been used for the
output stages. The large currents required to drive a DFB laser diode cause a large
voltage swing on these transistors. The thicker gate oxide would increase the voltage
handling capabilities of these transistors and enable larger currents to be generated.
While optimizing the output stage additional changes could be made. Transitioning
CHAPTER 6. CONCLUSIONS AND FUTURE WORK
124
from the 0.18 µm CMOS technology to a shorter gate length should also allow for
increased performance. Cost should be kept in mind if this technology change occurs
as the transceiver is a highly cost sensitive area. Differential input matching networks
should also be added to both designs for future testing purposes.
Additionally the bias currents achieved by both LDSs were greater than those set
out in the design goals. Minimizing the size of the biasing transistor in the future
should limit the parasitic capacitance at the output which would increase the speed
of operation.
Further work implementing automatic power control and end of life detection
at both data rates is needed to obtain a fully functioning laser driver for PONs.
Implementing these features has been omitted in this work, however in the future the
feedback loop for APC is needed. A review of the research performed to date has
been provided in this thesis and provides a starting point for future implementation
of these systems.
Finally, verifiable electrical models of the laser diodes being used would benefit
this research greatly. The current software being used for this research lacks device
models for laser diodes. An accurate model of the laser diode would greatly benefit
the research as optimization could be performed in simulation to obtain the best
result for device integration. These device models are hard to obtain as the models
are developed based on laser diode rate equations require detailed knowledge of the
device fabrication which manufactures do not readily give up. Simulation software
that can also bridge the gap between the electrical and optical domain while modeling
the devices being used would be greatly beneficial.
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Appendix A
Integration
An attempt was made to obtain optical measured results described in the following
sections. PCBs were fabricated to integrate a laser diode with the designed CMOS
LDSs in a chip on board (COB) configuration. This appendix discusses the design
and fabrication of the PCBs and the problems encountered with wirebonding which
did not allow optical measurements.
A.0.1
PCB Designs
The first step to designing the PCB boards was to select an appropriate substrate. The
two layer Rogers Duroid 5880 laminate was selected because the dielectric constant
of the substrate is constant over a wide frequency range and offers a low dissipation
factor which extends the usefulness of the substrate to the Ku-band and above [36].
This substrate should offer sufficient performance for data rates above 10 Gbps.
Following substrate selection, ADS’s linecalc was used to determine the required
width needed for a microstrip line with a characteristic impedance 50Ω. A line width
of 1.15 mm was obtained for a laminate with a dielectric thickness of 0.318 mm.
This combination of line-width and thickness was selected to provide a transmission
line relative to the scale of the CMOS chip, while leaving it as thick as possible to
minimize line losses. This impedance was selected as series resisters were to be used
130
APPENDIX A. INTEGRATION
131
for broadband matching the laser diode impedance to 50Ω.
Following this, component selection for various purposes was performed. To couple the signal off of the PCB, SMA edge connectors were selected. The Johnson
Components 50Ω edge connector [37] which is compatible with a substrate with a
thickness of 1.575 mm. The PCB board was fabricated with an aluminum shim to
make it compatible.
Next, the series matching resistors were selected. Two 0805 surface mount resistors
from Susumu were selected. A 1/10W RR series resistor for high frequency applications [38], and a 1/4W RGH series high power resistor [39] were chosen. This was to
provide two resistor options in the same package type. The RR series should handle
drive currents of 44.7 mA, while the RGH should handle currents up to 70 mA. This
provided multiple options for a series matching resistor. This was deemed important
as the parasitics at high frequencies could affect the impedance of the resistors.
Finally, decoupling capacitors were selected for the DC supply lines. Multilayer
high Q capacitors [40] were selected. Selection of the capacitors was based upon
selecting the largest possible capacitance while being able to operate below the self
resonant frequency of the device. With that in mind a 7 pF, 0603 capacitor was
selected for the 2.5 Gbps LDS and a 1 pF, 0201 capacitor was selected for the 10 Gbps
LDS.
Having selected all the needed components, ADS Momentum was used to layout
the PCBs. The boards were laid out according to the design rules provided by Saturn
Electronics Inc.. The manufactured PCBs are shown in Figure A.1. Gold plating was
used on the copper traces to allow for wire bonding. This was important as gold wire
is typically used in high frequency circuits for wire bonding and does not interface
with copper. Additionally, a solder mask was also used.
Next, the CMOS LDS needed to be attached to their respective PCB. The die
were attached with H20E silver epoxy [41]. This was performed by hand under a
132
APPENDIX A. INTEGRATION
(a)
(b)
Figure A.1: Manufactured PCBs; 2.5 Gbps (a), 10 Gbps (b)
133
APPENDIX A. INTEGRATION
microscope. Post attachment the board and die were baked in an oven at 100O C for
two hours. Figure A.2 shows both PCBs with their respective CMOS LDS attached.
(a)
(b)
Figure A.2: Photograph of CMOS Chip Attached to PCB; 2.5 Gbps (a), 10 Gbps (b)
Having attached the CMOS chips to their carrier PCBs, wire bonding was attempted.
APPENDIX A. INTEGRATION
A.0.2
134
Wirebonding Attempt
Wire bonding was performed at Queen’s University in the Energy and Power Electronics Applied Research Laboratory (ePEARL) by the author. The Kulicke & Soffa 4522
manual wire bonder was used, as shown in Figure A.3. The 4522 offers independent
z axis, force, bond time and bond power controls.
Figure A.3: Photograph of Wire bonder Setup in PEARL Lab
Initial training was provided by the lab engineer which included loading and setting up of the wire bonder. A planar ceramic substrate was supplied which consisted
of a variety of gold bond pads. To perform a wirebond the work piece was attached
to a heated chuck under the microscope. The chuck placement was controlled by the
mouse in the right hand side of Figure A.3. An initial click and hold of the left mouse
button will bring the bond head down to the first search height. This height should
be set just above the work piece. The bond head should be moved above the desired
bond area, then the right mouse button is released. The bond head then places a wire
bond at this area, then the bond head will rise to the loop height. The mouse should
then be adjusted to move the chuck to the approximate area of the second bond.
The left mouse button is clicked again and the bond head will lower to the second
search height. When the mouse button is released a wedge bond is formed. Once
successful bonding was accomplished on the supplied substrate, attempts at bonding
APPENDIX A. INTEGRATION
135
the CMOS chip to the PCB were carried out. Successful planar wire bonding was
then demonstrated on the manufactured PCB which is shown in Figure A.4. Various
length wire bonds were produced on the PCB. The ones shown in Figure A.4 are
relatively short.
Figure A.4: Example of Successful Planar Wirebond on PCB
Problems were encountered while wire bonding from the CMOS chip to the designated landing area on the PCB. It was determined that the transmission lines were
brought in too close to the CMOS chip. The transmission lines were brought in as
close as possible in an effort to reduce the parasitic inductance associated with the
bondwire. Bond wire inductance is directly proportional to bondwire length. Coupled
with this, the use of the solder mask covered the transmission lines limiting where the
wire bond could be place. The author was able to successfully place the ball bond
on the CMOS bond pads. However, when the second bond was being placed, the
bondwire was catching the side of the CMOS chip. This usually resulted in the wire
breaking, and in some cases, removing the CMOS chip off of the PCB. Figure A.5
APPENDIX A. INTEGRATION
136
shows an example of this result.
Figure A.5: Example of Wirebond Length Required
The image captured in Figure A.5 is of a 2.5 Gbps LDS attached to another PCB
from the same fabrication run. This PCB had a much larger die attach area than
the 2.5 Gbps PCB. This allowed for longer wire bond attempts to be performed.
The spacing from the die attach area to the transmission line on the right hand side
is 127 µm, which was the same spacing used in the 2.5 and 10 Gbps designs. The
width of the die attach area was 2400 µm, while the CMOS chip had a width of
approximately 1200 µm. Under these spacing conditions a few successful wire bonds
were performed. When attempts at some shorter bonds were made, the wire once
again caught the edge of the CMOS chip which caused the CMOS chip to be pulled
off the PCB. From this work it was evident that the 127 µm spacing used in the 2.5
and 10 Gbps designs was too small.
Upon this conclusion, attempts at obtaining optical measured results for this work
were halted.
A.0.3
Future Suggestions
If this work is developed further, a solution is needed to integrate the laser diodes
with the LDS. Optimization of the transmission line spacing to the die attach area
APPENDIX A. INTEGRATION
137
is required. In the future a more cost effective solution for the 2.5 Gbps PCB should
be designed, fabricated and integrated first. Utilizing the 5880 substrate at this
frequency is over design. Therefore, a cheaper solution could have been chosen which
would allow for multiple runs. Removal of the soldermask would also allow one to
figure out the minimum bond distance. With this spacing in hand creating new
designs with repeatable wire bonding should be successful.
An additional solution that should result in a shorter wire bond is the milling
of the die attach area. If the PCB was milled by the manufacture to a depth equal
to the CMOS chip, it would be possible to epoxy the chip in this area. This would
result in the top of the CMOS chip being roughly on the same plane as the PCB. As
demonstrated above, planar wire bonds were performed quite successfully over short
distances. This would be beneficial as it would limit the parasitic inductance.