EE290C - Spring 2004
Advanced Topics in Circuit Design
High-Speed Electrical Interfaces
Lecture #22
Link Budgeting and BER Analysis
Vladimir Stojanovic (vlada@stanford.edu)
Stanford University and Rambus Inc.
4/8/2004
Agenda
Backplane channel review
Link system models and noise
Performance analysis
2
1
Backplane Environment - Recap
Package
On-chip parasitic
Back plane trace
Package
via
(termination resistance and
device loading capacitance)
Line card trace
Line card
via
Back plane connector
Backplane via
Line attenuation
Reflections from stubs (vias)
3
Backplane Channel
Same backplane
Different lengths
Different stubs
Top vs. Bot
Required signal amplitude set
by noise
Need to architect the link to
work over all channels
Need tools to estimate link
performance over all channels
Attenuation [dB]
Loss is variable
0
9" FR4
-10
-20
-30
26" FR4
-40
-50
9" FR4,
via stub
26" FR4,
via stub
-60
0
2
4
6
8
10
frequency [GHz]
4
2
Inter-symbol Interference (ISI) - Recap
Channel is low pass
Dispersion –
short latency
(skin-effect,
dielectric loss)
1
0.8
0.6
Reflections –
long latency
(impedance mismatches –
connectors, via stubs, device
parasitics, package)
Tsymbol=160ps
0.4
0.2
0
0
1
2
3
ns
5
ISI
1
Error!
0.8
Amplitude
pulse response
Our nice short pulse gets spread out
0.6
0.4
0.2
0
0
2
4
6
8
10 12
Symbol time
14
16
18
Middle sample is corrupted by 0.2 trailing ISI (from the previous symbol), and
0.1 leading ISI (from the next symbol) resulting in 0.3 total ISI
As a result middle symbol is detected in error
6
3
Crosstalk
Don’t just receive the signal you want
Get versions of signals “close” to you
Vertical connections have worse coupling
“Close” in these vertical connection regions
Sercu, DesignCon03
Far-end XTALK (FEXT)
Desired signal
Reflections
Near-end XTALK (NEXT)
7
Attenuation [dB]
Frequency View of Crosstalk
0
-10
THROUGH
-20
-30
NEXT
-40
FEXT
-50
-60
0
2
4
6
8
10
frequency [GHz]
For this example:
> 4GHz, noise is as large as the signal
8
4
Agenda
Backplane channel review
Link system models and noise
Previous standard approaches
Statistical modeling
Performance analysis
9
Parameter Definition for VT Based Budget
Voltage parameter definitions
Simultaneous switching output (SSO) noise
Receiver sensitivity (offset + overdrive)
Channel loss
Crosstalk
Back-to-back read
Timing parameter definitions
tQ: transmitter output timing
tSH: receiver output timing
tCE: channel timing error
tJ: clock source jitter
10
5
RDRAM VT Budget
Component of
Timing Budget
Bit time
RAC tQ
RDRAM tSH
tCE
tJ
Margin
Total
RAC to RDRAM
ps
%
1250.0
500.0 40.0%
400.0 32.0%
290.0 23.2%
60.0
4.8%
0.0
0.0%
100.0%
Vterm=1.2V and 36D (channel)
At 800Mb/s
tCE is at 23% of bit time
vCE is at 62.5% Vswing (900mV)
11
Fiber Channel – Methodologies for Jitter Specification
Total jitter = Deterministic (DJ) + random jitter (RJ)
DJ: Non-Gaussian, bounded in amplitude and has specific causes (duty cycle
distortion, data dependent, sinusoidal and uncorrelated (power supply noise
injection))
DJ is measured as a peak-to-peak value and adds linearly
RJ: Gaussian and measured as an RMS value
-12
RJ: Peak-to-peak jitter = 14 * RMS jitter for a BER of 10
Total jitter = peak-to-peak DJ + peak-to-peak RJ
Jitter measurement definitions
Jitter output
Jitter transfer
Jitter tolerance (ability of a CDR to successfully recover the data in the
presence of jitter)
Create a tolerance mask by examining the CDR lock at different
frequencies vs. sinusoidal jitter magnitude
12
6
Jitter measurement definitions
CDR Tolerance & XAUI Sinusoidal Jitter Tolerance Mask
Jitter Amplitude (UI)
9.00
8.50
8.00
7.50
7.00
6.50
6.00
5.50
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
0.010
XAUI Sinusoidal Jitter Mask
XAUI Mask
LV at Vtt-Rx=1V & 3.125Gbps
1.875MHz
22KHz
0.100
20 MHz
0.1UI
0.1UI
1.000
10.000
100.000
Jitter Frequency (MHz)
Jitter generation (jitter added by the PLL due to phase and supply noise)
Jitter transfer (jitter at the output of the PLL due to refClk noise)
Jitter tolerance (ability of a CDR to successfully recover the data in the
presence of jitter)
Create a tolerance mask by examining the CDR lock at different frequencies vs.
sinusoidal jitter magnitude
13
Fiber Channel Jitter Specification for 1.0625 Gbps
14
7
Previous system models
Mostly non-existent
Borrowed from computer systems
Worst case analysis
Can be too pessimistic in links
Borrowed from data communications
Gaussian distributions
Works well near mean
Often way off at tails
ISI distribution is bounded
Need accurate models
To relate the power/complexity to performance
15
Comparison w/ Gaussian Model
-2
-4
-6
-8
-10
-1 0
40 m V erro r @ 1 0
2 5% of eye h eig h t
0
25
50
75
100
re sidu al IS I [m V ]
10
Steady-State Phase Probability
0
Impact on CDR phase
0
-2
9% T s ym bol
-4
-6
-8
-10
log
log
10
probability [cdf]
Cumulative ISI distribution
4% T s ym bol
e rro r @ 10
80
-1 0
100 120 140 160 180
ph ase cou nt
Gaussian model only good down to 10-3 probability
Way pessimistic for much lower probabilities
16
8
A new model
Use direct noise and interference statistics
Main system impairments
Interference
Voltage noise (thermal, supply, offsets, quantization)
Timing noise – always looked at separately
Key to integrate with voltage noise sources
Need to map from time to voltage
17
Residual ISI Error
Cannot correct all the ISI
Equalizers are finite length
EQ coefficients quantized
Channel estimate error
The error affects both voltage and timing
Need to find the distribution of this error
18
9
voltage [mV]
200
0.75
0
1
2
sample #
probability [pmf]
-3 -2 -1
ISI distribution
0.5
0.25
0
15
-10
Convolution method
1
-15
15
[mV]
1
probability [pmf]
Tx Equalized
pulse response
probability [pmf]
Generating ISI Distributions
0.75
1
0.75
0.5
0.25
0
-25
-5
5
25
voltage [mV]
0.5
0.25
0
-10
[mV]
10
19
Estimated Residual Error
5 Tap Transmitter Equalizer
probability distribution of residual ISI
probability distribution of residual ISI
0.016
0.04
0.012
0.03
0.008
0.02
0.004
0.01
0
-60
-40
-20
0
20
voltage [mV]
40
60
Data sample distribution
0
-150
-100
-50
0
50
100
voltage [mV]
150
Edge sample distribution
20
10
Power spectral density [dBV]
Equalizer Related Error Sources
edge sample
data sample
-30
-30
residual ISI
residual ISI
-40
10% /tap max. eq.
estimation error
-50
-60
-40
10%/tap max. eq.
estimation error
-50
10mV/tap max. eq.
quantization error
0
1
2
3
frequency [GHz]
-60
10mV/tap max. eq.
quantization error
0
1
2
3
frequency [GHz]
Residual ISI is the biggest source of error
Quantization error and equalizer estimation
Are significant for reasonable assumptions about accuracy
21
Random Voltage Noise
Thermal noise
Resistor and Device noise
Quantization
Estimation error
Supply noise
Receiver offset
22
11
Effect of Timing Noise
Need to map from time to voltage
Jittered
sampling
Voltage noise
when receiver
clock is off
Ideal
sampling
Voltage noise
The effect is going to depend on the size of the jitter, the input
sequence, and the channel
23
Effect of Transmitter Jitter
Jittered pulse decomposition
ideal
bk
bk
ε kTX
kT
1
kT
ε TX
k +1
(k + 1)T
2
+
(k +1)T
bk
ε TX
k +1
ε kTX
− bk
noise
Decompose output into ideal and noise
Noise are pulses at front and end of symbol
Width of pulse is equal to jitter
V. Stojanović, M. Horowitz, “Modeling and Analysis of High-Speed Links,”
IEEE Custom Integrated Circuits Conference, September 2003.
24
12
Transmitter Jitter Noise
Approximate the noise pulses with deltas
Assuming jitter is much narrower than channel impulse response
bk ε kTX+1
ε TX
k +1
bk
εkTX
≈
− bk
− bk ε kTX
Channel output
Output with no jitter
Response to the noise deltas
25
Jitter effect on voltage noise
Transmitter jitter
High frequency (cycle-cycle) jitter is bad
Changes the energy (area) of the symbol
No correlation of noise sources that sum
Low frequency jitter is less bad
Effectively shifts waveform
Correlated noise give partial cancellation
ε
Rx
k
≡
εkRx
Receive jitter
Modeled by shift of transmit sequence
Same as low frequency transmitter jitter
26
13
Jitter Propagation Model
TX
precoder
ak
w
bk
ideal
pulse
response
p( jT )
nvdd
nin
noise h jT + T 
PLL
Hjit(s)
sbE
∑b
j = − sbS
sbE
∑b
j =− sbS
âk
xk
x kjitTX
ε kRX
RX
impulse
response
x ISI ( kT + φ i + ε kRX ) =
x jitter (kT + φi + ε kRX ) =
+
2

ε kTX,k +1
x kISI
k− j
k− j
p ( jT + φ i )
T
T


RX
TX
RX
TX
h( jT + 2 + φi ) ε k − ε k − j − h( jT − 2 + φi ) ε k − ε k +1− j 


(
)
(
)
Channel bandwidth matters
If h(T/2) is small, the noise is small
27
h(nT+1/2) not small, many pulses add
White jitter
Noise from Tx much larger
than from Rx jitter
From Rx jitter, noise is white
From Tx jitter, filtered by the channel
Y-axis is noise σ (in Volts)
If the noise was white
Power spectral density [dBV]
Voltage Noise From Jitter
Source – white jitter
-30
Noise from Tx jitter
-40
-50
Noise from Rx jitter
-60
σ = 10mV => -40dBV
0
0.5
1
1.5
2 2.5 3
frequency [GHz]
Bandwidth of the jitter is critical
It sets the magnitude of the noise created
28
14
Jitter Source From PLL Clocks
Noise sources
Reference clock phase noise
VCO supply noise
Clock buffer supply noise
RefClk
+detector
Phase
Icp
− Kpd
Icp
VCO
R
Kvco/s
Clock
buffer
C
÷N
Stationary phase-space model
29
RefClk
Phase
Icp
− Kpd
Icp
+detector
VCO
R
C
÷N
Kvco/s
Clock
buffer
Noise transfer functions [dB]
Noise Transfer Functions
10
from
input clock
from
clock buffer supply
0
-10
-20
from
VCO supply
-30
5
10
6
10
7
10
8
10
9
10
10
10
frequency [Hz]
Low-pass from reference (input clock)
Band-pass from VCO supply
High-pass from clock buffer supply
M. Mansuri, C-K.K. Yang, "Jitter optimization based on phase-locked loop design parameters,"
IEEE Journal Solid-State Circuits, Nov. 2002
30
15
PLL supply noise
Deterministic noise still
present.
Where is this noise
coming from?
Total noise ~ 25mV peak-to-peak
3.7% of on-chip VddA (quiet PLL supply)
E. Alon, V. Stojanovic, M. Horowitz “Circuits and Techniques for High-Resolution Measurement
of On-Chip Power Supply Noise,” IEEE Symposium on VLSI Circuits, June 2004.
31
Noise Spectrum (1)
0
0
-20
-20
-40
-40
PSD (dBV)
PSD (dBV)
V dd noise
-60
-80
-60
-80
Noise floor
-100
10MHz
V ddA noise
100MHz
1GHz
Frequency
Noise floor
10GHz
-100
10MHz
100MHz
1GHz
Fre quency
10GHz
Deterministic noise frequency components:
200MHz - ASIC core operating frequency.
Noise on link supplies due to ground bounce.
400MHz - reference clock, some link logic.
4GHz - link data rate.
Data & edge clocks at 2GHz => 4GHz noise.
Tail current modulation in diff. pairs.
32
16
Noise Spectrum (2)
0
0
-20
-20
-40
-40
PSD (dBV)
PSD (dBV)
V dd noise
-60
V ddA noise
-60
-80
-80
Noise floor
-100
10MHz
100MHz
1GHz
Frequency
Noise floor
10GHz
-100
10MHz
100MHz
1GHz
Fre quency
10GHz
Random noise mostly white.
Low frequency peaking in Vdd noise due to underdamped impedance
of distribution network.
VddA distribution network more damped because of higher resistance.
33
2x Oversampled Bang-Bang CDR
RX
dn
Slicer
dn
PD
en
data Clk
edge Clk
deserializer
dataOut
Phase
control
Phase
mixer
en (late)
ref Clk
PLL
dn-1
Generate early/late from dn,dn-1,en
Simple 1st order loop, cancels receiver setup time
Now need jitter on data Clk, not PLL output
34
17
Data Clk Noise
Model phase selector and PLL
Base linear PLL jitter
Add non-linear phase selector noise from CDR
Model the CDR loop as a state machine
The current phase position is the state
State transitions are caused by early/late
Jitter on input data and PLL means
Possible to be late and get early PD result
Often filter early/late to generate up/down
A.E. Payzin, "Analysis of a Digital Bit Synchronizer," IEEE Transactions on Communications, April 1983.
35
Probability
Transition Probabilities
1
p-up
p-dn
CDR loop
0.8
Accumulate-reset
filter, length 4
Residual ISI
0.6
0.4
p-no-valid
transitions
p-late
p-early
At edge -30dBV
Desired phase
State = 133
p-hold
0.2
0
0
Example system:
50
100
150
200
250
Phase count
On average move to correct position
But probability of wrong movement is not small
Need to find probability of at each phase location
36
18
Bang-Bang CDR Statistical Model
pdn,i
φ0
phold,i
φi−1 φi
pup,i
φi +1
φL
Need steady state probabilities of the states
Have the transition probabilities
Iteratively apply transition probabilities (Markov chain)
Results will converge to a steady-state
37
Bang-Bang CDR Model
log 10 Steady-State Probability
0
-5
-10
-15
0
50
100
150
200
250
Phase Count
Gives the probability distribution of phase
Which is the CDR jitter distribution
38
19
Noise and Interference Summary
Many important sources of noise and interference
ISI, crosstalk, quantization, estimation, etc.
Largest error comes from ISI
By factor of 10x
Timing is noisy too
High frequency transmitter jitter is bad
CDR jitter needs to be considered
Especially if the data input is noisy
What is the impact on performance?
39
Agenda
Backplane channel review
Link system models and noise
Previous standard approaches
Statistical modeling
Performance analysis
40
20
ISI and CDR Phase Distributions
300
2PAM - lin. eq
-5
voltage [mV]
200
-10
100
-15
0
-100
-20
-200
-25
-300
50
60
70
80
90
time [ps]
100
110
-30
In ideal world, there would be only two dots
This plot shows how these dots spread out
Vertical slice – ISI distribution per time offset
Horizontal weight – CDR phase distribution
41
Putting It All Together
To compare different designs
Compare the voltage margin at given BER
Need to include all noise sources
Accurate ISI distribution
Transmit and receive jitter
CDR jitter
EQ quantization noise
Receiver offset
42
21
BER Contours
5 tap Tx Eq
5 tap Tx Eq + 1 tap DFE
150
150
-5
-5
100
-10
50
-15
0
-50
-20
-100
-150
0
20
40
60 80 100 120 140 160
time [ps]
margin [mV]
margin [mV]
100
-10
50
-15
0
-50
-20
-25
-100
-25
-30
-150
0
20
40
60 80 100 120 140 160
time [ps]
-30
Voltage margin
Min. distance between the receiver threshold and contours with same
43
BER
BER Contours
PAM2 DFE
150
100
-5
150
-10
50
-15
0
-50
-20
-10
100
50
-15
0
-50
-20
-100
100
150
-25
200
250
0
200
-5
margin [mV]
200
250
margin [mV]
250
PAM4 linear equalization
-150
-25
-200
40 80 120 160
time [ps]
-30
-250
0
40
80 120 160 200 240 280 320
time [ps]
-30
44
22
Model and measurements
0
log10(BER)
-2
-4
-6
-8
-10
-12
-14
80
60
40
20
0
-20 -40 -60 -80
Voltage Margin [mV]
PAM4, 3taps of transmit equalization, 5Gb/s,
26” FR4 channel
45
Attenuation [dB]
Example channels
0
-20
(b)
26" NELCO,
no stub
-40
-60
-80
26" FR4,
via stub
-100
0
5
10
15
20
frequency [GHz]
Legacy (FR4) - lots of reflections
Microwave engineered (NELCO)
V. Stojanović, A. Amirkhany, M. Horowitz, “Optimal Linear Precoding with Theoretical
and Practical Data Rates in High-Speed Serial-Link Backplane Communication,”
IEEE International Conference on Communications, June 2004
46
23
Capacity achieving bit loading
10
10
Multi-tone data rates with thermal noise
9
Capacity with thermal noise
8
Nelco 105Gb/s
7
Nelco 64Gb/s
FR4 38Gb/s
FR4 70Gb/s
6
#bits/Hz
#bits/Hz
8
5
6
4
4
3
2
2
1
0
0
5
10
15
frequency [GHz]
20
0
0
25
2
4
6
8
10
12
14
frequency [GHz]
Capacity is very big
Practical rates lower
low target BER<10-15
peak power constraint
Thermal noise – the smallest noise source
47
Capacity with link-specific noise
140
therm al noise
120
100
therm al noise and LC PLL
phase noise
80
FR4
Capacity [Gb/s]
Capacity [Gb/s]
NELCO
140
120
100
thermal noise
80
therm al noise and ring PLL phase noise
60
60
40
40
therm al noise and
ring PLL phas e noise
therm al noise and
LC PLL phase noise
20
20
0
-25
-20
log10(Clipping probability)
-15
-10
-5
0
0
-25
-20
log10(Clipping probability)
-15
-10
-5
0
Effective noise from phase noise
Proportional to signal energy
Decreases expected gains
Still, capacity is much higher than data rates in today’s links (3Gb/s)
48
24
NELCO
90
Data rate [Gb/s]
Data rate [Gb/s]
Multi-tone with integer bit loading
a) NELCO
80
thermal noise
70
60
50
thermal nois e and LC PLL
phase noise
40
80
70
60
thermal noise and LC PLL
phase noise
30
20
10
10
-20
the rm al noise
50
20
0
-25
b) FR4
40
therm al noise and ring PLL phase noise
30
FR4
90
log10(Clipping probability)
-15
-10
-5
0
therm al noise and ring PLL phase noise
0
-25
log10(Clipping probability)
-15
-10
-5
0
-20
Peak-power constraint introduces large gap penalty to
capacity (can go around with coding, but too expensive)
Still pretty high data rates
49
Multi-level: Offset and jitter are crucial
thermal noise
35
PAM16
30
PAM8
25
30
PAM8
25
20
PAM16
PAM4
15
20
25
20
PAM4
15
PAM2
PAM4
15
10
PAM2
10
PAM2
10
PAM8
5
5
0
0
30
Data rate [Gb/s]
Data rate [Gb/s]
Data rate [Gb/s]
45
40
thermal noise +
offset+
jitter
thermal noise +
offset
2
4 6
8 10 12 14 16 18 20
Symbol rate [Gs/s]
0
0
5
2
4
6
8 10 12 14 16 18 20
Sym bol rate [Gs/s]
0
0
2
4
6
8 10 12 14 16 18 20
Sym bol rate [Gs/s]
To make better use of available bandwidth, need better circuits
PAM2/PAM4 robust candidate for next generation links
50
25
Full ISI compensation too costly
thermal noise
+ offset
16
PAM4
14
12
20
20
18
PAM8
10
Data rate [Gb/s]
Data rate [Gb/s]
20
18
18
16
16
14
14
12 PAM16
PAM2
PAM4
12
10
10 PAM8
8
8
thermal noise
+ offset+ jitter
Data rate [Gb/s]
thermal noise
PAM2
8
6
6
4
4
4
2
2
0
0
0
0
6
2
4
6 8 10 12 14 16
Symbol rate [Gs/s]
PAM4
PAM8
PAM2
2
2
4
6 8 10 12 14 16
Sym bol rate [Gs/s]
0
0 2 4 6 8 10 12 14 16
Symbol rate [Gs/s]
Today’s links cannot afford to compensate all ISI
Limits today’s maximum achievable data rates
51
Conclusions
Backplane links limited by the channel
ISI is large in baseband links
Can’t completely compensate
(At least not with reasonable area/power)
Residual ISI also increases CDR jitter
Generally have low BER requirements
Accurate noise statistic important
Many of large noise source are bounded
Power constrained transmitter
PAM4 and PAM2 with simple DFE are attractive solutions
Still, capacity of these links is very big
Smart multi-tone?
52
26