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DesignCon 2010
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Statistical Simulation of Power
Supply Noise in Multi-Gigabit
Systems
Wendemagegnehu T. Beyene,
Amir Amirkhany
Aliazam Abbasfar
Rambus Inc.
4440 El Camino Real
Los Altos, CA 944022
Abstract
Authors Biography
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The use of deterministic techniques to evaluate the impact of simultaneous switching
output (SSO) noise on the performance of modern high-speed systems with tight timing
budget can be pessimistic. These can lead to conservative design, especially, in multigigabit systems with embedded coding or scrambling sub layer. To overcome the
shortcomings of conventional methodologies, a statistical simulation method of
evaluating the impact of SSO noise on high-speed single-ended signaling systems is
presented. The method correctly considers the spatial and temporal distributions of
switching activities of devices in the system to calculate the performance degradation of
the interface due to power supply noise.
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Wendemagegnehu (Wendem) T. Beyene received his B.S. and M.S. degrees in Electrical
Engineering from Columbia University, in 1988 and 1991 respectively, and his Ph.D.
degree in Electrical and Computer Engineering from University of Illinois at UrbanaChampaign, in 1997.
From 1988 to 1994, he was with the IBM, Microelectronics division, Fishkill, NY, where
he worked on design and electrical characterization of advanced multilayer packages.
From 1997 to 2000, he was with Hewlett-Packard Company and Agilent Technologies
EEsof EDA at Westlake Village, CA working on analog and RF circuit simulation tools.
In 2000, he joined Rambus Inc., Los Altos, CA and is currently a senior principal
engineer responsible for signal integrity of multi-gigabit memory and logic-to-logic
interfaces. His professional interests are in the general area of simulation and
optimization of deterministic and stochastic systems. Specific current interests include
efficient circuit simulation of large distributed networks, noise analysis of autonomous
circuits, and analysis of parameter variations in high-speed links.
Amir Amirkhany received the Ph.D. degree from Stanford University, Stanford, CA, in
2008, the M.Sc. degree from the University of California, Los Angeles, in 2002, and the
B.Sc. degree from Sharif University of Technology, Iran, in 1999, all in Electrical
Engineering.
Since July 2007, he has been with Rambus Inc., Los Altos, CA. From 2003 to 2007 he
was a Research Assistant with the VLSI group, Stanford University, where he was
involved with the design of chip-to-chip electrical links, in close collaboration with
Rambus Inc. From 2001 to 2002, he was with Sequoia Communications, Los Angeles,
CA, working on the ASIC design of WCDMA systems. His main research interests
include the design and implementation of communication systems, VLSI circuit design,
and application of communication and signal processing techniques to the design of low
power circuits.
Dr. Amirkhany was a recipient of a Best Student Paper Award at the IEEE Global
Communications Conference in 2006 for his work on the design and analysis of an
Analog Multi-Tone system for chip-to-chip interconnects.
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Aliazam Abbasfar received the B.Sc. (Highest Honors) and M. Sc. degree in Electrical
Engineering from University of Tehran, Iran in 1992 and 1995 and the Ph.D. degree in
Electrical Engineering from University of California Los Angeles (UCLA) in 2005.
Between 2001 and 2004 he held positions as a senior design engineer in the areas of
communication system design and digital VLSI/ASIC design with Innovics Inc., Sequoia
Communications Inc., and Jaalaa Inc. all in California. Upon graduation from UCLA he
joined Rambus Inc. where he is a Principal Engineer working on high-speed data
communications on wireline serial and parallel links.
He has published over 25 journal and conference papers and authored the book, "Turbo
codes: Design for high-speed decoding". He also holds 5 patents and more than 20
pending.
He is a Senior Member of the IEEE. He received the IEEE Communications Society &
Information Theory Joint Paper Award in 2008. He was the co-recipient of Best Student
Paper Award at IEEE Global Communications Conference in 2006, ``Analog Multi-Tone
Signaling for High-Speed Backplane Electrical Links''. His main research interests
include wireless and wireline communications, equalization, error correcting codes, and
VLSI for digital data communications.
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.
I. Introduction
As the signal switching becomes faster and the supply voltage drops with every new
process geometry shrink, power supply noise prediction becomes critical to insure the
signal integrity of the system When a large number of logic gates switches, the voltage
supply to the input/output (I/O) circuitry may fluctuate and these disturbances, referred as
Simultaneous Switching Output (SSO) noise, can cause undesired transient behavior
among output drivers, input receivers, or internal logic. Through the coupling between
the power and signal distribution systems, SSO noise causes false logic, degrades the
signal edge rate, and increases delay skew and signal overshoot or undershoot and jitter
[1]-[2]. Therefore, accurate determination of SSO noise in gigahertz applications has
been of critical importance to maximize bandwidth and minimize I/O power
consumption.
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In order to suppress the power and ground plane fluctuations, consequently SSO noise,
the Power Distribution Network (PDN) needs to be designed to provide a clean power
supply, at least to the more sensitive analog circuits such as a PLL. The PDN must also
provide a low impedance voltage supply and good return path to the devices. Low
impedance and constant voltage supply can be obtained from DC to few harmonics by
using decoupling capacitors. The decoupling capacitors provide an AC ground to the
noise. At medium and high frequencies, the impedance peaks can be suppressed using
large and small value decoupling capacitors. The low-frequency low impedance is
maintained using a regulated voltage supply. If the devices do not see a low-impedance
power supply at all frequencies, voltage spikes or droops occur on the power supply
terminals of the circuit when edge rates coincide with the high impedance of the power
supply. Additionally, if the PDN does not provide low-coupling at all frequencies among
devices, the spikes or droops caused by one device affect the neighboring devices. These
limit the maximum number of active devices that can simultaneously transmit for reliable
operation.
A special concern for the power supply design of high-speed I/O systems is the packagechip resonance between the inductance of the package solution and the local capacitance
on the chip [1]-[2]. This resonance, which typically occurs at medium frequencies around
50 MHz to 300 MHz, generates a large increase in the impedance of the PDN and can
cause significant supply noise in this frequency range. The inductance causing this
resonance is generated by the power supply system inside the package in combination
with the decoupling solution on the PCB. This inductance should be as small as possible
to reduce the supply impedance in this medium frequency range. Therefore, minimizing
the power supply inductance of the package is a major design goal for high-speed I/O
systems.
The supply noise is directly proportional to the impedance of the power supply system.
The resulting noise can easily be calculated as the product of the current spectrum and the
impedance of the power supply network. A typical current profile and an impedance of
the power supply network are shown in Figure 1. The impedance shows small
amplitudes at low and high frequencies, but shows a large amplitude peak at medium
frequencies, where the inductance of the package system resonates with the on-chip
capacitors. Consequently, the magnitude of the current noise spectrum at this medium
frequency also plays critical role in determining the magnitude of the supply noise.
=
*
FFT
Supply
Current
Power supply
Supply
Current noise
noise spectrum
impedance
Voltage noise
Figure 1: High-speed power supply noise and PDN impedance.
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Therefore, the impact of SSO noise in high-speed system can be reduced by making
changes to the supply noise, the noise spectrum, or to the power supply impedance. The
power supply impedance can be reduced in the medium frequency range by reducing the
inductance of the package and by placing decoupling capacitors placed very close to the
chip. Increasing the on-chip decoupling capacitance can be critical in reducing the highfrequency supply noises. Controlling the slew rate of signals or using coding such as data
bus inversion (DBI) or other variants can also be used to reduce the overall di/dt noise.
These solutions may have limited impact due to increase in system cost or complexity.
The switching activities of the transmitters can be randomized to reduce the worst-case
supply noise or shape the noise spectrum. If the likelihood of the worst case SSO is low,
lower than the target Bit Error Ratio (BER), the SSO noise does not affect the
performance of the system.
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The time-domain simulation of the complete system that combines the circuit model of
the PDN and channel is required to evaluate the impact of supply noise on the signal
integrity of the high-speed interface. The calculation of BER using time-domain
simulation is very time consuming. It is almost impossible to calculate at lower BER with
high confidence using conventional circuit simulation techniques. In addition, current
high-speed interfaces employ complex circuitries and digital processing components such
as a pre-emphasis filter for the transmitter and a decision feedback equalizer for the
receiver to mitigate channel impairment such as inter symbol interference (ISI). Since
Synchronizing circuits responses to small deviations in voltage and time can be
significant, the behaviors of these complex circuitries need to be accurately modeled.
Therefore, the time-domain simulation of high-speed channels, PDN with these
circuitries is no longer tractable even for BER of 1E-12.
An alternative approach is to use a system simulation approach by modeling the
components in a link as blocks whose behaviors are described by higher-level languages
such as MATLAB, Verlog-A, or NumPy (Python) [3]. The channel behavior is
characterized through an ISI probability density function (pdf) or probability mass
function (pmf) that is analytically derived from the channel characteristic functions. The
pdf of the channel ISI is commonly built from the channel pulse or step responses. Then,
the ISI eye is constructed by calculating the pdf at multiple sampling points of the
channel response within one unit interval. The statistical eye is constructed by combining
the ISI eye with the device noise. It gives the BER over voltage and time offsets. Thus,
instead of performing the time-domain simulation by solving the system equation at each
discrete time, the BER is efficiently calculated by convolving together the pdf's or the
pmf's of the various blocks in the links. It is important to note that this statistical approach
is based on superposition and therefore relies on the linearity of the system. A tutorial and
a summary of the recent development in statistical simulation of transmission channels
are presented in [3].
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Similar statistical simulation approach can be used to analyze the impact of SSO noise in
the signal transmission of high-speed bus. The approach can provide a more realistic
prediction of SSO noise impact on the performance of high-speed systems with tight
voltage and timing margins. It also provides more efficient method of analyzing power
supply noise and signal propagation than the conventional and time-intensive
deterministic methods. In Section II, the assumption and theory behind method are
discussed. Then, a high-speed signaling example is given and the result from
deterministic and statistical approaches is compared in Section III.
II. Method
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The physical implementation of a single-ended signaling, pseudo-open drain logic
(PODL), is shown Figure 2. A single-ended signaling bus generates significant SSO
noise, if no mitigating factor such as DBI or other coding is implemented in the design of
the interface. Figure 3 shows an interface bus with the PDN. When the transmitters send
data, the logic gates switches and the voltage supply to the input/output (I/O) circuitry at
locations (1, 2, n) on PDN fluctuate. These noise sources at the PDN coupled through the
termination and Ron and generate noise and jitter at the receiver of the devices, i.
VDDQ
VDDQ
Channel
Vref
Figure 2: A single-ended signaling system.
n
2
xn
1
x2
i
x1
Vref
Figure 3: Power supply network and SSO sources.
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The impact of SSO noise on the signal transmission can be characterized using an
impulse response between any arbitrary noise source (location) on the PDN and the
receiver. Thus, a family of single-bit (pulse) responses can completely describe the
impact of all SSO noise sources on the performance of a signaling system.
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When a single bit is transmitted from the driver to the receiver, the transfer characteristics
between the n noise sources on the power supply network and the m receivers are
captured by the bit (pulse) response hij, where (i,j) are the observation and source
locations of the noise waveforms. This relation is described by.
ED
⎡ y1 ⎤ ⎡ h11
⎢ y ⎥ ⎢h
⎢ 2 ⎥ ⎢ 21
⎢ M ⎥ ⎢ M
⎢ ⎥=⎢
⎢ yi ⎥ ⎢ hi1
⎢ M ⎥ ⎢ M
⎢ ⎥ ⎢
⎢⎣ y m ⎥⎦ ⎢⎣hm1
h12
h22
O
hi 2
O
hm 2
L h1n ⎤ ⎡ x1 ⎤
L h2 n ⎥⎥ ⎢⎢ x2 ⎥⎥
O M ⎥ ⎢M⎥
⎥ ⊗ ⎢ ⎥,
L hin ⎥ ⎢ xi ⎥
O M ⎥ ⎢M⎥
⎥ ⎢ ⎥
L hmn ⎥⎦ ⎢⎣ xn ⎥⎦
(1)
where xj is transmitted binary data stream and yj is the noise waveforms at the receiver.
To calculate the impact of SSO noise at a receiver, i, Equation (1) reduces to :
n
yi = ∑ hij ⊗ x j .
(2)
j =1
In the conventional deterministic (synchronized) SSO noise analysis, all xj's are switching
together. In other words, xj=x for all j, where x is a binary data stream. This type of
analysis assumes a worst case scenario when all the bit slices can switch together over
several consecutive bit periods. However, the chance of transmitting identical bit
sequence over a 32-bit interface is small. The probability of transmitting n-identical bits
on 32-bit wide interface is listed in Table I. The chances of transmitting worst-case
sequence of bits even for as short instance as 3 UI is a very unlikely event with a
probability of p=1.25E-29. Thus, this worst case scenario, which is often considered over
much larger simulation times, is allowing for a very unlikely event in the analysis that
results in pessimistic prediction of the SSO noise impact in high-speed signaling. To be
realistic, when designing high-speed links for a certain bit-error rate, the probability of
the bit sequences causing eye closure should be included in margining the link, in the
same way that ISI and jitter are included in bathtub curves [4].
p
2.3283e-10
7.4506e-9
1.1548e-7
1.1548e-6
8.3726e-6
:
0.0024
:
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n
0 or 32
1 or 31
2 or 30
3 or 29
4 or 28
:
8 or 24
:
0.0809
0.1098
0.1317
0.1399
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13 or 19
14 or 18
15 or 17
16
Table I : Probability (p) of n devices switching in 32-bit interface.
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The impact of the power supply noise at any receiver for an arbitrary bit sequences, xj's,
can be obtained by using the Equation (2). The evaluation of the equation for arbitrary
long bit pattern can be computationally intensive. If the noise sources are located very
close to each other as compared to the observation point, i , the noise transfer functions of
observation point with respect to various noise sources are approximately the same,
hi = hij , for all j . Then, Equation (2) further reduces to :
yi = hi ⊗ x ,
(3)
where x is the set of transmitted random data stream on the bus.
This SSO characteristic function, hi , can also be simulated or measured by selecting and
holding nearby data bits low or high while the data drivers in the interface switching. The
SSO generated on the power supply grid is coupled through the termination and driver
Ron into the signal nets. Then, the waveform at the receiver of the selected quiet bits is
measured. A typical characteristic response, hij, is shown in Figure 4.
-4
x 10
magnitude
2
1
0
-1
-2
0.5
1
1.5
2
3
-9
x 10
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time (sec)
2.5
Figure 4: A typical response to characterize supply noise.
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If the data pattern that each driver transmit is independent and the bit sequences are
random, or the probability distribution of the bits switching behavior are known, the
calculation of the impact of the SSO noise at the receiver can be dramatically improved.
If we assume that each driver switches independently from low to high and from high to
low with identical probability, then, the two possible outcomes (0 can represents the
switching from low to high and high to low) can be modeled by Bernoulli random
variables with p=0.5. Figure 5 shows a block diagram of high-speed system with data
scrambling. The scrambling logic can be implemented using linear shift register (LFSR)
[5]. The LFSR produces a pseudo-random number sequence. The pseudo-random
sequence and data passes through an exclusive-OR (XOR) to produce scrambled data. At
the receiver, the original data is recovered by XORing the received signal with the
pseudo-random pattern from the LFSR that operate in lock step. Synchronization of
LFSRs is required to successfully recover the original transmitted data. This is
accomplished by guarantee the LFSRs have identical initial states.
Figure 5: A block diagram of high-speed system with data scrambling.
The n-bit LFSR with initialization is depicted in Figure 6. The LFSRs sequence through
(2n-1) states, where n is the number of the register in the LFSR. At each clock, the
contents of the registers are shifted to the right one position. The feedbacks from
predefined registers to the leftmost register pass through an XOR or exclusive-OR
(XNOR) gate. The input seeds are used to determine the initial states of the LFSR.
Depending on the implementation of the LFSR, these seeds cannot have a value of all
zeros or ones to avoid lock up of the counter.
2
…
3
n-1 n
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1
Initial states
Figure 6: An n-bit LFSR with initial state settings.
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The transmitted sequence in high-speed system with scrambling capabilities can be
assumed to be independent. If the random variables, xi …xn, are assumed to be both
independent and identically distributed (i.i.d.), then the sum of all drivers switching
behavior can be represented by the sum of the Bernoulli(p) random variables,
x = x1 + x2 + L + xn . The resulting random variable, x , is called a Binomial(n,p) random
variable and it describes the switching behavior of the n-bit bus. The distributions of each
Bernoulli(p) variable, x = x1 , x2 , L , xn , and their sum, Binomial(n,p) variable, X , are
shown in Figure 7. If the transmitters are driven by independent randomized bit pattern,
the resulting switching behavior on n-bit interface can be represented by a Binomial
random variables and the pmf is written as,
⎛n⎞
X (k ) = ⎜⎜ ⎟⎟ p k (1 − p) n−k , k = 0, L , n.
⎝k ⎠
X1
X2
X3
(4)
X
0.5
*
0
1
* …*
0
1
0
1
0
n
Figure 7: The pmf distributions of each data line and the resulting distribution of the interface.
Using the SSO characteristic functions of Equation (1) and the probability distribution of
the switching of data or drivers in the interface, accurate prediction of the impact of the
SSO noise can be performed. Equation (3) can be further rewritten to show that each Yi
sample is a summation of some independent random variables whose pmf is scaled
version of X . First, the convolution in Equation (3) can be written as,
yi (k ) = ∑ hi (l ) ⊗ x (k − l ).
(5)
l
Then, the distribution of Yil can be written as,
⎛ υ ⎞
⎟⎟ .
Yil (υ ) = X ⎜⎜
⎝ hi (l ) ⎠
(6)
Since Yil’s are independent, the Yi is given by
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Yi = Yi1 ⊗ Yi 2 ⊗ LYil ⊗ L .
(7)
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For the high-speed interface described in the next Section, the probability distribution of
the SSO noise impact at the receiver is calculated. Figure 8 shows the SSO noise impact
using randomized and synchronized (worst-case) switching of data drivers. The SSO
impact of the synchronized switching is significantly higher and saturate at relatively
higher BER. The assumption of synchronized switching leads to very pessimistic results
compared to randomized switching because the former ignores the probability of the
synchronizes switching happening at the transmitter. The impact of maximum of 16 and
32 data drivers for randomized switching are shown in Figure 9. It can be gleaned form
this graph that the improvement of SSO noise using coding such as DBI and randomizing
data switching varies as a function of BER.
Figure 8: Synchronized and randomized switchings
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Figure 9: Randomized switching of 16 and 32 devices.
III. Results
dB(insertion loss)
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To compare the SSO simulation techniques, a multi-gigabit chip-to-chip interconnect
system with 32-bit wide bus is analyzed. The system uses single-ended PODL signaling.
The power system is modeling using one of the conventional methods described in [1][2]. The insertion loss of the channel is shown in Figure 10. Since the signal attenuation
of the channel is over 15 dB at Nyquist data rate, it is critical for reliable transmissions
the use of equalization techniques.
Figure 10: The insertion loss of the high-speed channel.
0.25 0.5 0.75 1.0 1.25
Time [UI]
1.5
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-0.5 -0.25 0
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Voltage [mV]
The time-domain simulation of the interface is performed by combining the circuit model
of the power plane with signaling channel. The responses of the system to pseudorandom binary sequence excitations are also shown in Figure 11. The eye diagram
significantly opens when equalization techniques are applied in series to the channel as
shown in Figure 12. Figure 13 shows the performance predictions using deterministic
and statistical simulation techniques. Figure 14 shows significantly wider eye opening
than that of the deterministic prediction of Figure 13.
Voltage [mV]
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Figure 11: Received eye diagram of the channel before equalization.
-0.5 -0.25 0
0.25 0.5 0.75 1.0 1.25
Time [UI]
1.5
Figure 12: Received eye diagram of the channel after equalization.
Voltage [mV]
-0.5 -0.25 0
0.25 0.5 0.75 1.0 1.25
Time [UI]
1.5
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Voltage [mV]
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Figure 13: Received eye diagram with SSO noise from synchronized switching.
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-0.5 -0.25 0
0.25 0.5 0.75 1.0 1.25
Time [UI]
1.5
Figure 14: Received eye diagram with SSO noise from randomized switching.
Once the distributions of deterministic and random noises are determined, ths SSO noise
distribution is integrated into a behavior simulation tools to perform system-level analysis
in similar factions as described in [3]. The bounded distributions of the SSO noise, ISI,
and crosstalk (Xtalk), and the bounded and unbounded device noise and jitter are
combined to generate the probability distribution or BER of the overall system as a
function of time or voltage. The noise and jitter of the devices and sensitivity and
bandwidth of the receiver and the channel characteristics are combined with the SSO
noise to calculate the BER as shown conceptually in Figure 15.
×
×
Supply network
SSO noise
Channel
ISI & Xtalk
System
Performance
Device
Jitter & noise
Figure 15: The conceptual intergration of SSO noise, ISI,
distributions to generate system probability or BER.
Xtalk, and device noise and jitter
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The BER curves of the complete system as a function of voltage and time are shown is
shown in Figures 16 and 17, respectively. The curves labeled c and d show the system
margin degradation due to only SSO noises if the channel were ideal (no attenuation).
The SSO noise using randomized switching reduces the voltage margin of the system by
50 mV, while the synchronized switching reduces the margins by more than 150 mV.
Similarly, the timing margins reduction for randomized and synchronized switching are
almost 0.2 UI and 0.4 UI, respectively. The equalized channel, curves labled e, without
consider any SSO noise show a voltage and timing margins over 250 mV and 0.5 UI,
respectively. When combining the signal channel and SSO noise effects, the overall
voltage and timing margins for the randomized switching, curves labled f, show
significantly larger margins for the synchronized switching, curves labled g.
Figure 16: BER of the high-speed interface
IV. Summary
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Figure 17: BER of the high-speed interface
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The statistical modeling of SSO noise for high-speed system is presented. The
deterministic simulation techniques give worst-case results that often result in very
conservative designs as it ignores the probability of the synchronized switching
happening at the transmitter. As a result, the voltage and timing margins of gigabit
signaling systems using the two approaches give significantly different answers. As
current high-speed systems have architectural constraints that minimize or remove the
simultaneously switching of large number of drivers for several consecutive switching,
the proposed statistical simulation can predict a real impact of SSO noise and give a more
practical SSO noise limits to high-speed systems with and without embedded coding or
scrambling blocks. The method can easily be integrated to the existing statistical
simulation techniques that are currently used to analyze high-speed channels.
References
[1] M. Swaminathan and E. Engin, Power Integrity Modeling and Design for
Semiconductors and Systems, Prentice Hall, Boston, MA 2007.
[2] I. Novak and J. R. Miller, Frequency-Domain Characterization of Power
Distribution Networks, Aretech House, Inc., Norwood, MA 2007.
[3] D A. Sanders, ``Statistical simulation of physical transmission media,'' IEEE Trans.
on Advanced Packaging, Vol. 32, No. 2, pp. 260-267, May 2009.
[4] W. T. Beyene, A. Amirkhany, A. Abbasfar, “Statistical Simulation of Power Supply
Noise in Multi-Gigabit Systems ,” in the Proceedings of IEEE 18th Topical Meeting on
Electrical Performance of Electrical Packaging and Systems (EPEPS), Portland, OR,
October 19-21, 2009.
[5] C. P. Mozak, “Suppressing power supply noise using an LFSR pseudo random
scrambling process,” UK Patent Application, GB 2453259