Study of n-channel MOSFETs with an enclosed-gate
layout in a 0.18 micron CMOS technology
Li Chen and Douglas M. Gingrich
Abstract— Enclosed-gate layout MOSFETs with guard rings
have been fabricated in a commercial 0.18 micron CMOS technology. The static, signal, and noise performance of the MOSFETs
were determined before and after being subjected to ionizing
radiation. The transistor design could provide the basis for lownoise radiation-tolerant circuits.
I. I NTRODUCTION
D
ESIGNERS of application specific integrated circuits
(ASICs) must continue to follow the trend in device
scaling of commercial CMOS technologies or face process obsolescence. By using the most advanced technologies, designers
can profit from the advantages of high speed, reduced power
consumption, high level of integration, high volume production,
high yield, and consequently low cost. With each technology,
it is important to fabricate single-transistor test devices to
parameterize new effects – like short-channel effects in deep
submicron technologies – and study the tolerance of the devices
to radiation.
For 0.25 µm and smaller technologies, radiation induced
threshold voltage shifts become negligible even at very high
doses [1], [2]. However, due to positive charge trapping, ionizing radiation may induce an inversion layer at the bird’s beak
or shallow trench corner, giving rise to various leakage current
paths from the drain to the source. In addition, thick oxides
are still present in the isolation regions of CMOS components
and can be quite sensitive to radiation damage, causing leakage
current paths from one transistor to another.
These current paths have to be eliminated by special layout techniques. Enclosed-gate MOSFETs prevent any leakage
current through a radiation induced lateral path under the
bird’s beak or at the shallow trench corner. Neighboring n+
implantations can be separated by p+ guard rings to prevent
leakage currents between components.
Enclosed-gate layout MOSFETs, along with guard rings, in
0.25 µm technologies have been very successful in providing
resistance to extremely high levels of ionizing radiation [3],
[4], [5], [6]. The main drawbacks of enclosed-gate MOSFETs
are slower switching times, due to the larger input capacitance
than in standard layouts, and the larger area consumption of
Li Chen was with the Department of Electrical and Computer Engineering,
University of Alberta, Edmonton, AB T6G 2V4 Canada. He is now with the
Department of Electrical and Computer Engineering, South Dakota School of
Mine and Technology, Rapid City, SD 57701 USA.
Doug Gingrich is with the Centre for Subatomic Research, University of
Alberta, Edmonton, AB T6G 2N5 Canada and TRIUMF, Vancouver, BC V6T
2A3 Canada (e-mail: gingrich@ualberta.ca).
the enclosed-gate geometry. These drawbacks can be partially
compensated by using aggressive CMOS technologies, such as
sub-quarter-micron technologies.
While enclosed-gate layout MOSFETs are starting to be used
for ASICs in 0.13 µm technologies [7], to our knowledge
single-transistor studies in technologies smaller than 0.25 µm
have not yet been reported. The aim of this paper is to
evaluate enclosed-gate layout MOSFETs in a 0.18 µm CMOS
technology in view of them being implemented in low-noise
radiation-tolerant ASICs. We report on the static, signal, and
noise performance of devices with various gate sizes which
have been exposed to ionizing radiation.
II. E XPERIMENTAL D ETAILS
A. Enclosed-Gate Transistor Design
MOSFETs were made using a technology with 0.18 µm
minimum gate length and 4 nm oxide thickness manufactured
by TSMC (Taiwan Semiconductor Manufacturing Company
Ltd.) and supplied through collaboration with PMC-Sierra. The
technology was a single polysilicon, six metal layer, silicide
CMOS process. Nothing has been done by the foundry to
harden the gate or field oxides against radiation.
n-channel MOSFETs were made using an enclosed-gate
layout and p+ guard rings. The well-studied square layout
with corners cut at 45◦ (broken corners) was chosen for the
enclosed-gate geometry, and is shown in figure 1. In a 0.25 µm
technology, the effective aspect ratio has been found to be well
estimated by using an effective three-transistor model giving
the following formula [3], [8]:
W
L
eff
=
+
4
3
2α
d
ln d −2αL
eff
d−d
2
Leff
,
+ K 1√
2
α2
1−α
+ 2α + 5 ln α1
(1)
√
where d = d − 2c, and c, d, L, and α are
√ shown in figure 1.
We have used d = 0.54 µm and c = 0.1/ 2 ≈ 0.07 µm.
K is a geometry dependent parameter, used to take into
account the polysilicon strip (A in figure 1) necessary to
integrate the gate contact outside the thin gate oxide region.
Since the polysilicon strip hides part of one of the T2 transistors
in figure 1, the value of K will vary between 7 and 8
depending on the relative transistor length and the width of
the polysilicon strip. We choose a continuous value of K given
by K = 8 − A/L, where A = 0.18 µm is the width used
0-7803-8701-5/04/$20.00 (C) 2004 IEEE
A
Source or Drain
T1
c
T2
T3
T2
αL
L
Drain or Source
d
d’
Gate
oxide will push the n-substrate or n-well more into accumulation without danger of the formation of an inversion layer.
To provide measurable currents, 50 enclosed-gate transistors of
each size were connected in parallel. To reduce the number
of pins on the package, the substrate was tied to the source
for each enclosed-gate transistor. Five parts of this device were
fabricated.
A second device was made mainly to extract the aspect
ratio of the enclose-gate transistor and test the validity of
equation 1. Enclose-gate transistors and standard transistors
were made with identical gate lengths. The widths of the
standard transistors were chosen to be close to the predicted
widths of the enclose-gate transistors. Because of die-size
restrictions, the parts were bonded in two different ways. Only
enclose-gate or standard transistors, but not both, could be used
in any part. Ten parts of each bonding type were fabricated.
C. Measurement Setup
Source or Drain
Fig. 1. Enclosed-gate transistor shape. The enclosed-gate transistor can be
thought of as being formed from three different kinds of transistors in parallel:
T1, T2, and T3.
for the polysilicon strip. In our case, K ranges from 7.14 for
L = 0.21 µm to 7.94 for L = 3 µm. The value of K only
becomes important in estimating the effective aspect ratio at
large values of L.
α is a fit parameter which identifies the boarder between the
effective transistors represented by the first and second terms
in equation 1. It is not possible to a priori know the value of
α but its value has been found to be 0.05, almost independent
of CMOS technologies ranging from 2.5 µm to 0.25 µm [8].
For this value of α, and our values of d and c, the model is
only valid for transistor lengths less than 4.40 µm and aspect
ratios greater than 2.23.
Leff is used in formula 1 to take into account the gate
length shortening due to underdiffusion, photolithography, and
etching. We were unable to measure Leff in a direct way. We
assume that it will be somewhere between the mask channel
length, Lm , and the metallurgical channel length, Lm − 2LD ,
where LD ≈ 0.014 µm is the length of the lateral diffusion of
the source or drain region. We estimate the effective channel
length to be halfway between the two extreme values with error
LD .
B. Test Devices
We have made two test devices consisting of different size
enclosed-gate transistors. The first test device consisted of
n-channel enclosed-gate MOSFETs of six different channel
lengths. We did not make p-channel MOSFETs with enclosed
gates, since in this case the positive charge accumulated in the
Measurements of the static and signal parameters of the
MOSFETs were made using an Agilent 4155A semiconductor
parameter analyzer. For each test device and each transistor
size, the drain current, ID , as a function of the gate-to-source
voltage, VGS , for drain-to-source voltages of 0.05 V and 1.0 V,
and drain-to-source voltage, VDS , for gate-to-source voltages
of 0.5, 0.6, 0.7, 0.8, 0.9 V was measured.
An Agilent 8593E spectrum analyzer was used to measure
the gate-referred voltage noise spectra of the transistors [9]. The
system was based on converting the noise current at the drain
to a voltage by a transimpedance amplifier and by referring the
voltage noise spectrum back to the gate.
D. Irradiation Procedure
The devices were irradiated with an x-ray generator operating
at a constant electron accelerating potential of 320 kVp and a
tube current of 10 mA. The machine was capable of exposure
rates of up to about 35 R/s. The absorbed dose rate at the die of
the device under test was estimated to be (48±3) cGy(SiO2 )/s.
Irradiations were carried out in five steps. During each step,
the devices were biased in the worst-case conditions, that is,
with 1.8 V (maximum voltage allowed by the technology) on
the gate relative to source, drain, and body. Device parameters
were measured at the end of each irradiation step.
III. R ESULTS AND D ISCUSSION
A. Aspect Ratio Determination
We have extracted the aspect ratio of the enclosed-gate
transistors by measuring the ratio of the drain current of a
standard transistor to the drain current of an enclosed-gate
transistor of the same length. This ratio will be constant if
it only depends on the aspect ratios of the two transistors.
However, other transistor parameters may differ between the
enclosed-gate and standard transistors. To avoid differences in
these other parameters, we have chosen to calculate the ratio
at a drain-to-source voltage of 0.05 V, where the effects of
0-7803-8701-5/04/$20.00 (C) 2004 IEEE
0.16
Channel Length Modulation (1/V)
channel modulation should be small. We also choose a value
of the gate-to-source voltage in which the current ratio was as
constant as possible. At these voltage values, the current ratio
will depend only on the ratio of aspect ratios, which can be
used to extract the aspect ratio of the enclosed-gate transistor.
A plot of the enclose-gate transistor aspect ratio versus
channel length is show in figure 2. Also shown in figure 2
is a fit to the model of the aspect ratio in equation 1. The
results of the fit gave α = 0.056 ± 0.001. If we also take
LD to be a free parameter, we obtain α = 0.057 ± 0.001
and LD = (0.005 ± 0.002) µm, for χ2 /ndf = 2.87/3. The
agreement between the formula and the measured values are
very good.
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0.5
1.0
1.5
2.0
Gate Length (µm)
2.5
3.0
Fig. 3. Channel length modulation versus gate length for VGS = 0.9 V.
The open circles are for standard-geometry transistors, the opens squares for
enclosed-gate transistors with the drain inside the gate, and the solid squares
for enclosed-gate transistors with the drain outside the gate.
12
10
Aspect Ratio
8
0.05 V. The upper curve was before irradiation and the lower
curve after an absorbed dose of 71 kGy(SiO2 ). Above a gateto-source voltage of zero there was no detectable difference due
to radiation.
6
4
2
-5
10
0
0.5
1.0
1.5
2.0
Gate Length (µm)
2.5
3.0
-6
10
-7
B. Channel Length Modulation
Drain Current (A)
10
Fig. 2. Extracted aspect ratio versus gate length. The curve is a fit to the data
with α and LD as free parameters.
-8
10
-9
10
-10
10
-11
10
For enclosed-gate transistors, the output conductance in the
saturation region is different if the inner or outer diffusion
region is chosen as the drain. Using the SPICE level-1 definition
of the channel length modulation parameter, λ, figure 3 shows
the channel length modulation for enclosed-gate transistors
when the inner or outer diffusion region is chosen as the drain.
Also shown in figure 3 is the channel length modulation for
standard-geometry transistors. There is a clear asymmetry in
the channel length modulation, which is lower when the drain
is outside the gate.
C. Enclosed-Gate Transistor Parameter Extraction
During the measurements of the enclosed-gate transistor
characteristics, several problem transistors were identified.
These devices were probably damaged during testing and
handling since we have not implemented ESD protection. Nine
enclosed-gate transistors have been removed from our total
sample of 30 transistors, and are not included in any of the
analysis.
Figure 4 shows the behavior of the drain current as a function
of the gate-to-source voltage for a drain-to-source voltage of
-12
10
-13
10
-0.5
0.0
0.5
1.0
Gate Voltage (V)
1.5
Fig. 4. Drain current for an L = 1 µm enclosed-gate transistor as a function
of the gate-to-source voltage before irradiation and after an absorbed dose of
71 kGy(SiO2 ). The measurements were made with a drain-to-source voltage
of 0.05 V.
Before irradiation the threshold voltage was measured for
each enclosed-gate transistor. The mean and rms deviation
for each threshold voltage is shown in table I. The average
threshold voltage was (399±4) mV. Figure 5 shows the change
in threshold voltage as a function of the absorbed dose for
each enclosed-gate transistor. There was no significant change
in threshold voltage up to an absorbed dose of 71 kGy(SiO2 ).
The effect of interface states can be distinguished from that
of oxide traps by analyzing the subthreshold slope of the ID
versus VGS curve. Before irradiation the subthreshold slope
was measured for each enclosed-gate transistor in the linear
region (0.1 < VGS < 0.35 V). The mean and rms deviation of
the subthreshold swing (inverse of the subthreshold slope) for
0-7803-8701-5/04/$20.00 (C) 2004 IEEE
L
(µm)
3.00
2.00
1.50
1.00
0.50
0.21
VT
(mV)
393 ± 3
388 ± 4
381 ± 1
402 ± 4
398 ± 5
430
Subthrehsold Swing
(mV/decade)
81.9 ± 0.2
82.0 ± 0.2
82.0 ± 0.5
81.0 ± 0.2
81.2 ± 0.5
83.0
Leakage Current
(nA)
0.014 ± 0.020
0.008 ± 0.010
0.004 ± 0.001
0.011 ± 0.015
0.010 ± 0.006
0.006
6
∆ Subthreshold Swing (mV/decade)
TABLE I
T HE MEAN AND RMS OF THE THRESHOLD VOLTAGE , VT , SUBTHRESHOLD
SWING , AND LEAKAGE CURRENT FOR EACH ENCLOSED - GATE TRANSISTOR .
5
4
3
2
1
0
-1
-2
0
15
10
20
30
40
50
Dose (kGy(SiO2))
60
70
80
10
Fig. 6. Change in subthreshold swing as a function of the total absorbed dose.
The solid circles are for L = 3 µm, the solid squares for L = 2 µm, the solid
triangles for L = 1.5 µm, the open circles for L = 1 µm, the open squares
for L = 0.5 µm, and the open triangles for L = 0.21 µm.
0
-5
-10
40
-15
30
-20
0
10
20
30
40
50
Dose (kGy(SiO 2))
60
70
80
Fig. 5. Change in threshold voltage, ∆VT , as a function of the total absorbed
dose. The solid circles are for L = 3 µm, the solid squares for L = 2 µm,
the solid triangles for L = 1.5 µm, the open circles for L = 1 µm, the open
squares for L = 0.5 µm, and the open triangles for L = 0.21 µm.
∆ Leakage Current (pA)
∆ VT (mV)
5
20
10
0
-10
each enclosed-gate transistor is shown in table I. The average
subthreshold swing was (81.8 ± 0.4) mV/decade. Figure 6
shows the change in subthreshold swing as a function of the
absorbed dose for each enclosed-gate transistor. There was no
significant change in subthreshold swing up to an absorbed dose
of 71 kGy(SiO2 ).
Before irradiation the leakage current was measured for each
enclosed-gate transistor. We define the leakage current as the
drain current when the gate-to-source voltage is zero and the
drain-to-source voltage is 1.0 V. The mean and rms deviation
of the leakage current for each enclosed-gate transistor size
is shown in table I. The average leakage current was 9 pA.
Figure 7 shows the change in leakage current as a function of
the absorbed dose for each enclosed-gate transistor. There was
no significant change in leakage current up to an absorbed dose
of 71 kGy(SiO2 ).
A plot of the transconductance, gm = ∂ID /∂VGS , at a drainto-source voltage of 0.05 V for an enclose-gate transistor of
channel length 1 µm is shown in figure 8. Shown in figure 8 is
the transconductance before irradiation and after an absorbed
dose of 71 kGy(SiO2 ). There was no detectable change due to
radiation.
D. Noise Measurements
The noise performance of a CMOS device can be characterized in terms of the gate-referred noise power spectral density,
-20
0
10
20
30
40
50
Dose (kGy(SiO2))
60
70
80
Fig. 7. Change in leakage current as a function of the total absorbed dose.
The solid circles are for L = 3 µm, the solid squares for L = 2 µm, the solid
triangles for L = 1.5 µm, the open circles for L = 1 µm, the open squares
for L = 0.5 µm, and the open triangles for L = 0.21 µm.
Se (f ), which is modeled by means of the equation [10], [11],
[9]
Se2 (f ) =
2
vin
2
2
= SW
+ S1/f
(f ).
∆f
(2)
The first term is the white noise or thermal noise, and the
second term is the 1/f or flicker noise. The second term is
the noise due to the channel current and can be expressed as
2
(f ) =
S1/f
2
v1/f
∆f
=
Ka
1
,
2 WL fα
Cox
(3)
where α is a parameter close to 1, Ka is an intrinsic technology
dependent parameter which expresses the noise characteristics
of the process, and Cox is the gate capacitance per unit area. Ka
should be constant for devices of a given process with different
values for n- and p-channel transistors.
The white noise is determined by the channel thermal noise,
bulk resistance thermal noise, and gate resistance thermal noise.
0-7803-8701-5/04/$20.00 (C) 2004 IEEE
0.7) × 10−27 C2 /m2 . A systematic decrease of Ka of about
6% was observed after irradiation, but this was well within the
errors of our measurements. The white noise, SW , component
√
Hz was
depends on the transconductance. A value of 1.7 nV/ √
observed in strong inversion and a value of 6.4 nV/ Hz in
medium inversion. A systematic decrease of up to 11% was
observed after irradiation.
Transconductance (µA/V)
14
12
10
8
6
IV. C ONCLUSION
4
2
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Gate Voltage (V)
1.4
1.6
1.8
Fig. 8. Transconductance for an L = 1 µm enclosed-gate transistor as a
function of gate-to-source voltage before irradiation and after an absorbed dose
of 71 kGy(SiO2 ). The measurements were carried out with a drain-to-source
voltage of 0.05 V.
The channel thermal noise is due to the random thermal motion
of the carriers in the channel, and depends on the transconductance, gm , and the bulk small-signal transconductance, gmb .
Figure 9 shows the noise spectral density of an enclosed-gate
transistor of channel length 1 µm before irradiation and after
an absorbing dose of 29 kGy(SiO2 ). The noise measurements
were taken with a gate-to-source voltage of 0.6 V, in both strong
inversion, VDS = 0.7 V, and medium inversion, VDS = 0.1 V.
Although a slight decrease was observed after irradiation, it
was insignificant.
10
Noise (nV/ Hz)
V DS = 0.1 V
V DS = 0.7 V
1
4
10
5
10
Frequency (Hz)
6
10
Fig. 9. Input-referred noise voltage spectral density for an L = 1 µm enclosedgate transistor. The upper dark lines are before irradiation and the lower light
lines are after an absorbing dose of 29 kGy(SiO2 ). The measurements were
carried out with a gate-to-source voltage of 0.6 V, and drain-to-source voltages
of 0.1 V and 0.7 V.
Fits to the noise spectra using equation 2 have allowed us
to extract the white noise and flicker noise contributions. An
α parameter in equation 3 of about 0.8 was favored. Since
the data was limited in the high-frequency range, we have set
α = 1 in the subsequent fits. Ka in equation 3 was constant for
different bias conditions and found to have a value of (7.0 ±
We have designed radiation tolerant transistors in a commercially available 0.18 µm CMOS technology. The thin gate
oxide of the technology provides natural resistance to threshold
voltage shifts due to ionizing radiation. We have shown that
the enclosed-gate layout for NMOS transistors can reduce the
leakage currents due to ionizing radiation. The noise properties
of the transistor were not effected up to an absorbed dose of
29 kGy(SiO2 ).
ACKNOWLEDGMENT
We are grateful to the Canadian Microelectronics Corporation for access to test equipment and fabrication facilities. We
thank Shengli Liu for helping with the irradiations, and Doug
Gish for helping with the irradations and dosimetry.
R EFERENCES
[1] M. Campbell et al, “An introduction to deep submicron CMOS for vertex
applications”, Nucl. Instr. and Meth. A 473 (2001) 140-145.
[2] M. Manghisoni, L. Ratti, V. Re, V. Speziali, “Radiation Hardness Perspectives for the Design of Analog Detector Readout Circuits in the 0.18-µm
CMOS Generation”, IEEE Trans. Nucl. Sci., vol. 46, pp. 2902-2909, Dec.
2002.
[3] G. Anelli et al, “Radiation Tolerant VLSI Circuits in Standard Deep
Submicron CMOS Technologies for the LHC Experiments: Practical
Design Aspects”, IEEE Trans. Nucl. Sci., vol. 46, pp. 1690-1696, Dec.
1999.
[4] W.J. Snoeys et al, “Layout techniques to enhance the radiation tolerance
of standard CMOS technologies demonstrated on a pixel detector readout
chip”, Nucl. Instr. and Meth. A 439 (2000) 349-360.
[5] W.J. Snoeys, T.A. Gutierrez, G. Anelli, “A New NMOS Layout Structure
for Radiation Tolerance”, IEEE Trans. Nucl. Sci., vol. 49, pp. 1829-1833,
Aug. 2002.
[6] D.M. Gingrich, S. Böttcher, N.J. Buchanan, S. Liu, J.A. Parsons, W.
Sippach, “Radiation Tolerant ASIC for Controlling Switched-Capacitor
Arrays”, IEEE Trans. Nucl. Sci., vol. 51, pp. 1324-1332, Aug. 2004.
[7] G. Cervelli, A. Marchioro, P. Moreira, “A 0.13µm CMOS Serializer for
Data and Trigger Optical Links in Particle Physics Experiments”, IEEE
Trans. Nucl. Sci., vol. 51, pp. 836-841, June 2004.
[8] A. Giraldo, A. Paccagnella, A. Minzoni, “Aspect ratio calculation in nchannel MOSFETs with a gate-enclosed layout”, Solid-State Electronics
44 (2000) 981-989.
[9] M. Manghisoni, V. Re, V. Speziali, F. Svelto, “Experimental studies of
the noise properties of a deep submicron CMOS process”, Nucl. Instr.
and Meth. A 461 (2001) 537-539.
[10] G. Anelli, F. Faccio, S. Florian, P. Jarron, “Noise characterization of a
0.25 µm CMOS technology for the LHC experiments”, Nucl. Instr. and
Meth. A 457 (2001) 361-368.
[11] V. Re et al, “Experimental Study and Modeling of the White Noise
Sources in Submicron P- and N-MOSFETs”, IEEE Trans. Nucl. Sci.,
vol. 48, pp. 1577-1586, Aug. 2001.
[12] M. Manghisoni, L. Ratti, V. Speziali, “Submicron CMOS Technologies
for Low-Noise Analog Front-End Circuits”, IEEE Trans. Nucl. Sci., vol.
49, pp. 1783-1790, Aug. 2002.
0-7803-8701-5/04/$20.00 (C) 2004 IEEE