APPLICATION NOTE
Enhancement-Mode GaN Transistors
Using Enhancement Mode
GaN-on-Silicon Power Transistors
EFFICIENT POWER CONVERSION
Edgar Abdoulin, Steve Colino, Alana Nakata; Efficient Power Conversion Corporation
Using enhancement mode GaN-on-Silicon
devices is very similar to using modern
power MOSFETs. However, due to the significantly better performance, there are
some additional design and test considerations to make certain devices are used
efficiently and reliably.
In an effort to make the transition from power
MOSFETs to the new generation of power management devices as easy as possible, this paper
describes the general operation of enhancement
mode GaN devices, gate drive techniques, circuit
layout considerations, thermal management techniques, and testing considerations.
S
G
GaN
Si
Fig 1 – EPC’s GaN Power Transistor Structure
General Description of
Enhancement-Mode GaN
Devices and GaN-on-Silicon
Technology
Structure
100V
10
200V
1
Si Limit
10
0
Ron (Ωmm2)
Efficient Power Conversion Corporation’s
(EPC) hyper fast enhancement mode Gallium Nitride (GaN) power transistors offer
performance improvements well beyond
the realm of silicon-based power MOSFETs. Standard power converter topologies can greatly benefit from the added
performance and leap to performance not
attainable with current MOSFET designs;
improving converter efficiency, while
maintaining the simplicity of converter
designs.
10
-1
SiC Limit
EPC1010
GaN Limit
A device’s cost effectiveness
10-2
EPC1001
starts with leveraging existing production infrastructure.
10-3
EPC’s process begins with sili10-4
con wafers upon which a thin
101
102
103
104
layer of Aluminum Nitride
Breakdown Voltage (V)
(AlN) is grown to isolate the
Fig 2 – Resistance vs Breakdown Voltage
device structure from the substrate. On top of this, a layer
of highly resistive Gallium Nitride is grown. This
Operation
layer provides a foundation on which to build the
EPC’s GaN transistors behave very similarly to siliGaN transistor. An electron generating material is
con Power MOSFETs. A positive bias on the gate
applied to the GaN. This layer produces an abunrelative to the source causes a field effect which atdance of electrons near the top of the underlytracts electrons that complete a bidirectional chaning GaN. Further processing forms a depletion
nel between the drain and the source. Since the
region under the gate. To enhance the transistor, a
electrons are pooled, as opposed to being loosely
positive voltage is applied to the gate in the same
trapped in a lattice, the resistance of this channel is
manner as turning on an n-channel enhancement
quite low. When the bias is removed from the gate,
mode power MOSFET. A cross section of this
the electrons under it are dispersed into the GaN,
structure is depicted in figure 1. This structure
is repeated many times to form a power device.
recreating the depletion region, and once again,
The end result is a fundamentally simple, elegant,
giving it the capability to block voltage.
cost effective solution for power switching. This
To obtain a higher voltage device, the distance
device behaves similarly to silicon MOSFETs with
between the Drain and Gate is increased. As the
some exceptions that will be explained in the folresistivity of the GaN “electron pool” is very low,
lowing sections.
the impact on resistance by increasing blocking
voltage capability is much lower when compared
Electron Generating Layer
with silicon. Figure 2 shows the theoretical tradeoff between device on resistance and blocking
Dielectric
voltage for GaN, SiC, and Si. The capability of EPC’s
Aluminum Nitride
D
first generation of devices is shown as well. Please
Isolation Layer
note that after 30 years, silicon MOSFET development has approached its theoretical limits. Progress in silicon has slowed to the point where small
gains have significant development cost. GaN is
young in its life cycle, and will see significant improvement in the years to come.
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2010 |
| PAGE 1
APPLICATION NOTE
Enhancement-Mode GaN Transistors
Driving Enhancement-Mode
GaN Transistors
Driver
CGD
High dV/dt
on Drain
Do Not Exceed Gate Drive Maximum Ratings
The equivalent gate circuit of the EPC1001 GaN
Power MOSFET is depicted in Fig 3. The gate consists of a small resistor (RG ~ 0.5 Ω), and a Capacitor, CGS. Full enhancement of the device channel
is achieved with 5 V between the gate and source.
RG
GaN
5V
Gate
High Current
in Driver
QG
Source
Fig 3 – EPC GaN power transistor gate structure
It is important to maintain a gate drive level that
will not exceed the 6 V maximum rating. Excessive
inductance in the gate loop can drive the voltage beyond 5 V. EPC’s GaN Transistor’s simulated
in-circuit waveforms with 1 nH and 2 nH gate inductance are shown in Fig 4. As the inductance
increases, so does the ringing and peak voltage,
which could damage the gate structure.
Fig 5 – High dV/dt can cause high currents to flow in the gate driver.
To reduce gate drive loop inductance on
a PCB layout:
in excessive losses. Therefore, the selection of a
proper driver is not only driven by the current/
switching time requirement, but also by the need
to provide a low impedance path for stray current
generated by the high dV/dt.
• Ensure gate driver is placed close to the
device being driven, Keep lead lengths
shorter than 0.5 in (1.2 cm)
• Place gate drive and return lines on top of
one another (strip-line) to reduce the
loop inductance.
• Use small outline package surface mount
drivers intended for high speed operation,
with minimal lead inductance.
• The use of limiting Zener diodes on the gate is
NOT recommended. These diodes carry
considerable capacitance and will result
in slower switching of the GaN
transistors and promote gate
oscillations
As an example, EPC GaN transistors can switch a
48 V bus in under 4 nsec, resulting in dV/dt in excess of 12 V/nsec. With a 60 pF CGD, the resulting
current fed back into the driver is going to be:
I(Peak) = CdV/dt = 60E-12 *12/1E-9 = 0.72 A
A driver with a 0.5 W impedance will see a rise in
gate voltage of 0.72 A x 0.5 W = 0.36 V, which is still
well below the minimum threshold of EPC’s GaN
transistors (0.7 V).
Provide Low Gate Drive Impedance
to Prevent Undesired Turn-On
1 nH Gate Inductance | Green: Vds | Yellow: Gate drive
2 nH Gate Inductance shows excessive ringing
Green: Vds | Yellow: Gate drive
Fig 4 – Effect of drive loop inductance on
maximum drive voltage
Due to the hyper-fast switching characteristics of the EPC GaN power transistor, high dV/dt is present when the
device switches from one state to another. This high dV/dt can cause high
current to flow in the miller capacitor (CGD). In a half bridge topology a
small driver with a relatively high on
resistance could cause an undesired
turn-on of the lower device when the
actual requirement is to keep the device off. This phenomenon is shown
in figures 5 & 6 and will increase the
risk of shoot-thru current and result
Fig 6 – Half Bridge Topology with high gate drive RDS(ON) –
High dV/dt causes “Bump” in Lower gate drive.
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| PAGE 2
APPLICATION NOTE
Enhancement-Mode GaN Transistors
A driver with a 1 W output impedance will see a
0.72 V “Bump” on the gate which, when added
with spikes due to other board parasitics will
come quite close to the minimum turn-on threshold of the GaN transistor and could cause undesired turn-on, and possible shoot-through current
specifically in half or full-bridge topologies. Care
should be taken to ensure that the driver impedance is specified at the appropriate operating voltage. Drivers designed for, and specified for 12 V
operation have significantly higher impedance
when operated at 5 V.
Another possible solution for eliminating the
“Bump” Is shown in fig 7. This method employs
a smaller GaN device to pull down the gate and
provide a path for the current generated by high
dV/dt.
Characteristics of preferred gate drivers for
EPC GaN transistors:
• Low inductance surface mount package.
Driver
CGD
Input Pulse
GaN
5V
GaN
Fig 7 – Example of circuit providing a low impedance path for dV/dt generated current.
Part #
QG (Tot)
VGS= 5V
QGS (Typ)
QGD (Typ)
CGD (Typ)
CISS (Typ)
COSS (Typ)
QRR (Typ)
RG (Typ)
nC
nC
nC
pF
pF
pF
nC
W
1.00
0.55
15
280
150
4.6
0.50
EPC1014
3.00
• Output impedance 0.5 W or less.
EPC1015
11.60
3.80
2.20
60
1100
575
18.5
0.50
• Must operate down to 4.5 V supply voltage
EPC1009
2.40
0.75
0.63
11
196
120
5.8
0.50
• Peak output current >5 A at 5 V supply.
EPC1005
10.00
3.00
2.50
43
790
480
23
0.50
• Better than 5 ns rise and fall times with
1 nF load.
EPC1007
2.70
0.75
1.00
10
200
110
8
0.50
EPC1001
10.50
3.00
3.30
40
800
450
32
0.50
EPC1013
1.70
0.37
0.70
8
110
85
8
0.50
EPC1011
6.70
1.50
2.80
30
440
340
32
0.50
EPC1012
1.90
0.37
0.90
8
110
80
10
0.50
EPC1010
7.50
1.50
3.50
30
440
310
40
0.50
The following two tables list the DC and Capacitive characteristics of EPC GaN Transistors and are
provided as an aid to determine the drive requirements for each type.
Table 1 – Gate charge and Capacitive characteristics of EPC GaN Power Transistors
Part
Number
VDS ( Max)
VGS (Max )
VGSTH (Typ)
VGSTH (Min)
VGSTH (Max)
RDS(ON) (Typ) @
VGS=5VDC
RDS(ON) (Max) @
VGS=5VDC
VSD (Typ)
ID
Package
VDC
VDC
VDC
VDC
VDC
mW
mW
VDC
ADC
(mm)
EPC1014
40
+6/-5
1.4
0.7
2.5
12
16
1.80
10
LGA 1.7x1.1
EPC1015
40
+6/-5
1.4
0.7
2.5
3
4
1.80
33
LGA 4.1x1.6
EPC1009
60
+6/-5
1.4
0.7
2.5
24
30
1.80
6
LGA 1.7x1.1
EPC1005
60
+6/-5
1.4
0.7
2.5
6
7
1.80
25
LGA 4.1x1.6
EPC1007
100
+6/-5
1.4
0.7
2.5
24
30
1.80
6
LGA 1.7x1.1
EPC1001
100
+6/-5
1.4
0.7
2.5
6
7
1.80
25
LGA 4.1x1.6
EPC1013
150
+6/-5
1.4
0.7
2.5
70
100
1.80
3
LGA 1.7x0.9
EPC1011
150
+6/-5
1.4
0.7
2.5
18
25
1.80
12
LGA 3.6x1.6
EPC1012
200
+6/-5
1.4
0.7
2.5
70
100
1.80
3
LGA 1.7x0.9
EPC1010
200
+6/-5
1.4
0.7
2.5
18
25
1.80
12
LGA 3.6x1.6
Table 2 – DC Characteristics of EPC GaN Power Transistors
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| PAGE 3
APPLICATION NOTE
Enhancement-Mode GaN Transistors
Drain to source maximum voltage rating
The maximum drain to source breakdown voltage (BVDSS) is specified in EPC GaN transistor data
sheets. As a general practice, the maximum bus
voltage should be de-rated to 80% of the GaN
breakdown voltage rating.
Special considerations have to be taken when
switching inductive loads - These types of loads
present a possibility of the drain voltage exceeding
the maximum rating due to inductive “Kickback”.
This phenomenon will cause the drain voltage
to increase beyond the breakdown and dissipate
the energy from the inductor in the device. EPC’s
GaN transistors are not rated for avalanche mode
operation. If an avalanche mode operation is suspected, proper active or passive clamps/snubbers
must be used to limit the rise in the VDS to a safe
level. Also, proper layout techniques must be used
to limit the parasitic inductance in the circuit and
hence limit the stray inductive energy present in
the system.
Fig 9 - Low inductance Buck converter layout
Layout considerations
Due to the fast switching and high current-carrying capability of EPC’s GaN transistors, special considerations have to be taken into account when
designing printed circuit boards utilizing these devices. Keeping gate drive and return trace lengths
to a minimum and using a single point ground to
avoid mixing high currents with gate drive and
control currents are some of the techniques that
have been proven to minimize oscillations and
reduce parasitic losses in high frequency circuits.
Using ground and VCC planes can also lower losses.
Reducing drain trace inductance and adequately
bypassing bus bars with capacitors placed as close
as possible to the devices are additional techniques for reducing unwanted loss.
In higher frequency circuits (>1 MHz), it might be
necessary to use “strip line” techniques to match
the impedance of the gate driver and drain/source
traces to the device and to reduce oscillations and
hence EMI. A low-inductance, distributed-capacitance layout for a half buck converter is shown in
figs 8 & 9 and the resulting waveforms are shown
in fig 10. The result of these simple layout techniques is negligible overvoltage.
Consider Using the Body Diode Instead of a
Parallel Schottky
Fig 8 – DC-DC 48 V-1 V Converter board with distributed capacitance and low inductance (250 kHz)
EPC’s GaN transistor’s integral diode is similar
to the reverse diode in a silicon power MOSFET.
However, only minority carriers are used in GaN
device conduction so there is zero reverse recovery. The forward voltage of the internal diode is
equal to VGS(TH).
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Fig 10 – Oscillographs of a Buck converter with a
low inductance board
There are at least two ways to reduce the losses
in the body diode. The most advantageous is to
use a near zero dead time. If this is not practical, a
Schottky diode can be used eliminate the high forward voltage during high side turn off, and drastically reduce it after low side turn off. Fig 11 shows
| PAGE 4
APPLICATION NOTE
EPC1001 GaN VSD
90
2.8
85
2.7
80
2.6
75
Efficiency (%)
VSD (VDC)
2.9
Enhancement-Mode GaN Transistors
2.5
2.4
2.3
70
65
60
2.2
With Schottky
55
2.1
2
Comparison of Converter Efficiency
50
0
5
10
15
I (ADC)
20
25
30
Fig 12 – GaN Reverse Diode Voltage Drop (VSD) for a typical EPC1001 device.
Without Schottky
0
2
4
8
10
12
14
Other losses could result from inappropriate gate
drives, where excessive loop inductance and dV/
dt “bumps” on the gate cause shoot thru currents.
In half/full bridge topologies this noise will result
in undesired loss of efficiency (See pages 2 – 4 of
this paper for recommended drive techniques)
• Switching losses: By using adequate gate
drive, these losses can be minimized. EPC’s
GaN transistors are hyper fast devices that
can switch a 48 V bus within 4~5 nsec.
Switching losses in a properly driven EPC
GaN can be negligible.
the reverse characteristics of EPC GaN transistor
at 25 A with a circuit-set dead time of about 30
nsec. The graph in Fig 12 shows the the forward
voltage drop of the internal diode for a typical
EPC1001 device.. A comparison of efficiencies of
a DC-DC converter with and without a (1 A, 100
V) Schottky diode are shown in fig 13. The loss
of efficiency for small this small diode is negligible. We can therefore conclude that the use of
a Schottky diode is optional and will depend on
efficiency requirements and cost.
IOUT (ADC)
Fig13 - Comparing Efficiency of 48 V to 1 V Buck converter with
and without a Schottky diode in parallel.
EPC GaN main losses consist of two
basic components:
Fig 11 – GaN Reverse Diode voltage drop @25 A
6
One further advantage of EPC’s GaN transistors is
the isolation offered by the silicon substrate. The
substrate electrically isolates the device from the
back side enabling the user to mount a heat sink
DIRECTLY on the die. This feature greatly reduces
the thermal resistance of the system allowing removal of heat generated by power losses using a
smaller and less costly heatsink and double sided
cooling. (Fig 14)
• RDS(ON) /Static losses: These losses are the
main contributors to junction temperatures.
By using thermal resistance values, a maximum
RMS current can be calculated to maintain the
device within its thermal limits.
Heat Sink
Thermal Management
Due to the low RDS(ON) of EPC GaN transistors, the
possibility of currents exceeding the maximum
rating of the device is high. High currents, over
and beyond the maximum ratings can cause gradual degradation of the device under heavy use and
should be avoided. High currents will also cause
excessive dissipation which will also contribute to
reducing the reliability of the GaN transistor.
EPC GaN transistors are specified for operation at
a maximum of 125 °C. Losses in the device can increase the junction temperature beyond the maximum rating.
PCB
Thermal Pad
EPC GaN
Die
Fig 14 – Dual Die under one heat sink with thermal pad
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| PAGE 5
APPLICATION NOTE
Enhancement-Mode GaN Transistors
Large switchnode pads on the PCB added to help
dissipate the heat should be avoided for the following reasons:
1) They will cause unwanted oscillations
and EMI.
2) Thermal resistance of junction to air through
the PCB is ~40 °C/W and will not be effective.
10 kΩ
1 nH
0.8 Ω
Drain
2 nH
13 uF
100 VDC
Max
+
–
5 VDC
Source
0.1 Ω
Gate
VDRIVER
50 Ω
In all circuits the heatsink thermal resistance can
be calculated from the following formula:
(100˚C – TA)
(RDS(ON) x (IPEAK * D))2
– RθJB – RθBA
Where IPEAK is the peak current, D is the duty cycle
and a 100 °C maximum working temperature is
chosen for the die.
To confirm the thermal characteristics, an EPC1001
die was operated in a DC-DC converter at 250 kHz,
converting 24 V input to 1 V output , while conducting 12 A. The measurement of the backside
temperature indicated a rise of 25.8 °C, without a
heat sink or forced air flow. Total losses were calculated to be 684 mW. The copper pad surrounding
the die had an area of 0.25 square inches. The resulting thermal resistance from junction to air for
this setup was calculated to be 38 °C/W.
Using Device Models to
Simulate Circuit Behavior
Years of work have gone into the development
of silicon power MOSFET device models. Early attempts were based on a fitting of device behavior
with functions of the approximate shape, polynomials of many orders, or simple look up tables.
Recent trends have been toward solving multidimensional electrostatic conditions from the
basic underlying physics – a daunting task – but
great simplification in the final solution has been
achieved using this approach. The V091 models
developed for EPC’s enhancement mode GaN
transistors are a hybrid of physics-based and phenomenological functions. Although quantumbased effects have not been incorporated, the
models developed by EPC accurately reproduce
the basic response of the devices under circuit operation conditions.
As a demonstration of device model and circuit
considerations, a simple circuit was built and
tested to compare device performance with that
predicted by the model.(Fig 15)
Figure 15: Schematic of demo circuit number 1
Curve Tracer and Auto-Testing Considerations
The circuit consisted of a voltage source charging
a 13 µF cap through a 10 kW resistor used to isolate
the voltage source from the device under test. The
GaN transistor is driven with a 5 V pulse and the capacitor is discharged through a 0.8 W resistor and
the device with a 0.1 W stray resistance.
EPC enhancement mode GaN transistors generally
behave like n-channel power MOSFETs. Common
curve tracers, parametric analyzers, and automatic
discrete device parametric testers that are used for
an n-channel power MOSFET will be applicable
for the characterization of GaN transistors. Below
are some general guidelines for characterizing
DC parameters using a Tektronix 576 curve tracer,
Keithley 238 parametric analyzer, or a TESEC 881TT/A discrete device test system.
Comparison of the simulated results for the demo
circuit show reasonable correlation with the measured values. Although not perfect, overshoot
and ringing is qualitatively reproduced. Figure 16
shows the overlay of the gate and drain voltages
vs time for the measured and simulated circuit.
Caution: GaN transistors are sensitive to static.
GaN transistors have very low capacitances
A number of improvements are under development to incorporate field dependent mobility and
gate injection current. SPICE models for all EPC
parts are available for download on the EPC web
site (www.epc-co.com).
and a low maximum allowed gate voltage.
Wrist straps, grounding mats, and other ESD
precautions must be followed to avoid exceeding maximum device ratings.
20
VGATE
VDRAIN
15
SIM VDRAIN
SIM VGATE
Voltage
RθSA=
10
5
0
-5
0.0E+00
5.0E-08
1.0E-07
1.5E-07
2.0E-07
2.5E-07
3.0E-07
3.5E-07
4.0E-07
Time (s)
Figure 16: Comparison of simulated and measured demo circuit 1
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| PAGE 6
APPLICATION NOTE
Enhancement-Mode GaN Transistors
5.0E-03
gate with respect to the source and accidentally
turning on the device. The device could be damaged during the IDSS testing if this occurs.
With Rg
Without Rg
4.5E-03
Current (Drain to Source)(A)
4.0E-03
As with IGSS and RDS(ON) measurements, it is not recommended to use the Autorange function during IDSS testing on an automated tester such as a
TESEC 881-TT/A, as range-changes during testing
can lead to voltage spiking which may destroy the
gate. The use of “Function BVDSS” should also be
avoided because the measurement of the drainsource voltage at a fixed drain current may exceed
device VDS maximum rating.
3.5E-03
3.0E-03
2.5E-03
2.0E-03
1.5E-03
1.0E-03
5.0E-04
0.0E+00
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Bias (Drain/Gate to Source)(V)
Figure 17: Comparison of VTH curves with and without a gate resistor for EPC1001 transistors
VTH Measurement
VTH is the gate-source voltage (VDS = VGS) which
produces a specified drain current on the data
sheet. This test is typically done with the drain and
gate shorted.
Caution for VTH curve tracer testing: If there
is no gate resistor (RG) in series with the gate
during the VTH measurement, you may see an
oscillation on the gate which will result in a
typical S curve like that shown in figure 17.
The oscillation voltage can become many time
the input voltage. THESE OSCILLATIONS CAN
DAMAGE OR DESTROY THE DEVICE.
IGSS Measurement
IGSS is the gate-source leakage current with the
drain shorted to the source.
RDS(ON) Measurement
RDS(ON) is the drain to source resistance with
VGS = 5 V. Since RDS(ON) is sensitive to temperature,
it is important to minimize heating of the junction
during the test. A drain pulse test is therefore used
to measure RDS(ON). Accurate RDS(ON) measurement
requires the use of Kelvin Sense on both drain and
source. The locations of sense points have a strong
influence on RDS(ON) reading. It is not recommended
to use the Autorange function during RDS(ON) testing on an automated tester such as a TESEC 881TT/A, as range-changes during testing can lead to
voltage spiking which may destroy the gate.
It is not recommended to use needles on a bare
die to measure RDS(ON). Too high current density at the probe needle /solder bump contacts
could damage the device.
IDSS / BVDSS Measurement
Do not exceed 6 V on the gate in the positive direction or 5 V in the negative direction as that is the
maximum gate rating for the device.
BVDSS is the rated voltage of the device at VGS = 0 V.
IDSS is the drain current at a specified drain-source
voltage which is equal or less than the rated voltage of the device, with VGS = 0 V.
It is very important to have a very low resistance
short between the drain and the source in order
to get an accurate Igss measurement. It is not recommended to use the Autorange function during IGSS testing on an automated tester such as a
TESEC 881-TT/A, as range-changes during testing
can lead to voltage spiking which may destroy
the gate.
The true breakdown voltage for a GaN device from
EPC is generally well above the maximum drainsource Voltage rating of the device. Therefore a
BVDSS test should not be done on the device because the maximum VDSS rating will be exceeded.
Degradation of device RDS(ON) may be seen if the
max rating is exceeded. It is also very important to
short the gate and the source to avoid floating the
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Users should first verify that there is no spiking
above voltage test settings during the IDSS measurements. It is recommended to use a controlled voltage ramp to aid in avoiding voltage
overshoot.
It is very important to short the gate and the
source to avoid floating the gate with respect to
the source and accidentally turning on the device.
The device could be damaged during the IDSS testing if this occurs. It is not sufficient to set the gate
to 0 V; you must have a very low resistance short
from the gate to the source
A Final Note
How easy a device is to use depends on the skill
of the user, the degree of difficulty of the circuit
under development, how different the device is
compared with devices within the experience of
the user, and the tools available to help the user
apply the device
The new generation of enhancement mode GaN
transistor is very similar in its behavior to existing
power MOSFETs and therefore users can greatly
leverage their past design experience. Two key
areas stand out as requiring special attention are:
relatively low gate dielectric strength, and relatively high frequency response. The first of these two
differences, relatively low gate dielectric strength,
will be improved as the technology matures. The
second difference, relatively high frequency response, is both a step function improvement over
any prior silicon devices, and an added consideration for the user when laying out circuits.
On the other hand, there are several characteristics that render these devices easier to use than
their silicon predecessors. For example, the
threshold voltage is virtually independent of temperature over a wide range, and the on-resistance
has a significantly lower temperature coefficient
than silicon.
| PAGE 7
APPLICATION NOTE
Enhancement-Mode GaN Transistors
Typical 100 V Power MOSFET
EPC1001 Enhancement-Mode GaN
Max Gate Source Voltage
± 20 V
+6 V / -5 V
Operating Temperature
150˚C
125˚C
Avalanche Energy
OK
Not Rated
Gate Threshold
2-4 V
0.7-2.5 V
Gate-Source Leakage
few nA
few mA
Gate Resistance
few W
approx 0.6 W
Switching Charge
high
very low
Reverse Diode Recovery Charge
high
zero
Ratio RDS(ON) 125˚C / 25˚C
2.2
1.5
Ratio VTH 125˚C / 25˚C
0.66
1
The table above is a summary comparison between a silicon power MOSFET and an EPC1001
GaN transistor’s basic characteristics.
User-friendly tools can also make a big difference
in how easy it is to apply a new type of device.
EPC has developed a complete set of SPICE device models available for user download. Whereas
more work refining these models needs to be
done, the first-generation should provide reasonably reliable circuit performance predictions that
can enhance the engineer’s productivity and the
time it takes to get a product to market.
Application notes and design tips codify the collective experience of engineers over the years.
Thousands of applications notes are available
describing power MOSFET use in hundreds of applications. It will take many years for GaN users
to match this body of knowledge but, because of
the similarities between enhancement mode GaN
transistors and silicon power MOSFETs, much of
this work continues to apply.
Today, we are at a threshold with enhancement
mode GaN on silicon and we are beginning an
exciting journey with new products and breakthrough capabilities almost monthly.
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2010 |
The power MOSFET is not dead, but is nearing the
end of the road of major improvements in performance and cost. GaN will most likely become the
dominant technology over the next decade due
to its large advantages in both performance and
cost; advantage gaps that promise to widen as we
plummet down the learning curve.
GaN Applications Notes from EPC
1. Fundamentals of Gallium Nitride
Power Transistors
2. Single-Stage 48 V - 1 V DC-DC Conversion
Simplifies Power Distribution While
Significantly Boosting Conversion Efficiency
3. High Frequency 24 V-to-1 V DC-DC Converters
Using EPC’s Gallium Nitride (GaN)
Power Transistors
4. High Frequency 12 V - 1 V DC-DC Converters
Advantages of using EPC’s Gallium Nitride
(GaN) Power Transistors vs Silicon-Based
Power MOSFETS
5. EPC GaN Transistor Parametric
Characterization Guide
| PAGE 8