VP0550
P-Channel Enhancement-Mode
Vertical DMOS FETs
Features
General Description
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The Supertex VP0550 is an enhancement-mode (normallyoff) transistor that utilizes a vertical DMOS structure
and Supertex’s well-proven silicon-gate manufacturing
process. This combination produces a device with the
power handling capabilities of bipolar transistors, and the
high input impedance and positive temperature coefficient
inherent in MOS devices. Characteristic of all MOS
structures, this device is free from thermal runaway and
thermally-induced secondary breakdown.
Free from secondary breakdown
Low power drive requirement
Ease of paralleling
Low CISS and fast switching speeds
High input impedance and high gain
Excellent thermal stability
Integral source-to-drain diode
Applications
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Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Motor controls
Converters
Amplifiers
Switches
Power supply circuits
Drivers (relays, hammers, solenoids, lamps,
memories, displays, bipolar transistors, etc.)
Ordering Information
Device
VP0550
Package Option
TO-92
BVDSS/BVDGS
RDS(ON)
ID(ON)
(V)
(max)
(Ω)
-500
125
-100
VP0550N3-G
(min)
(mA)
-G indicates package is RoHS compliant (‘Green’)
Pin Configuration
DRAIN
Absolute Maximum Ratings
SOURCE
Parameter
Value
Drain-to-source voltage
BVDSS
Drain-to-gate voltage
BVDGS
Gate-to-source voltage
±20V
Operating and storage temperature
Soldering temperature*
-55°C to +150°C
+300°C
Absolute Maximum Ratings are those values beyond which damage to
the device may occur. Functional operation under these conditions is not
implied. Continuous operation of the device at the absolute rating level
may affect device reliability. All voltages are referenced to device ground.
*
GATE
TO-92 (N3)
Product Marking
SiVP
0 5 5 0
YYWW
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
Package may or may not include the following marks: Si or
TO-92 (N3)
Distance of 1.6mm from case for 10 seconds.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
VP0550
Thermal Characteristics
ID
ID
Power Dissipation
θjc
IDR†
θja
IDRM
Package
(continuous)†
(mA)
(pulsed)
(mA)
@TC = 25OC
(W)
( C/W)
( C/W)
(mA)
(mA)
TO-92
-54
-250
1.0
125
170
-54
-250
O
O
Notes:
† ID (continuous) is limited by max rated Tj .
Electrical Characteristics (T = 25°C unless otherwise specified)
A
Sym
Parameter
Min
Typ
Max
Units
BVDSS
Drain-to-source breakdown voltage
-500
-
-
V
VGS = 0V, ID = -1.0mA
VGS(th)
Gate threshold voltage
-2.0
-
-4.5
V
VGS = VDS, ID = -1.0mA
Change in VGS(th) with temperature
-
3.5
6.0
mV/ C
VGS = VDS, ID = -1.0mA
Gate body leakage current
-
-
-100
nA
VGS = ±20V, VDS = 0V
-
-
-10
-
-
-1000
-
-90
-
-100
-240
-
Static drain-to-source on-state resistance
-
85
-
-
80
125
Change in RDS(ON) with temperature
-
0.85
-
%/ C
VGS = -10V, ID = -10mA
25
40
-
mmho
VDS = -25V, ID = -10mA
ΔVGS(th)
IGSS
IDSS
Zero gate voltage drain current
ID(ON)
On-state drain current
RDS(ON)
ΔRDS(ON)
GFS
Forward transconductance
CISS
Input capacitance
-
40
70
COSS
Common source output capacitance
-
10
20
CRSS
Reverse transfer capacitance
-
3.0
10
td(ON)
Turn-on delay time
-
5.0
10
Rise time
-
8.0
10
Turn-off delay time
-
8.0
15
Fall time
-
5.0
16
Diode forward voltage drop
-
-0.8
Reverse recovery time
-
200
tr
td(OFF)
tf
VSD
trr
O
µA
mA
Ω
O
Conditions
VGS = 0V, VDS = Max Rating
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
VGS = -5.0V, VDS = -25V
VGS = -10V, VDS = -25V
VGS = -5.0V, ID = -5mA
VGS = -10V, ID = -10mA
pF
VGS = 0V,
VDS = -25V,
f = 1.0MHz
ns
VDD = -25V,
ID = -100mA,
RGEN = 25Ω
-1.5
V
VGS = 0V, ISD = -0.1A
-
ns
VGS = 0V, ISD = -0.1A
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
0V
PULSE
GENERATOR
10%
INPUT
-10V
td(ON)
RGEN
90%
t(OFF)
t(ON)
td(OFF)
tr
D.U.T.
tF
0V
INPUT
90%
OUTPUT
VDD
Output
10%
90%
RL
10%
VDD
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VP0550
Typical Performance Curves
Output Characteristics
Saturation Characteristics
-0.5
-100
-0.4
-80
ID (milliamps)
ID (amperes)
VGS = -10V
-0.3
-8V
-7V
-0.2
-6V
-0.1
0
VGS = -10V
-8V
-5V
-60
-4V
-40
-20
-5V
0
0
-10
-20
-30
-40
-50
0
-2
-4
VDS (volts)
-6
-8
-10
VDS (volts)
Power Dissipation vs. Case Temperature
Transconductance vs. Drain Current
100
2.0
VVDS
DS = -25V
TA= -55°C
80
TA = 25°C
60
PD (watts)
GFFSS (millisiemens)
-6V
TA = 150°C
40
1.0
20
0
0
0
-0.05
-0.10
-0.15
-0.20
0
-0.25
25
50
I D (amperes)
100
125
150
Thermal Response Characteristics
Maximum Rated Safe Operating Area
-1.0
1.0
Thermal Resistance (normalized)
ID (amperes)
75
TC (°C)
-0.1
TO-92(DC)
-0.01
T C = 25°C
-0.001
-1
-10
-100
VDS (volts)
-1000
0.8
0.6
0.4
0.2
0
0.001
P D = 1W
T C = 25°C
0.01
0.1
1.0
t p (seconds)
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10
VP0550
Typical Performance Curves (cont.)
On-Resistance vs. Drain Current
200
1.10
160
RDS(ON) (ohms)
1.05
1.00
VGS = -5V
VGS = -10V
120
80
40
0.95
0
0.90
-50
0
50
100
150
0
-0.05
Transfer Characteristics
-0.4
-0.15
-0.20
-0.25
V(th) and RDS Variation with Temperature
1.10
VDS = -25V
2.0
RDS(ON) @ -10V, -10mA
VGS(th) (normalized)
TA = -55°C
ID (amperes)
-0.10
ID (amperes)
Tj (°C)
TA = 25°C
-0.2
TA = 150°C
1.05
1.6
1.00
1.2
0.95
0.8
0.90
0.4
V(th) @ -1mA
0
0.85
0
0
-2
-4
-6
-50
-10
-8
0
50
VGS (volts)
150
Tj (°C)
Capacitance vs. Drain-to-Source Voltage
Gate Drive Dynamic Characteristics
80
-10
VDS = -10V
f = 1MHz
-8
VGS (volts)
60
C (picofarads)
100
CISS
40
20
COSS
VDS = -40V
-6
83pF
-4
30pF
-2
CRSS
0
0
0
-10
-20
-30
VDS (volts)
-40
0
0.2
0.4
0.6
0.8
QG (nanocoulombs)
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4
1.0
RDS(ON) (normalized)
BVDSS (normalized)
BVDSS Variation with Temperature
1.15
VP0550
3-Lead TO-92 Package Outline (N3)
D
A
1
Seating Plane
2
3
L
b
e1
e
c
Side View
Front View
E1
E
3
1
2
Bottom View
Symbol
Dimensions
(inches)
A
b
c
D
E
E1
e
e1
L
MIN
.170
.014†
.014†
.175
.125
.080
.095
.045
.500
NOM
-
-
-
-
-
-
-
-
-
MAX
.210
.022†
.022†
.205
.165
.105
.105
.055
.610*
JEDEC Registration TO-92.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc.#: DSPD-3TO92N3, Version E041009.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an
adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the
replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com.
©2009
All rights reserved. Unauthorized use or reproduction is prohibited.
Doc.# DSFP-VP0550
A052109
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
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