ML4004-PAM MDS
ML4004-PAM
PAM4 Time Domain Analyzer
2x56 Gb/s PAM4 BERT with
integrated 50GHz DSO
Dual PAM4 PPG and ED
Jitter Analysis
Eye Measurements
Eye Mask Test
Advanced Pattern Acquisition
MultiLaneSAL, ML4004-PAM Marketing Datasheet
Advanced product information subject to change. MultiLane SAL reserves the right to make changes to its product specifications at any time
without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.
ML4004-PAM MDS

ML4004-PAM
Histogram and SNR measurements (PAM4 Mode)
2x28 GB/s NRZ or 2x56 GB/s PAM4 BERT with 50
GHz Scope
 Mask Margin, Alternate Mask Margin
rules available (NRZ mode).
 Eye contour and Bathtub curve in NRZ mode,
Histogram in PAM4 mode
DSO features
PAM4 Mode
PAM4 scope measurements are currently
following the OIF contribution: 2014.051.00
Summary

PAM4 Measurements
The ML4004-PAM is a state of the art dual Channel
PAM4 BERT and Digital Sampling Oscilloscope,
integrated in an ultra-compact form factor.
USB/Ethernet controlled, it performs accurate eyediagram analysis to characterize the quality of
transmitters and receivers.
The ML4004-PAM DSO implements a statistical under
sampling technique using comprehensive software
libraries. It performs various eye and pattern
measurements (if the rate is above 6Gbps), mask
margin tests and jitter analysis on PAM4 and NRZ
signals.
Key Features
PAM4 Measurements
Symbol Levels
Vertical Eye Amplitudes
Vertical Eye Openings
Horizontal Eye Openings
Vertical Eye Closure (dB)
Openings by BER
Max, Min, Peak-to-Peak…
PAM4 scope measurements are currently following
the OIF contribution: 2014.051.00
BERT features
 NRZ Bit Rates: 10-15 and 18.6-30.2 Gb/s
 PAM4 Bit Rates: 37.2-60 Gb/s
 Inner eye amplitude variation (PAM4 mode)

Statistics histograms and Histogram measurements.
MultiLaneSAL, ML4004-PAM Marketing Datasheet
Advanced product information subject to change. MultiLane SAL reserves the right to make changes to its product specifications at any time
without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.
ML4004-PAM MDS
NRZ Mode
Ordering Information
 Total Jitter & Jitter decomposition:
o DJ, RJ
 Mask Margin, alternate Mask Margin
rules available.
 The mask margin (positive or negative)
can be extracted for a defined number of
points that fail, thus allowing for DUT
quality assessment, control and binning.
 Number of failing points for a region
can be returned as well as the actual
points that failed.
 Eye opening, eye height and width, eye
amplitude, top, base, max, min, peak to
peak.
 Rise/
fall
time,
single
edge
measurement in pattern capture.
 Statistics histograms and histogram
measurements.
 Crossing percentage.
 Pre-emphasis positive & negative
(amplitude width).
 Zooming, markers, X and Y histograms,
overlays, and multiple measurements,
statistics.
 Advanced Pattern Measurements
o Eye measurements on specific properties
of the pattern.
Eye Capture
ML4004-PAM: 2x 56 Gb/s PAM4 BERT
with 1x 32 or 50 GHz BW Scope
Target Applications
 Interconnect testing, SFP, SFP28, CFP, CFP2,
CFP4, QSFP, QSFP28, …
 Backplane testing
 Interference and Xtalk testing
 Receiver sensitivity testing
Mask Capture
Pattern Measurements
MultiLaneSAL, ML4004-PAM Marketing Datasheet
Advanced product information subject to change. MultiLane SAL reserves the right to make changes to its product specifications at any time
without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.
ML4004-PAM MDS
Time Domain Analyzer GUI
The user interface for the ML4004-PAM is an all-new combination of the ML-Bert and ML-DSO
programs for either PAM4 or NRZ modes. Both the DSO and Bert functions are accessible by the
same IP address, and can either be arranged to be tabs, or side by side in the same window
MultiLaneSAL, ML4004-PAM Marketing Datasheet
Advanced product information subject to change. MultiLane SAL reserves the right to make changes to its product specifications at any time
without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.
ML4004-PAM MDS
Electrical Specifications
Bit Rates
TX Amplitude Differential
Patterns
TX Amplitude Adjustment
NRZ Mode
PPG1/2
NRZ Mode
ED1/2
Pre-Emphasis
Pre-Emphasis Resolution
Equalizing Filter Spacing
Random Jitter RMS
Rise/ Fall Time (20–80%)
Output Return Loss up to 10GHz
Output Return Loss (16-25GHz)
Error Detector Phase Margin
Error Detector Maximum Input
Input CTLE Dynamic Range
TX/RX and clock connectors
Reference clock Output
Bit Rates
TX Amplitude Differential
Patterns
TX Amplitude Adjustment
PAM4
Mode
PPG1/2
PAM4
Mode
ED1/2
DSO
Pre-Emphasis
Pre-Emphasis Resolution
Equalizing Filter Spacing
Random Jitter RMS
Rise/ Fall Time (20–80%)
Output Return Loss up to 10GHz
Output Return Loss (16-25GHz)
Error Detector Phase Margin
Error Detector Input Range
Input CTLE Dynamic Range
TX/RX and clock connectors
Reference clock Output
Input Bandwidth
Input Amplitude (Single ended)
Input Rise / Fall Time
Diff. Input Return Loss
Vertical Resolution
10-15 and 18.6-30.2Gbps
250-1000mV
PRBS7/9/15/23/31 or User Pattern 40 bits
Programmable adjustment (± 20%) of
internal voltage regulators for margin testing
6 dB
10 steps
1UI
220 fS
12 pS
-15 dB
-10 dB
5 pS
1200 mV Diff
10 dB
2.92 mm K Connectors
Rate / 64
37.2 - 60 Gbps
250 - 1000 mV
PRBS7/9/11/15/23/31/Square_16/Square_32
Programmable adjustment (± 20%) of
internal voltage regulators for margin testing
6 dB
10 steps
1UI
200 fS
12 / 12 pS
-15 dB
-10 dB
5 pS
250 mV- 500 mV Diff
10 dB
2.92 mm K Connectors
Rate / 64
32 GHz or 50 GHz
AC: 600 mVpp S-E
12 / 12 ps
Better than 10 dB
12 bits
MultiLaneSAL, ML4004-PAM Marketing Datasheet
Advanced product information subject to change. MultiLane SAL reserves the right to make changes to its product specifications at any time
without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.
ML4004-PAM MDS
Electrical Specifications
Clock Input Range (Normal Mode)
50 - 710 MHz
Clock Input Range (Bypass Mode)
Clock Input Amplitude
Input Impedance
Intrinsic Jitter (excluding DDJ)
Amplitude Error
Data Format Support
PRBS Pattern Capture
Spurious-Free Dynamic Range
Power Adapter Specifications
Temperature range
Power Requirements
Memory Depth
50 - 125 MHz
200 - 1000 mV
50 Ω
200 fS
5 mV
NRZ/PAM4
up to PN11
8 bits
12V/1.2A 2.1 x 5.5 mm Centre Positive
0-65C
1A @ 12V
256K sample
Worldwide
North America & Europe
Asia
MultiLane SAL
Houmal Technology Park
141 Main Road
Houmal, Lebanon
+961 5 941668
MultiLane Inc
2000 Wyatt Drive, Suite 6
Santa Clara CA 95054
USA
+1 408 890 2234
MultiLane Asia Inc
No. 18, Prosperity Rd. 2
Hsinchu Science Park,
Taiwan
+886-3-6686667
Website: www.multilaneinc.com
Email: sales@multilaneinc.com
About MultiLaneSAL
MultiLaneSAL is leading developer of high speed instruments and interconnects test modules for10, 40, and 100Gbps of SerDes and high
speed IO for the semiconductor and cloud computing infrastructure. Products includes BERTs, Scopes, and a host of MSA Compliant
development tools for CFP, CFP2,CFP4,QSFP,zQSFP,QSFP28 and5x7 LH modules. MultiLane’s products are used to test semiconductors,
AOC, electro-optical modules and blades.
MultiLane operates out of Houmal Technology Park in Lebanon, and has been offering leading edge technology and products toTier1 equipment suppliers globally. Visit www.multilaneinc.com
Brochure History
Revision 1.0: July 17th2015
Revision 1.1: December 10th, 2015
Revision 1.2: January 4th, 2016
Revision 1.3: February 5th, 2016
MultiLaneSAL, ML4004-PAM Marketing Datasheet
Advanced product information subject to change. MultiLane SAL reserves the right to make changes to its product specifications at any time
without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.