A Low-Power Fully-Differential CMOS Operational
Transconductance Amplifier for A/D Converters
Andrea Gerosa and David A. Sobel
ABSTRACT
The design of a fully differential CMOS
transconductance amplifier is presented in this paper.
This amplifier is to be used in the first stage of a 13-bit
pipelined A/D converter, and was designed to meet the
necessary specifications at a minimum level of power
consumption. The amplifier presented below was based
on a two-stage design of a telescopic cascode input stage
followed by a common-source output gain stage. The
amplifier was compensated with a variation of Miller
compensation in order to achieve maximum bandwidth.
The amplifier designed meets all performance
specifications and consumes less than 2 mW of power.
1
INTRODUCTION
Pipelined analog-to-digital converters (A/D’s)
convert an analog input to a high-resolution digital
output (i.e. high number of output bits) through a
pipelined cascade of lower-resolution A/D converters,
each with a resolution of typically 1 to 1.5 bits. Each
pipeline stage calculates the digital output for its input,
and then passes on its analog error residue to the next
stage for a similar conversion. In order to ease the
conversion process for later stages, an inter-stage gain
of two is applied to the error residue to keep this signal
at a reasonable magnitude.
Hence, aside from the actual comparator, pipelined
A/D’s also require a circuit that can provide an adding
function and accurate gain. Both of these functions can
be provided by an operational transconductance
amplifier (OTA) connected in a switched-capacitor
(SC) gain configuration. It is worth noting two facts
about the performance requirements for an OTA within
a pipelined A/D converter. First, the circuit
specifications are determined by the overall
performance metrics of the entire A/D converter.
Therefore, pipelined A/D converters with high bit
resolutions require more precise analog circuits than
those converters with low-bit resolutions. Also, these
circuit requirements are relaxed as the signal
propagates down the pipeline. Hence, the performance
specifications are most rigorous for the OTA in the first
pipeline stage of the converter and scaling techniques
can be used in subsequent stages of the A/D in order to
minimize power dissipation [Cho95].
In this project, we designed a fully-differential OTA
to be used as the first stage of a 13-bit pipelined A/D
converter. The specifications to be met can be seen in
Table 1, and the circuit has to be robust over process
variations.
Supply
Dynamic Range
Open-loop gain
Settling Time
Accuracy
Power
3V
> 80 dB
> 10,000
< 100ns
> 0.01%
Minimum
Table 1: OTA specifications
The rest of this paper proceeds as follows: Section 2
includes a discussion of circuit topology considerations
for low power. Section 3 outlines the approach we took
to meeting the required specifications at a minimum
power level. Section 4 presents our two-stage OTA
design and the simulation results. Section 5 concludes
this paper with a discussion of the practicality of our
design and its effectiveness at achieving a low-power
solution.
2
TOPOLOGY CONSIDERATIONS FOR
LOW POWER
An a priori design decision was the choice of a class
A amplifier. While this choice does increase power
dissipation, the tradeoff of much simpler circuit design
was viewed as a net gain. With this decision in mind,
the circuit specifications present the following
considerations in choosing an OTA topology.
2.1
Transistor network topology
With the process parameters given, an open-loop
gain of 10,000 is on the order of (gmro)3. Therefore, at
least 3 gain devices must be placed within the signal
path in order to achieve the necessary gain. The
following topologies are candidates for such a
specification:
• A single-stage “regulated” cascode OTA
• A cascaded three-stage common-source OTA
• A two-stage folded cascode/common-source
OTA
•
A two-stage
source OTA
telescopic
severely degrading output swing or introducing a
complicated
dynamic
level-shifting
scheme
[Feldman97]. An OTA with a telescopic first stage
would most likely have a PMOS first stage and an
NMOS second stage in order to create a more stable
topology. Therefore, for a given settling constraint and
a fixed compensation technique, an OTA with a PMOS
first stage would consume roughly (µn/µp) more power
than an OTA with an NMOS first stage. For the
process parameters given, this ratio roughly equals 2.5.
Therefore, it can be seen from a power perspective,
the two topologies are roughly equivalent; the power
increase for the folded first-stage demanded by
criterion (1) and (2) are roughly balanced by the power
increase demanded by criterion (3) for the telescopic
first-stage. As there is no clear power advantage to
choosing one topology over another, we decided on the
OTA with the telescopic cascode as it seemed easier to
implement.
It is worth noting that two main advantages of the
folded first-stage unrelated to power consumption are
not relevant in this circuit. Namely, the folded-first
stage allows for a greater input common-mode range
and a greater output swing. As the required input
common-mode range of the circuit is not specified, and
common-mode feedback is employed, the commonmode input range of the telescopic first-stage is more
than sufficient. Also, the gain of the second stage of the
OTA will be high enough such that the limited output
range of the telescopic first stage has no effect on the
overall output swing of the OTA.
cascode/common-
The high dynamic range requirement of the circuit
is significantly easier to meet with a larger output
signal swing. Therefore, the regulated cascode, with its
cascoded devices on its output node, was deemed to be
a less favorable topology.
The three-stage common source cascade presents
three main disadvantages to its implementation. First,
its nested Miller compensation will narrow-band the
system, as each level of compensation tends to reduce
the bandwidth by a factor of two. Second, as the gain
of the first stage is only on the order (gmro) noise
contributions from the second stage will be
appreciable. Finally, as this OTA is to be fully
differential, a common-mode feedback circuit is
necessary for all topologies. It seems feasible that a
single CMFB circuit may not be enough to keep all
three stages in saturation [Flores96].
The tradeoffs between the other two topologies—
folded-cascode/common-source
and
telescopiccascode/common-source—are more subtle. Before the
tradeoffs are considered, we should first introduce the
primary characteristics desired for a two-stage OTA for
minimum power: [Feldman97]
1) minimum number of current legs,
2) minimum number of devices contributing
significant thermal noise, and
3) an all NMOS signal path
2.2
A folded-cascode stage has extra current legs which
dissipate more static power than a similar telescopic
stage. For a given settling constraint and a fixed
compensation technique, this extra current leg will in
effect double the power dissipated in the first stage of
the folded cascode in comparison to a similar
telescopic stage. Therefore, by criterion (1) presented
above, a telescopic stage is favorable to a folded stage.
A folded-cascode stage also has more devices
which contribute significant input-referred thermal
noise to the signal. The extra current source transistors
comprising the “fold” add directly to the noise factor of
the input stage. While the Vdsat’s of these transistor can
be increased to minimize the added noise, the extra
noise inserted requires a commensurate increase in
power dissipation for a fixed dynamic range
specification. Therefore, according to criterion (2)
listed above, the telescopic stage is preferable to the
folded stage.
With careful biasing, however, an OTA with a
folded-cascode first stage can consist of an all-NMOS
signal path while still achieving reasonable output
swing [Flores96]. An OTA with a telescopic first stage
cannot achieve such a signal path without either
Compensation Topology
As the OTA topology selected is multi-stage a
compensation technique is necessary. As described in
appendix C, we sought to design an OTA with 70
degrees phase margin at the unity-gain frequency of the
loop configuration. Standard Miller compensation can
be employed for a simple solution, but this
compensation technique introduces a zero is the right
half-plane. In order to increase phase margin,
techniques to push that zero out to infinity were
explored. Putting a resistor in the feedback path is one
possible solution. In order to achieve a reasonably
sized resistance without consuming an excessive
amount of chip area, transistors operating in triode
would be needed to be placed in the compensation
feedback path. This can be troublesome in low-voltage
topologies, as it can be difficult to maintain a linear
resistance in a triode device without a very high gate
voltage. Furthermore, the extra devices were deemed
an unnecessarily complex addition and alternate
solutions were looked into. Unilateral feedback could
also be employed, but it has been shown that such a
technique not only adds to total static power
consumption, but it also can limit slew rate and hence
2
degrade settling time. It was determined that the extra
power consumption needed to make the slew rate
limitation negligible was too excessive for the lowpower constraints of the design.
Instead, a variant of standard Miller compensation
was employed where the compensation capacitor is
connected to the drain of the input device (rather that
the drain of the cascode device). It has been determined
that such a technique pushes the right half-plane zero
out to infinity while adding another non-dominant pole
at the complex conjugate of the primary non-dominant
pole [Nakamura95]. As is shown in appendix C, this
technique will result in a better phase margin than
standard Miller compensation techniques and can lead
to a more power-conscious compensation technique.
3
noise level (refer to appendix A for the precise math).
Finally it is worth considering that the noise level will
be increased by the flicker noise contribution; this
expression for flicker noise power is:
2
2
o ,1 / f
v
The total noise power is the sum of these two
contributions.
3.2
Settling Time
The specification of settling time requires a settling
accuracy of 0.01% within a period of 100ns. This
specification can be directly translated into a trade-off
between ωu and the vdsat of the input pair, as a greater
ωu reduces the linear settling time and a greater vdsat
cuts down on the slewing time for a given voltage
swing.
As shown in appendix B, the settling time can be
expressed by the following equation:
DESIGN ANALYSIS AND
OPTIMIZATION
In this section, we present the results from our
analysis of the tradeoffs involved in meeting the
specifications presented. We will use these results in
presenting our device sizing in Section 4.
3.1
K g2   f 
 1  1  K fp

= 
+ fn m2 7  ⋅ ln  H 

 f FB  Cox W1L1 W7 L7 g m1   1Hz 
t settle =
2
ωu
 vi
1

−
 v dsat 2 f FB

 v
1
 −
ln  ξ i
 f FB ⋅ ω u  v dsat



Dynamic Range
The design of high resolution A/D converters sets
serious limitations on the allowable noise in the OTA
in order to keep the overall system resolution.
A typical requirement for this kind of system is a
dynamic range (DR) greater than 80 dB. Note that this
specification refers only to the amplifier noise and not
to noise of the overall system. Therefore the sampling
noise from switches, necessarily present in the
switched capacitor (SC) circuits, is not considered in
the following analysis.
DR depends on both the output swing and the
output noise power. Therefore a tradeoff between
achievable swing and injected noise has to be found. In
our design approach, the output swing was fixed to
2.2V (single-ended), considering the power supply
value and reliable values for the saturation voltages of
output stage devices.
As shown in appendix A, the output power for
thermal noise is given by:
vth2 = 2 KT
where vi is the maximum input swing seen, fFB is the
feedback factor (slightly greater than 3, due to the
parasitic input capacitance of the OTA), and ξ is the
required settling accuracy.
3.3
Open-loop Voltage Gain
As shown in appendix D, the gain of the telescopiccascode/common-source OTA is on the order of
(gmro)3. A more first-order precise calculation of gain,
leads to the following expression:
( ) (v
Avo = α1α 2 2 λ
3
sat
d1
⋅ vdsat3 ⋅ vdsat9
)
−1
where α1, α2 < 1 to account for the loading effects of
the current source loads of the first and second stages,
respectively. In order to maximize gain, it is desired to
keep the loading factors as close to unity as possible.
This is achieved by making the load transistors longer
than minimum length.
2 nf 1
,
3 f FB C C
3.4
where CC is the compensation capacitor, nf is the noise
factor of the amplifier and fFB is the feedback factor.
This relation clearly shows that a lower limit on the
size of CC is imposed, in order to limit the noise level.
Also, there is a lower limit on the sampling capacitor
(CS) even though CS does not appear explicitly in the
formula: indeed if CS is too small with respect to the
input pair gate capacitance, the 1/f term would be
appreciably higher than 3 and would result in a higher
Summary of Design Tradeoffs and
Optimization
As can be seen in the above analysis, each of the
OTA specifications present a set of constraints to be
met by setting circuit parameters appropriately. These
specifications put conflicting sets of constraints on the
circuit parameters, and an optimal (i.e. minimal power)
solution must be found within the subspace of
acceptable circuit parameter sets. This is a difficult
process not amenable to simple hand calculations as
the constraints cannot be reduced to a closed-form
3
problem. Therefore, in our design process, we used
simple hand calculations to set rough limitations on
acceptable parameters, and then we developed and
used a computer optimization technique to find an
approximate optimal solution. This process is described
in detail in appendix E. The results of the optimization
procedure are summarized in Table 2: all the saturation
voltages and currents for the circuit are determined,
therefore the OTA dimensioning can be now easily
obtained. These values refer to Figure 1 and the
expected performances for slow process parameters are
reported in Table 3.
Vdsat [mV]
0.983
1.5
1.5
0.46
1
150uA
200uA
Iss
I2
4.1
gm [mS]
160
100
100
320
350
300
M1/M2
M3/M4
M5/M6
M7/M8
M9/M10
M11/M12
between the previewed and the actual performance,
which are summarized in the following section.
1.5 pF
0.8 pF
Cc
Cs
Table 2: Results of optimization process
81.5 dB
468,750
72 ns
71°
2.3V
Dynamic Range
Gain
Settling time
Phase margin
Output Swing (s.e.)
Table 3: Theoretical results for slow parameters
from optimization parameters
V
V g0
Vg V +
C
M 11
1 1
i
D D
M0
M1
V - Vg
C
M2
i
Vg
V +
o
C
1 1
M 12
C
C
M3
3
M4
V o
C
S
M9
S
M5
Vg
5
Vg
7
M6
M7
M8
M 10
Design modifications
One of the parameters deviating significantly from
the ideal hand-analysis behavior has been the
transconductance of the input stage, which was roughly
20% lower than originally expected. This is due to the
fact that our optimization procedure did not account for
weak inversion effects; as in any power-conscious
design the input devices reside near the transition to the
weak inversion region. We accounted for the
transconductance sag by increasing the current of the
input pair slightly. It is worth noting that—before
compensating with an increased bias current—this
effect was significantly reducing the unity gain
bandwidth, therefore causing the system to be slower
than predicted.
Another deviation from ideal behavior is
represented by variation of λ as the width of the device
varies. This phenomenon directly reduces the second
stage gain. In the first approach, the length of output
devices was increased to enhance their resistance;
however the width was also increased in order to keep
constant the saturation voltage, and this resulted in a
balancing effect on λ, leaving the resistance
unchanged. Therefore in order to meet the gain
specification in worst-case conditions (fast parameters
process) a scaling of saturation voltages was necessary,
according to the relations developed in appendix D.
As a consequence of this last modification the
output swing is decreased; moreover in the ideal
calculation the minimum drain to source voltage across
the output devices was assumed to be exactly their
saturation voltage. In reality the output resistance of the
transistors starts to drop before such critical voltage is
reached. Therefore the overall gain is greater than
10,000 only for smaller voltage swing than predicted.
This drop accounts for a safety margin included in the
dynamic range calculation.
With this last modification, the OTA is
dimensioned and the device size and main parameters
are summarized in Table 4. The simulations result,
reported in Section 4.4 will show the performance
obtained by this design.
Figure 1: Two-Stage OTA
4
M1-M2
M3-M4
M5-M6
M7-M8
M9-M10
M11-M12
TWO-STAGE OTA
Although the design developed in the previous
section meets all the specifications according to hand
calculations, the real behavior of the used technology
deviates from the simple models used for hand
analysis. In fact the more precise models used by
SPICE have underlined some important differences
Size
(µm)
91.6/0.6
213.8/0.6
91.6/0.6
17.6/2.2
33/0.6
608/4.8
vdsat
(mV)
160
100
100
320
300
330
Ibias
(µA)
80
80
80
80
245
245
gm
(mS)
0.821
1.13
Table 4: Final Device Parameters
4
1.02
4.2
Common Mode Feedback
4.3
As shown in Figure 2 dynamic switch capacitor
common mode feedback circuit (CMFB) was
integrated into the OTA. As the OTA is a two-stage
amplifier, the common-mode gain from input to output
is a positive value, and therefore CMFB cannot be
applied directly from output to input; instead an
inversion is needed. The necessary inversion is created
by utilizing a differential pair; for instance, as the
common mode output goes down, transistor MF1 steals
additional bias current from the input pair, which in
turn raises the common mode output back to its
nominal value. As shown in Figure 3, the CMFB
circuit has an open loop gain of 11,000 and unity gain
frequency of 9.5 MHz. While this is lower than the
unity gain frequency of the OTA, it should be
sufficient as long as the common-mode input signal
does not have significant signal strength above the
CMFB circuit’s unity gain frequency.
Bias Network
The design of the bias network is a fundamental
step in the OTA project, as this part ensures that all
devices are working in the expected conditions. The
sub-circuits of the OTA which require to be biased are:
• second stage active load (M11/M12)
• input pair current source (M0)
• first stage cascode active load (M5 to M8)
• first stage input pair cascode (M3/M4)
• CMFB circuit
The bias network is shown in Figure 4, and is
explained in detail below.
V
MB1
Vg11
DD
MB3
MC7
MC1
MC6
MC3
I
CMFBRef
MB4
A
CMFBRef
B
MC5
Vg5
MC4
r ef
Vg3
C M F B re f
A
MB5
VCM 0
CMBias
Vg7
MC2
Figure 4: Bias Network
The second stage active load has been biased using
a mirrored version of the reference current, as the gate
of Mb1 is directly connected to the gates of M11 and
V + M12. The reference current is mirrored in the same
M F1
way in the input pair and in all the other bias lags. Note
C M F B re f
M F2
that non-minimum current and devices have been
V - chosen, in order to overcome mismatch in the mirrored
currents. Moreover it would be more difficult to
C M B ia s
overcome current differences using cascoded current
mirrors, because the power supply is quite low.
The biasing of the first stage active load is
particularly delicate: indeed, referring to the OTA
schematic, the voltage across the cascode M5-M7 is
C M F B re f V C M 0
fixed by the Vgs of M9, which can't be very high.
Figure 2: Common-mode Feedback Circuit
Moreover, during slew rate settling, M9 is expected to
turn off completely. Therefore, the voltage at the gate
of M9 is expected to go below threshold while still
keeping the first stage cascode well in saturation. For
these reasons a high-swing biasing has been chosen to
generate Vg5 and Vg7. This part of the biasing
network is formed by devices from MC1 to MC9.
The current in the second stage is fixed biasing
M7/M8, which is fed by a current mirror (MC2). The
gate of M5 has to be fixed at the lowest possible
voltage, without pushing M7 to the triode region,
therefore:
V
D D
o
B
o
B
vG 5 = vgs 5 + Vdsat
7
In reality we must account for a safety margin
(~100mV), because the output resistance of M7 will
start to decrease before the triode threshold. In the
adopted circuit the bias voltage vg5 is given by:
Figure 3: CMFB open-loop response
5
vg 5 = vgs 3 + vds 4
4.5
Table 6 shows the power breakdown of our circuit
as reported by SPICE. The power dissipation of the
first and second stage are reasonably low, comprising a
little less than 2 mW under all process parameters.
MC4 and MC5 are dimensioned in order to make Vds4
equal to the Vd7sat plus the safety margin. The
equation regulating the circuit are:
( )
( )

W
L5
V sat = V sat ⋅
d7
 d5
W
L7




W


sat 
L
5
vds 4 = Vd 5 ⋅ 1 − 1 −

W


L 4 


( )
( )
First Stage
Second Stage
CMFB network
Bias network
Total of first and
second stage
Total of entire
OTA
The circuit has been dimensioned in order to have
vds 4 = 1.18 ⋅ Vdsat
7
V
=V
sat
d5
Process
Nominal
485 µW
1480 µW
175 µW
1790 µW
Fast
490 µW
1490 µW
180 µW
1845 µW
1.94 mW
1.96 mW
1.98 mW
3.82 mW
3.93 mW
4.01 mW
The bias network consumes a large amount of power in
comparison to the power of the other parts of the
circuit. The power is purposefully made relatively
large, because large bias currents are used so that
matching problems are minimized when mirroring
currents.
⇒ vgs 3 = v gs5
Note that this circuit is also insensitive to body effect.
Typically, the cascoded input devices are biased
indirectly off of the common source of the input pair.
In a previous revision, this was attempted, but was
deemed unsuccessful. This is because, during slew rate
setting, one of the input devices is by definition turned
off. Therefore, the common source no longer appears
to be a virtual ground, thus causing the bias voltage of
the cascode device to deviate from its DC value. This
caused a slow-settling transient error, as the changing
bias on the cascode effectively modulated the output
voltage. Instead, a more robust biasing scheme—
utilizing MB4 and MB5—was used in order to create a
stable bias voltage on the order of vdsatB4. An added
improvement of this biasing scheme is the
independence of the bias voltage on VTH variations.
The references needed by the CMFB were
generated using currents mirrors and other diode
connected transistors.
4.4
Slow
480 µW
1460 µW
165 µW
1710 µW
Table 6: Power dissipation of two stage design
MC3 has the same dimension of M5 and is driving the
same current, so
sat
d3
Power Dissipation
4.6
Open-Loop Gain Simulation
Figure 5 to 7 show the DC open-loop gain response
of the circuit for all 3 processes. In each figure, the top
plot shows the double-ended output response and the
bottom plot shows the differential output. In all plots,
the x-axis is the input single-ended voltage—the input
differential voltage is simply twice that value. As can
be observed on all three plots, the DC gain remains
above 10,000 between +2.2V to –2,2V differential
output.
Results
The circuit was simulated in SPICE and a summary
of results are as follows:
DR (dB)
Av0
Settling time
Slow
80.3
43,700
79 ns
Process
Nominal
80.4
27,500
75 ns
Fast
80.6
17,000
68 ns
Figure 5: DC open-loop response, slow parameters
Table 5: Performance summary
As can be seen above, all specifications were met.
In fact, the settling time is well under specification.
Part of this is due to the fact that a fair amount of safety
margin was included in the original design in order to
ensure proper operation.
6
Figure 6: DC open-loop response, nominal
parameters
Figure 9: AC open-loop response, nominal
parameters
Figure 7: DC open-loop response, fast parameters
Figure 10: AC open-loop response, fast parameters
4.7
Frequency and Step Response
Simulation
Figure 8 to 10 show the AC open-loop response of
the circuit for all 3 processes. As derived in appendix
C, the phase margin is
 f ⋅I ⋅v
C 
φ m = 90 − 2 ⋅ tan −1  FB 1 dsat 9 s 
 I 2 ⋅ v dsat1 C c 
The plots show that all frequency responses have a
phase margin of approximately 70 degrees at fFBωu =
ωu/3. The plots show that the unity-gain frequency is
slightly higher for the fast process than the slow
process. This is to be expected, as the fast process has a
higher kp, and also has slightly higher bias currents.
Figure 11 shows the double-ended step response
used in transient simulations. The output transitions
from a +2.2V differential output to a –2.2V differential
output, with the input step applied at 350ns.
Figure 8: AC open-loop response, slow parameters
7
Figure 11: Typical step response
Figures 12 to 14 show the step response of the
differential output for each process. In all processes,
the transient settles to 0.01% of its final value within
80ns. The transient does display a static settling error,
but this is due to parasitic capacitive loading at the
input. In order to minimize this static error, gains much
greater than 10,000 would be necessary.
Figure 13: Step response, nominal parameters
Figure 12: Step response, slow parameters
Figure 14: Step response, fast parameters
8
4.8
Noise Simulation
In order to evaluate the dynamic range
performances the output noise density was calculated
by simulations. Figures 15 to 17 show the obtained
output noise densities for the three process parameters.
In Table 7, the corresponding dynamic range and noise
factor are reported. The former quantity has been
calculated integrating the noise density from 1Hz up to
infinity, due to the fact that the presence of switches in
the circuit will fold very high frequency noise into the
base band. Table 8 reports the noise power contribution
from each device. It should be noted that, in all cases,
devices other than M1/M2 and M7/M8 contributed a
total of less than 0.15% of the total noise density.
Figure 17: Noise density, fast parameters
Dynamic Range
80.3 dB
80.4 dB
80.6 dB
Slow
Nominal
Fast
Noise factor
1.37
1.35
1.34
4.9
Table 7: Dynamic Range and Noise Factor
Slow
M1/M2
M7/M8
Th
72%
28%
1/f
67%
33%
Nominal
Th
1/f
73%
71%
27%
29%
Fast
Th
74%
2%6
Design Summary
As shown in the previous sections, the hand
analysis of the circuit was supported by a computerbased optimization routine, in order to find the
minimum power solution for the design. This analysis
was then calibrated and modified in order to
compensate for the main discrepancies between the
ideal model and the actual behavior of the circuit. This
approach has lead to a design solution which can be
addressed as minimum power while meeting the
specifications required by the specific application of
the pipelined A/D converter. As SPICE simulations can
present some errors, deviating from real circuit
operation, a safety margin is advisable. We can say that
the proposed solution satisfies this criterion, with the
exception of the DR values. However increasing the
DR requires a substantially bigger capacitor; as this
implies a increase the currents by the same amount, it
is to be avoided.
1/f
77%
23%
Table 8: Thermal and Flicker Noise Contributions,
by device
5
CONCLUSIONS
The OTA presented is a two-stage amplifier. Its
first stage is a PMOS telescopic cascode, and the
second stage is a common-source gain stage. It is
compensated using a variant of standard Miller
compensation, where the compensation capacitor is
connected to the drain of the input device rather than
the drain of the cascode device. The OTA meets all
performance specifications with a reasonable safety
margin across all process variations, and dissipates
slightly less than 2 mW of power.
We believe that this OTA is a good design for a
two-stage OTA with the required specifications. As
discussed in section 2, the use of a telescopic first stage
will give roughly the same performance/power tradeoff as a folded first stage, and the compensation
technique allows for a more power-conscious design
while keeping 70 degrees of phase margin. It is
Figure 15: Noise density, slow parameters
Figure 16: Noise density, nominal parameters
9
conceivable that a lower power design could be
obtained with this topology for the following two
reasons. First of all, in our optimization technique, we
did not take into account weak inversion effects of the
input pair. Therefore, in modifying the design for
SPICE verification, the device sizes did not “track” the
optimal
transconductance/power
trade-off
as
determined by SPICE. Also, our design has a good
degree of safety margin included in it. In particular, the
settling time for the slow process has a safety margin
of roughly 20%. This margin could be reduced by
reducing the input pair bias current, and thus the total
power could be reduced. Still, due to process and
performance variations not modeled by SPICE, we
believe that this safety margin makes our design more
realizable in real-world applications.
The CMRR and PSRR of this circuit will be
reasonable, but not exceptional. Both of these measures
could have been improved by raising the output
resistance of the input current source. Such a
modification could be achieved by cascoding the input
current source. This was not pursued, as the lowvoltage power supply and telescopic structure of the
first stage did not leave enough voltage headroom for
such a modification.
Due to the high output resolution of the A/D system
being designed, it seems as if device matching would
present a very difficult problem. Indeed, with 13-bit
precision, a single LSB error is only 268 µV.
Therefore, common-centroid layout techniques and
offset-cancellation circuitry in the SC structure seem a
necessity in order to keep overall system resolution.
density from an RC circuit; therefore the output power
noise can be expressed as:
vo2,th = KT
f FB =
vi2,1 / f
K fn g m2 7 
1 1  K fp
=
+
,

∆f
f C ox  W1 L1 W7 L7 g m2 1 
where f indicates a frequency and the other parameters
have the usual meaning. As the corner frequency of
flicker noise will be lower than the dominant pole of
the amplifier, this noise is not band-limited by the
OTA, therefore the output power is directly the integral
of the noise density, multiplied by the squared
feedback factor, to refer to the output of the amplifier.
So the noise power for flicker noise becomes:
2
2
o ,1 / f
v
∆f
= 4 KT
V
DR(dB) = 10 ⋅ log 10  sw
 2

(
2 Vo 2,th
1
+ Vo 2,1 / f
)




B. SETTLING TIME CALCULATIONS
Settling time consists of two components: slew rate
settling and linear settling Slew rate limited settling is
due to the class A configuration of the OTA and the
limited amount of current the first stage of the
amplifier can deliver to charge up the compensation
capacitor. As derived in lecture, the slew rate is:
2 nf
,
3 g m1
where gm1 is the transconductance of the input device
and the noise factor, n f = 1 +
K fn g m2 7   f H 
 1  1  K fp

= 
+
⋅ ln 


2 
 f FB  Cox W1L1 W7 L7 g m1   1Hz 
where the upper integration limit fH has to be chosen
higher enough than the corner frequency.
Finally the total output noise power is given by the
sum of the two powers calculated, multiplied by two, to
account for the doubled structure of the differential
amplifier. The expression for dynamic range then
becomes:
The total output noise power in a two-stage
compensated OTA can be obtained by considering the
input referred noise density of the amplifier. For
simplicity we consider thermal and flicker noise
separately, starting with the former.
The input referred thermal noise density, can be
expressed as
v
Cs
3C s + C gs1
where fFB is the feedback factor for the closed loop
configuration of the amplifier.
In a similar way the input density for the flicker
noise can be considered:
A. NOISE ANALYSIS CALCULATIONS
2
i ,th
2 nf 1
3 f FB CC
Vdsat
1
, is accounting for
Vdsat
7
SR = Iss/Cc
the contribution to noise of other devices in the
amplifier.
Approximating the frequency response of the
amplifier with a single pole response, where the
dominant pole in determined by the compensation
capacitance CC, the calculation of noise power can be
simply expressed as the known integral of the noise
which yields a slewing time of:
t slew =
10
2
ωu
 vi
1

−
 v dsat 2 f FB



where vi is the maximum differential voltage swing
seen at the input and fFB is the feedback factor. The
maximum voltage swing seen at the input will be 2.2V,
as the output has a differential swing of 4.4V (+2.2V to
–2.2V). Also, the feedback factor will be slightly
greater than 3, due to the input parasitic capacitance of
the OTA.
The linear settling time is:
t linear = −
 v
1
ln  ξ i
f FB ⋅ ω u  v dsat
The compensation technique used is not standard
Miller compensation. Instead, it is a variant of this,
where the compensation capacitor is attached to the
drain of the input device rather than the drain of the
cascoded device. The end result of this compensation is
to push the right-half plane zero out to infinity and
introduce a new non-dominant pole at the complex
conjugate of the first non-dominant pole. As the zero is
pushed out to infinity, there is no concern over a polezero doublet occurring near the frequency band of
concern. This compensation technique increases phase
margin slightly over standard Miller compensation as
the frequency location of the Miller zero is:



which yields a total settling time of:
t settle =
2
ωu
 vi
1

−
 v dsat 2 f FB

 v
1
 −
ln  ξ i
 f FB ⋅ ω u  v dsat



zero =
and the frequency of the new pole is:
pole =
The above results are based on the assumption that
the slew rate is set by the slewing capability of the first
stage and is not at all limited by the slewing of the
second stage of the OTA. In order for this assumption
to be correct, two conditions must hold, namely:
(1)
(2)
g m9
ωu
g m1
g m 9  Cc

g m1  C s

ω u

Therefore, for Cc greater than Cs, (which is always the
case), the additional pole is at a higher frequency than
the old zero. Thus, a net gain in phase margin is
obtained.
As the OTA has a global feedback network with a
feedback factor of roughly 1/3, the phase margin is
measured at the location where the open-loop gain is
approximately 3. The equation for phase margin
becomes:
The drain of the cascode devices must be able
to completely turn off the NMOS transistor in
the second stage.
The current supplied by the PMOS load of the
second stage is sufficient to supply the
necessary current to the slew-limited first
stage and simultaneously supply enough
current to charge up the load capacitance.
 f ⋅ω
φ m = 90 − 2 ⋅ tan −1  FB u
 ω
p1





Making some simple substitutions:
The first condition is met by biasing the NMOS
loads of the first stage with a high-swing biasing
technique—as described in Section 4.3—to allow the
output voltage of the first stage to go below the
threshold voltage of the second stage input. The second
condition is met by setting the second stage bias
current as follows:
 C + Cs
I 2 ≥ I1  c
 Cc
 f ⋅I ⋅v
C 
φ m = 90 − 2 ⋅ tan −1  FB 1 dsat 9 s 
 I 2 ⋅ v dsat1 C c 
This expression for phase margin, with a requirement
of 70 degrees, was used in the optimization procedure
in order to size the devices correctly.



D. DC GAIN CALCULATIONS
It can be shown that the DC gain for a two-stage
telescopic-cascode/common-source is as follows:
where I2 is the bias current of M9 and M10 and I1 is the
bias current of M1 and M2.
Av 0 = g m1 [(ro1 g m 3 ro 3 ) (ro 5 g m 5 ro 7 )]× g m 9 (ro 9 r011 )
C. PHASE MARGIN CALCULATIONS
If the following substitutions are made:
g m = 2 I vdsat and ro = 1 λI
Dynamic range calculations discussed in appendix
A set rough guidelines on the value of Cc, and feedback
factor requirements set rough guidelines on the value
of Cs. With the parameters set as outlined above, the
requirements for 70 degree phase margin can be
calculated.
the equation for gain can be expressed as follows:
( ) (v
Avo = α1α 2 2 λ
11
3
sat
d1
⋅ vdsat3 ⋅ vdsat9
)
−1
where α1, α2 < 1 are attenuation factors due to the
parasitic resistance of the current source loads. The
above expression shows an inverse relationship
between open loop gain and the vdsat’s of the transistors
in the signal path. This relationship was used in the
optimization procedure to size the signal path
transistors in order to meet the required gain
specification.
It is worth noting that the above expression is only
correct to the first order. This is due to the assumption
that λ is independent of device width. While this is
assumed to be true in first-order transistor models, it
does not hold in actual process parameters. Therefore,
the above expression was used as a guideline, but a
gain safety margin was included in the optimization
procedure in order to compensate for λ inaccuracies.
requirements, another relation limit is imposed on I2
and this time the lower limit in decreasing as a function
of Vd1sat. The two relations are reported below:

 2  Vstep 3  3  Vstep  
CsVdsat
9
I 2 ≥
−  − ln  ε sat  
 

2  ts  Vd1  
 90° − ϕm   t s  Vdsat
1
6 tan 


2



sat
I 2 ≥ Vd1 ωu (CC + Cs ) 1
2

As it can be easily observed, these two constraints let
us find an optimum point, where both the inequalities
are satisfied and the current is minimum: that value has
been assumed for Vd1sat.
Once determined Vd1sat, Vd7sat can be fixed in order
to satisfy the requirement chosen for the noise factor.
Finally the two input cascodes are to be dimensioned.
Their saturation voltages have been chosen as low as
possible: this criterion leads to an easier biasing, boosts
the gain (see appendix D), and helps move the second
non-dominant pole introduced by the compensation
network to a higher frequency.
As mentioned in Section 3, this procedure allowed
us to determine all currents and saturation voltages for
the OTA. Therefore the transistor dimensioning
becomes straightforward. According to the developed
math, these values are the minimum power
compromise which meets the required specs; in reality
currents and capacitor values have been increased to
grant a safety margin in the real circuit.
E. OPTIMIZATION ROUTINE
In the previous appendix, various circuit
characteristics were expressed analytically as functions
of circuit parameters. The assigned specifications can
be used with these relations in order to dimension the
amplifier. However some degrees of freedom are left
and finding an optimum solution in terms of power
dissipation becomes a challenge. For this reason the
various relations were combined to find a target
functions that was minimized in order to find the
minimum power configuration.
As a first step the output swing and the noise factor
were fixed to some achievable values (respectively
2.2V and 1.5). The value of output swing allows the
calculation of the maximum saturation voltages for the
output stage and the amplitude of the input step for
settling time testing. Moreover fixing these parameters,
from the dynamic range expression, it is possible to
determine the value for CC. CS was arbitrarily fixed at a
value that would not overly degrade the feedback
factor.
At this point we can choose the saturation voltage
of M1/M2 in order to minimize the total current. From
appendix B, ISS results a function of ωu and Vd1sat;
however ωu can be expressed as a function of Vd1sat;
therefore Iss only depends on Vd1sat:
I ss ≥
[Cho95] Cho, T. “Low-Power, Low-Voltage Analogto-Digital Conversion Techniques using Pipelined
Architectures.” PhD Thesis, University of
California, Berkeley. 1995.
[Flores96] Flores, A., Daniel, L., “Design of a
Minimum Power, Low-Voltage Supply FullyDifferential Transconductance Amplifier for A/D
Converters.” EE240 Project Report. University of
California, Berkeley. 1996.
[Feldman97] Feldman, A. R., “High-Speed, LowPower Sigma-Delta Modulators for RF Baseband
Channel Applications.” PhD Dissertation,
University of California, Berkeley. 1997.
[Nakamura95] Nakamura, K., Carley, L., “An 85mW,
10b, 40 Msample/s CMOS Parallel-Pipelined
ADC.” IEEE Journal of Solid-State Circuits, Vol.
30, No. 3, March 1995.
2CC 
3 sat  3C sat  Vstep 
Vstep − Vd1  − c Vd 1 ln  ε sat 
2
ts 
 ts
 Vd1 
This relation is a monotonically increasing function
of Vd1sat. Therefore to minimize the current in the first
stage we can minimize the saturation voltage of input
devices. However the current in the second stage also
has to be considered. From phase margin requirements,
I2 can be expressed as a function of ISS/Vd1sat, therefore
again as a function of only Vd1sat, which in this case is
monotonic decreasing. Moreover from slew rate
12