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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 3, MAY 2008
Three-Phase Three Level, Soft Switched, Phase
Shifted PWM DC–DC Converter
for High Power Applications
Dharmraj V. Ghodke, Member, IEEE, Kishore Chatterjee, and B. G. Fernandes
Abstract—A new three-phase, three-level dc to dc phase shifted
pulsewidth modulation (PWM) converter is proposed for high
power and high input voltage applications. Output voltage is
controlled by incorporating phase shift PWM. Clocked gate
signals of each leg are phase shifted by 2 3 from each other.
Major features of the converter include: 1) outer two switches of
each leg are turned on and off as zero voltage switching, 2) inner
two switches of each leg are turned on and off as zero current
switching, and 3) this is achieved without involving any extra
passive or active components. The secondary side of the converter
is of center tapped full-wave current tripler type. This results in
an increase of ripple frequency by a factor of six, leading to a
significant reduction in size of the output filter. In order to obtain behavioral and performance characteristics of the proposed
converter topology, detailed analytical and simulation studies
are carried out. Finally the viability of the scheme is confirmed
through detailed experimental studies on a laboratory prototype
developed for the purpose.
Index Terms—High power dc to dc converter, soft switching,
three-phase three-level (TPTL), zero voltage zero current
switching (ZCS).
I. INTRODUCTION
VER the years single phase full-bridge (FB) and
three-phase FB pulsewidth modulation (PWM) dc to
dc soft switched converters have become popular in the field
of dc to dc conversion system. For these converters metal
oxide semiconductor field effect transistors (MOSFETs) are
generally preferred over insulated gate bipolar transistors
(IGBTs), because they can be operated at higher switching
frequency and they do not have the problem of long tail current.
However, these FB PWM soft switched converters are not
suitable for switch mode power supply applications, where
the input voltage is high. This is because the MOSFETs have
to sustain high input dc link voltage. Moreover, service of
auxiliary circuits is required to operate devices in soft switched
mode. This requires extra components, devices and hence it
O
Manuscript received August 18, 2006; revised August 3, 2007. This paper
was presented in part at the IEEE PESC’05, Recife, Brazil, June 12–17, 2005.
Recommended for publication by Associate Editor J. Kolar.
D. V. Ghodke is with the Laser System Engineering Division (LSED), Raja
Ramanna Center for Advanced Technology, Indore 452013, India and also
with the Department of Electrical Engineering, Indian Institute of Technology
Bombay, Mumbai 400076, India (e-mail: dvghodke@cat.ernet.in).
K. Chatterjee and B. G. Fernandes are with the Department of Electrical
Engineering, Indian Institute of Technology Bombay, Mumbai 400076, India
(e-mail: kishore@ee.iitb.ac.in; bgf@ee.iitb.ac.in).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2008.920881
leads to incurring additional cost while reducing the system
reliability. In order to reduce the voltage stress to half of the
input dc voltage, a three-level topology has been considered in
[1] and [2] for inverter application and it has been used for realizing a dc to dc converter in [3]–[5]. The soft commutation is
achieved by using phase shift PWM modulation [4], [5] which
is having simple control structure and high power density can
be achieved. However at high power levels, these components
experience considerable current stress. In order to overcome
this problem, topologies consisting of three-phase inverter coupled to a three-phase high frequency transformer followed by
three-phase high frequency bridge-rectifier have been proposed
[6]–[9]. This results in an increase in the input current and
output current frequencies by a factor of three as compared
to the full bridge converter. This also results in lower current
rating for the components and also a considerable reduction
in size for the isolation transformer. However, the devices
experience high voltage stress and the control structure is also
quite involved. In an effort to overcome the aforementioned
limitations a new converter topology involving three-phase,
three-level, (TPTL) phase shifted PWM converter involving
six switches operating as zero voltage switching (ZVS) and
six switches operating as zero current switching (ZCS) has
been presented in this paper. It should be mentioned that in this
case soft switching of the semiconductor devices is achieved
without taking help from any additional auxiliary circuitry
comprising of active or passive elements. In the proposed
topology the output rectifier is a center tapped full wave current
tripler [10], [11] producing either two or three-level output
voltage depending on the operating duty cycle. This leads to
considerable reduction in size of the output filter compared to
that of the conventional full bridge topology.
The principle of operation and exhaustive analytical studies
for the proposed converter is presented. In order to obtain behavioral and performance characteristics of the converter, detailed
simulation studies are carried out. Finally the viability of the
scheme is confirmed through detailed experimental studies on a
6.6 kW laboratory prototype developed for the purpose. Finally,
extension of the proposed converter for different output voltage
and multiphase configurations has been illustrated.
II. PROPOSED SOFT SWITCHED DC TO DC CONVERTER
A. Power Circuit Configuration
The power circuit configuration of TPTL dc to dc converter is
shown in Fig. 1. Each leg is having four switches, two clamping
diodes and one coupling flying capacitor. Considering the first
leg top and bottom switches S1 and S4 are controlled by signals
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GHODKE et al.: TPTL, SOFT SWITCHED, PHASE SHIFTED PWM DC–DC CONVERTER
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Fig. 1. Proposed three-phase three-level (TPTL) soft switched dc to dc converter.
A and and inner switches S2 and S3 are controlled by signals B and respectively. The same logic is followed for the
other two legs of the converter. Duty cycle of 0.5 is maintained
for each switch. A short turn on delay is introduced to eliminate cross conduction. Signals A and B (similarly signals C & D
and E & F of other phases) are having uniform phase shift from
each other in a range of 0 to 120 in order to control the output
voltage. Further, the switching signals of the adjacent legs (A,
C, and E) are phase shifted by 120 with respect to each other.
Three high frequency single-phase transformers, with star connected primary, are employed to obtain the required isolation between primary and secondary side. At the secondary side, three
single-phase, center tapped full wave rectifiers are connected in
) across
parallel through three-output filter inductors
a common output filter capacitance . The three centre tapped
rectifiers are being fed by three single phase transformers. Three
primary windings of these three transformers are connected to
the three legs of three level inverter. Output current of the rectifier is the sum of the output currents of three single-phase center
tapped full wave rectifiers. As there exists a 120 phase difference among the transformer secondary voltages, the frequency
of the full-wave output voltage is six times to that of the inverter
frequency. The junction of diodes, D1 and D2, D3 and D4, and
D5 and D6 are all connected together to form the common node
point, .
B. Principle of Operation
In order to achieve output voltage control while realizing ZVS
for outer switches (S1 and S4) and ZCS for inner switches (S2
and S3), a phase shifted PWM (PSPWM) is adopted for each
phase. The switch-timing diagram for the range of duty cycle,
from 0 to 1/3 is shown in Fig. 2, for the range of from 1/3
to 2/3 is shown in Fig. 4 and for the range of from 2/3 to 1 is
shown in Fig. 6.
Following assumptions are made for the purpose of analysis.
All power devices except the outer switches of each leg
are considered ideal. Outer switches of each leg (S1 and
< D <1/3.
Fig. 2. Switch-timing diagram for duty cycle 0
S4, S5 and S8, S9 and S12) are considered along with its
parasitic capacitance.
Capacitors C1 and C2 are large enough to be treated as
voltage sources having a magnitude of
2.
Flying capacitors C3-C5 are large enough to be treated
2.
as a voltage sources having magnitude of
Effect of magnetizing inductance of the three-phase high
frequency transformer has been neglected.
Output filter inductors are large enough to be treated as
constant current sources during a switching period, so that
each filter inductor carries current of magnitude
3.
Operating modes for 0
1/3:
Mode-1 ( to ), [Fig. 2] and [Fig. 3(a)]: Before the initiation of this mode, the switches S1, S3, S6, S8, S9, and S11
are on, so the node points,
and
are all connected to
the dc link mid point, . As a result the primary voltages of the
transformer are zero. Moreover, the primary current of transformer-B is carried by the primary winding of transformer-C
therefore, primary current of transformer-A is zero. As all the
primary winding voltages of the transformer is zero, output current of each filter inductor present in the secondary side of the
transformer, is free-wheeling through output rectifying diodes,
D7–D12. Mode-1 is initiated when switch S3 is turned off and
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 3, MAY 2008
switch S2 is turned on at
. As a result
starts increasing
and
starts decreasing. The switch S2 turns on as ZCS, due
to presence of transformer leakage reactance in series with it.
is less than
As long as primary current of transformer-A,
the corresponding reflected secondary load current
, rectifying diodes D7 and D8, continue to conduct. This leads to
clamping of both the primary and secondary winding voltages
of the transformer to zero. The current
flows from the positive dc rail to the leakage inductance of the phase-A transformer.
Then it flows through two equal leakage inductances of phase-B
and phase-C of the transformers. These currents then finally terminate at positive plate of capacitor, C4 and negative plate of
capacitor C5. The potential of positive plate of C4 and nega2 respective to the negative dc rail,
tive plate of C5 are both
Hence positive plate of C4 and negative plate of C5 and negative plate of C1 are all having the same potential. The effective
inductance present in the current path is (3L )/2, therefore
(1)
this mode ends when
current at
and
becomes equal to the reflected load
0. therefore
(2)
Mode-2 ( to ), [Fig. 2] and [Fig. 3(b)]: After instant,
power from the primary side of the transformer is transferred
to the load. Diode D8 turns off and D7 carries one third of the
2. As priload current. Primary voltage of transformer-A is
mary currents of transformer B and transformer C are less than
reflected secondary current, voltages across windings of transis virformer B and transformer C are zero. Thus the node
tually at same potential as that of node . Primary windings of
, where n is turns
the transformers B and C will carry
ratio of the transformer.
Mode-3 ( to ) [Fig. 2] and [Fig. 3(c)]: At , S1 is
turned off. The primary current of transformer-A,
charges
and discharges
via flying capacitor C3. This happens
and
.The capacitor
and
limit the rate
as
of rise of voltage across S1, thereby rendering it the property of
effectively is in series with L1,
ZVS. During this mode,
and L1 can be treated as a constant current source. Hence, the
primary current
is
. Voltages across
and
can be expressed as
(3)
(4)
At
a result
rises to
and
decays down to zero. As
and
are having the same potential. Therefore,
(5)
Where,
Mode-4 ( to ), [Fig. 2] and [Fig. 3(d)]: From instant
, body diode of S4 starts conducting and this provides zero
0. A small difference
voltage turn-on condition for S4 as
in voltage between the mid point potential and the voltage on
C3 will get applied across leakage inductance of the primary
to decrease. If
is not decreased
winding, which causes
to zero, switching of other leg forces it to zero. As
is less
than the reflected secondary current, diode D7 and D8 start conducting simultaneously and therefore clamps both the primary
and secondary voltage of the transformer to zero.
The above switching sequence gets repeated for S7 and S8
during to ; and for S10 and S9 during to .
2/3 Mode:
Operating modes for 1/3
Mode-1 ( to ) [Fig. 4] and [Fig. 5(a)]: Before the initiation of this mode, switches S1, S3, S6, S8, S11, and S12 are
, and
are connected to the mid
on, so the node points,
is connected to the
point of the dc link, N and the node point
-ve rail of the dc link. As a result voltage across transformer-A
2 is applied across the priand transformer-B is zero and and
mary winding of transformer-C. Hence, node points
are at same potential. Primary windings of transformer-B and
and
transformer-C are carrying current
0. The currents through filter inductors, L1 and L2 are
free-wheeling through the respective output rectifying diodes,
D7–D10 and the current flowing through the filter inductor L3,
3 which is carried by D12. Mode-1 is initiated when S3 is
is
. The switch S2 turns
turned off and S2 is turned on at
on as ZCS, due to presence of transformer leakage reactance in
series with it. As long as the primary current of transformer-A,
is less than the corresponding reflected secondary load cur, rectifying diodes D7 and D8 continue to conduct.
rent
This leads to clamping of both the primary and secondary volt2 is applied across
ages of the transformer-A to zero.
as a result
rises linearly in the
direction and at the same
starts decresing. The expression for
for this mode
time
is given as
(6)
becomes equal to the reflected load current and
At
becomes zero. The duration of this mode is therefore
(7)
Mode-2 ( to ) [Fig. 4] and [Fig. 5(b)]: In mode-1, the
is equal to
primary current of the transformer-C,
and is carried by S11 and S12. From onwards, primary curalso becomes equal to
as a
rent of transformer-A,
result D8 turns off and D7 carries one third of load current. The
voltage applied across the primary winding of transformer-A is
2 and voltage across transformer-B is zero. Therefore node,
is at same potential as that of N, and nodes
and
are
connected to ve rail and ve rail of the dc link voltage respectively. As a result the primary winding of transformer-B will
carry the difference of ripple currents of the two filter inductors
which is negligible (around 0.02 p.u to 0.03 p.u) from all practical considerations, even though devices S6 & S8 are ON. In
this mode leg-B is not carrying any current, therefore if whenever S6 is switched off or S7 is switched on subsequently they
will do so as ZCS.
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GHODKE et al.: TPTL, SOFT SWITCHED, PHASE SHIFTED PWM DC–DC CONVERTER
1217
(a)
(b)
(c)
(d)
Fig. 3. (a) Equivalent circuit for mode-1. (b) Equivalent circuit for mode-2. (c) Equivalent circuit for mode-3. (d) Equivalent circuit for mode-4.
Mode-3 ( to ) [Fig. 4] and [Fig. 5(c)]: At , S12 is
charges
turned off. The primary current of transformer-C,
and discharges
, limiting the rate of rise of voltage
across S12 thereby imparting it the property of ZVS. Leakage
is in series with L3. As L3
inductance of transformer-C,
is large enough, primary current magnitude remains almost con. The voltage across
rises linearly and the
stant at
decays linearly whose expressions are
voltage across
(8)
(9)
At
rises to
2 and
decays to zero. The pois
2. The interval of this mode is,
tential of the node,
therefore
(10)
where
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 3, MAY 2008
C. Switching Behavior of Outer and Inner Switches
The outer switches operate as ZVS. The ZVS operation of
outer switches is explained by considering switches S1 and S4.
The remaining outer switches, S5, S8 and S9, S12 will also
behave in similar fashion. When S1 is turned off, the switch
, thereby charging this capaccurrent flows through the
. This charging and
itor and discharging other capacitor
discharging current mainly depends on the phase inductance,
which consists of the transformer leakage inductance and reflected dc filter inductance of each phase. If the total phase inductance is large enough, the switches can achieve ZVS with
fairly low load current. The outer switches are turned off at the
end of power transfer mode, and the reflected load current in
and discharges
. The enthe primary winding charges
ergy stored in the large dc filter inductor is responsible for introducing this duration of charging and discharging so that the
switches operate as ZVS. As the switches are turned on while the
body-diodes are conducting, they do so at zero voltage and zero
current condition. However, turn-on losses will be incurred if the
snubber capacitors are not fully discharged when the switches
are turned on. This can be avoided if it is ensured that the load
draws a minimum current, having magnitude
(11)
< D <2/3.
Fig. 4. Switch-timing diagram for duty cycle 1/3
Mode-4 ( to ) [Fig. 4] and [Fig. 5(d)]: From the instant
, body diode of S9 conducts which provides zero voltage turn
with respect
on condition for S9 as the potential of the node
is zero. Node
is connected to the
dc
to the node,
and
are connected to the node, . The prirail and node
is less than the reflected load
mary current of transformer-C,
current. As a result D11 and D12 conduct simultaneously. This
clamps both the primary and secondary voltages of the transformer-C to zero.
The above switching sequence is repeated for S6 and S7
to , wherein S6 is turned off and S7 is turned on
during
at zero current. Similarly during to , S1 is turned off and
S4 is turned on as ZVS. During to , S11 is turned off and
to
S8 is
S10 is turned on as a ZCS. And finally, during
turned off and S5 is turned on as a ZVS.
1: The switch-timing diaOperating modes for 2/3
1 is shown in Fig. 6.
gram for the range of duty cycle, 2/3
There are 12 operating modes in a switching half cycle. Output
voltage becomes nearly independent of the duty cycle variation
and remains almost constant. It is not a usable range of operation
for closed loop control, so the switching states are not explained
in detail.
The inner switches operate as ZCS. The ZCS operation of
inner switches is explained by considering the example of
switches S2 and S3. The remaining inner switches, S6, S7 and
S10, S11 will also behave in similar fashion. While turning
on, the leakage inductance of transformer which is in series
with the switch helps to turn it on as ZCS. Moreover, this
ZCS behavior of the switch is independent of the reflected
load current at the primary side of the transformer. Current
carried by a conducting switch depends on currents of other
two phases. When the upper switch of one phase and the lower
switch of remaining phase are on, the current flowing through
the switch becomes zero thereby accomplishing ZCS condition
for the switches while they are getting turned off. Hence ZCS
condition for the switches has been achieved without involving
any additional resetting circuit. The necessary condition for
accomplishing ZCS is that the reflected load current should
be higher than the magnetizing current of the transformer and
also the current flowing through the filter inductance should be
continuous.
D. Steady State Transfer Characteristic
2/3: The output voltage waveform
For Duty Cycle, 0
2/3 is shown in Fig. 7. Voltage apof the rectifier for 0
plied across any one of the output filter inductors, (L1–L2) in a
switching cycle is
(12)
Defining
as
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GHODKE et al.: TPTL, SOFT SWITCHED, PHASE SHIFTED PWM DC–DC CONVERTER
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(a)
(b)
(c)
(d)
< D < 2/3]. (b) Equivalent circuit for mode-2, [1/3 < D < 2/3]. (c) Equivalent circuit for mode-3, [1=3 < D <
< D < 2/3].
Fig. 5. (a) Equivalent circuit for mode-1, [1/3
2/3]. (d) Equivalent circuit for mode-1, [1/3
Considering
0
hence
(14)
The average of the sum of the any one of the filter inductor
voltage, which is the output voltage is given by
(13)
and
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 3, MAY 2008
Fig. 8. Controller configuration for the proposed TPTL dc to dc converter.
For Duty Cycle, 2/3
1: If the device capacitance and
leakage inductance of the transformer are neglected the output
voltage for this range of duty cycle variation can be shown as
(16)
As the output voltage is independent of duty cycle in this
mode, this mode does not have any significance so far as closed
loop control of the converter is concerned.
E. Control Strategy
Fig. 6. Switch-timing diagram for duty cycle 2/3
The schematic block diagram of the controller for the proposed TPTL dc to dc converter is shown in Fig. 8. It consists
of a single voltage controller loop, three phase shift PWM controllers (UCC3895N), 660 kHz oscillator, divide by three-ripple
counter, clock distribution and phase synchronization circuit.
The single voltage controller loop feeds the compensated error
to the PWM controllers. This signal
is
voltage
common for the three PWM controllers. The distribution logic
block synchronizes the ramp signals of PWM IC’s for phase
shift control so that the clock pulse for each PWM controller is
having an 120 phase shift from each other.
< D <1.
F. TPTL Small Signal Model
Fig. 7. Rectified output voltage of the three phases of the converter for 0
D <2/3.
<
which on simplification leads to
(15)
The power stage of the proposed TPTL phase shift dc
to dc converter along with the transformer and rectifiers
can be replaced by three equivalent pulsating sources,
(
and ) as illustrated in
Fig. 9(a). The frequency of each source is 2 , where,
is switching frequency of the converter. These pulsating
sources can be averaged over a switching cycle. As each
pulsating source is in series with a large filter inductor,
each of these sources can be replaced by a single source
,(
and ) as shown in Fig. 9(b).
The frequency of this equivalent source is
. This equivalent
source is in series with the equivalent filter inductance and
and
equivalent leakage inductance,
, here
2/3 for 0
1/3 and
1 for 1/3
2/3. As
is considerably small compared to
, its effect can be neglected. The equivalent model of the
system is shown in Fig. 9(e). Considering the equivalent series
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GHODKE et al.: TPTL, SOFT SWITCHED, PHASE SHIFTED PWM DC–DC CONVERTER
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Fig. 10. Simplified average model of TPTL.
Fig. 9. Deduction of average model of TPTL.
resistance of filter inductor and the output filter capacitor as
shown in Fig. 10, the transfer function of the TPTL converter
system s-domain can be expressed as
Fig. 11. Open loop frequency response of TPTL.
(17)
where
and
(18)
is load resistance,
is output filter capaciwhere the
is the equivalent series resistance of filter inductance,
is equivalent series resistance of output filter capactance,
is equivalent output filter inductor. The open loop freitor,
quency response of the system is shown in Fig. 11. The param350 H,
1330 F,
eters chosen for the purpose are
1.833
0.001
0.0167
600 V,
100 V.
III. SIMULATION AND EXPERIMENTAL RESULTS
To confirm the validity of the proposed scheme detailed simulation studies are carried out using MATLAB power system
800 V,
blockset. The parameters chosen for simulation are
60 V,
6 kW
100 kHz. Simulation perfor2/3 are
mance results for the range of duty cycle, 0
shown in Figs. 12 and 13. Fig. 12(a) shows the voltage across
S2 (inner switch) and the current flowing through it and these
quantities during turning on instant are shown on extended time
scale in Fig. 12(b). It can be inferred from the aforementioned
figures that S2 behaves as ZCS while turning on and turning
off. Fig. 13(a) shows voltage across S1 (outer switch) and the
current through it. When the device is turned off, the current
flowing through it charges the snubber capacitor present across
S1. While S1 is getting turned the current initially flows through
the body diode of the device. Therefore, the device behaves as a
ZVS during turn-on and turn-off transient. This behavior of the
device is depicted in Fig. 13(a) and (b). It can be inferred from
these figures that the inner switches of a leg of the converter
are operated as ZCS and that the outer switches of a leg of the
converter are operated as ZVS. In order to verify the viability
of the scheme detailed experimental studies are carried out on a
laboratory prototype developed for the purpose. The prototype
is designed for an output power rating of 6.6 kW. The components selected for laboratory prototype are provided in Table I.
The prototype is designed for an input voltage rating of 650 V
having an output voltage control range between 90 to 110 V.
The output current rating is 60 A. The switching frequency of
the semiconductor devices is maintained at 110 kHz.
Figs. 14 and 15 show the gate to source voltage and drain
to source voltage of switch S1, while turning on and off, respectively. Once the voltage across switch has almost reached
zero, gate to source voltage is applied, showing the ZVS turn
on action for S1. During turning off transient, it can be seen
from Fig. 15 that the drain to source voltage of the switch starts
rising only after gate to source voltage of the switch has assumed zero value. Hence it can be inferred that S1 turns off in
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 3, MAY 2008
(a)
(a)
(b)
(b)
Fig. 12. (a) Drain to source voltage and drain current for Switch S2. TR1:
voltage across switch S2 (100 V/div.), TR2: Current through switch S2
(10 A/div.). (b) Drain to source voltage and drain current for Switch S2 while
turning on. TR1: voltage across switch S2 (100 V/div.), TR2: Current through
switch S2 (10 A/div.).
ZVS mode. Figs. 16 and 17 show the drain to source voltage
and drain current through switch S2 while turning on and off,
respectively. Hence it can be inferred that S2 operates in ZCS
mode during transition from off state to the on state and vice
versa. Fig. 18 shows oscillogram records of one of the trans55 A
former primary voltages and its winding current, at
95 V, while Fig. 19 shows the same set of waveand
10 A and
95. It can be verified from
forms for
the aforementioned waveforms that the idling and/or circulating
currents of devices and the transformer windings are considerably low both for full load and light load conditions. The closed
loop frequency response of the system obtained experimentally
utilizing the laboratory prototype is depicted in Fig. 20. It can be
Fig. 13. (a) Drain to source voltage and drain current for Switch S1. TR1:
voltage across switch S1 (100 V/div.), TR2: Current through switch S1
(10 A/div.). (b) Drain to source voltage and drain current for Switch S2 while
turning on. TR1: voltage across switch S2 (100 V/div.), TR2: Current through
switch S2 (10 A/div.).
observed that this experimentally obtained frequency response
of the system matches closely with that obtained analytically
(Fig. 11) [12]–[14].
The power loss distribution in the laboratory prototype of
the converter estimated by following the procedure presented
in [15] while the converter is delivering 60A of load current at
95 V is shown in Fig. 21. The overall estimated efficiency of the
prototype is 92.03%. The measured efficiency of the converter
95 V and
as a function of the output current at
650 V, is shown in Fig. 22. The efficiency at full load condition
60 A and
95 V) is 91.5% and maximum effi(
ciency of 92.2% occurs when the converters delivers 45 A of
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GHODKE et al.: TPTL, SOFT SWITCHED, PHASE SHIFTED PWM DC–DC CONVERTER
1223
TABLE I
COMPONENTS USED IN THE LABORATORY PROTOTYPE
Fig. 14. Drain to source voltage and gate to source voltage for Switch S1, while
95 V, I
55 A.TR1: Gate to source voltage for
turning on, when V
switch S1 (10 V/div.), R2: voltage across switch S1 (100 V/div.).
=
=
load current. Photograph of the laboratory prototype of the proposed converter is shown in Fig. 23.
ZVS condition of outer devices is load current dependent, and
it is lost during light load condition. The ZVS soft switching behavior for the outer switches of the proposed converter is very
similar to that of full-bridge phase shift converter presented in
[16]. Therefore the same analysis presented in [16] can be extended for the proposed converter, and the minimum load current to achieve ZVS for the laboratory prototype of the converter
utilizing the aforementioned analysis is found to be 12.6 A. Similar to the full-bridge phase shifted converter presented in [16],
the converter proposed in this paper exploits the leakage inductance of the transformer to achieve ZVS for the outer switches.
Hence extension of the ZVS characteristic of the concerned converter switches over a wide range of load can be achieved by
Fig. 15. Drain to source voltage and gate to source voltage for Switch S1, while
95 V, I
55 A.TR1: Gate to source voltage
turning off, when V
for switch S1 (10 V/div.), TR2: voltage across switch S1 (100 V/div.).
=
=
connecting external inductances in conjunction with the transformers [4], [16], [17]. In order to achieve ZCS condition for the
concerned switches of the proposed converter, the following two
conditions have to be satisfied: first the reflected load current
should be higher than the magnetizing current of transformer
and secondly, the current flowing through the filter inductor
is
should be continuous. The peak magnetizing current
given by
(19)
Therefore, the peak magnetizing current for the prototype of the
proposed converter is around 0.886 A, In order to have the magnetizing current less than reflected current, the minimum load
current has to be more than 5.32A. The minimum load current
for achieving the condition of continuous current flow through
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 3, MAY 2008
Fig. 16. Drain to source voltage and drain current for Switch S2, while turning
95 V, I
55 A, TR1: Current through switch S2
on, when V
(4 A/div.), TR2: voltage across switch S2 (100 V/div.).
=
=
Fig. 17. Drain to source voltage and drain current for Switch S2, while turning
95 V, I
55 A, TR1: Current through switch S2
off, when V
(4 A/div), TR2: voltage across switch S2 (100 V/div.).
=
=
Fig. 18. Voltage across primary-A winding of transformer and it’s current for
95 V, I
55 A, TR1: voltage across one of the transformer priV
mary (100 V/div.), TR2: Current through same transformer primary (10 A/div.).
=
=
Fig. 19. Voltage across primary-A winding of transformer and it’s current for
95 V, I
10 A, TR1: voltage across one of the transformer priV
mary (100 V/div.), TR2: Current through same transformer primary (2 A/div.).
=
=
the output filter inductor can be shown to be (very similar to
basic buck regulator)
(20)
Therefore, the minimum load current required to make the filter
inductor current continuous conduction mode is 1.578 A. Hence
if load current is more than 5.32 A, ZCS condition of the concerned switches of the laboratory prototype of the proposed converter will be satisfied. The ZCS range can be increased by increasing the magnetizing inductance of the transformer.
Fig. 20. Experimentally obtained open loop frequency response of TPTL.
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GHODKE et al.: TPTL, SOFT SWITCHED, PHASE SHIFTED PWM DC–DC CONVERTER
1225
by slightly modifying the output rectifier configuration. Several such possible configurations are depicted in Fig. 24. The
converter configurations shown in Fig. 24(a) and (b) are having
almost the same output voltage and current ratings as that of
the proposed basic converter configuration. Fig. 24(a) is derived
from the classical current tripler configuration while Fig. 24(b)
is current hexa configuration formed with six-rectifier diode involving six-filter inductor. Here each diode and filter inductor
current will be one sixth of the load current. Therefore, this
configuration is suitable for applications where output current is
high. A conventional configuration to negotiate this type of load
would require paralleling of several diodes along with their balancing circuits which are very difficult to design. Configurations
depicted in Fig. 24(c) and (d) are having twice the output voltage
rating as that of the proposed basic converter configuration and
hence they are suitable for medium voltage and medium current
applications. Both configurations are of classical current tripler
type. Fig. 24(e) and (f) are conventional three-phase full wave
bridge rectifiers with single output filter inductors. The voltage
rating for these configurations is almost four times that of the
proposed basic configuration and hence they are suitable for
high voltage low current applications. In addition to these modifications, the primary connection of the star connected transformer can be changed to delta for increasing the output voltage
rating of the converter.
Output voltage for topology shown in Fig. 24(a) and (b) can
be derived on similar line given in Section II-C1
Fig. 21. Estimated loss distribution of TPTL dc to dc converter (in watts).
(21)
Fig. 22. Efficiency versys load current for the proposed converter (for V
650 V, V
95 V).
=
=
On similar line the output voltage for topology shown in
Fig. 24(c) and (d) can be derived to be
(22)
And the output voltage for topology shown in Fig. 24(e) and (f)
can be derived to be
(23)
B. Multiphase Configuration
The three-phase dc to dc converter topology with phase
shifted controller can be extended to multiphase topology as
shown in Fig. 25 by adding more number of inverter legs along
with it’s own phase shift controller maintaining proper phase
shifted clocked signal. In this case, the frequency of the input
current pulsations would be n times and the frequency of the
than
output voltage seen by the output filter capacitor is 2
that of a single phase topology [3]–[5], [19], [20].
Fig. 23. Prototype of a 6.6 kW three-phase three-level dc to dc converter.
V. CONCLUSION
IV. EXTENSION OF TPTL CONVERTER CONFIGURATIONS
A. Secondary Rectifier Configurations for Different Voltages
The aforementioned TPTL topology discussed so far is suitable for low voltage and high current applications. Loads requiring higher voltage for the same output power can be handled
A new soft-switched, TPTL dc to dc converter with phaseshift PWM converter is proposed. It has been shown that this
topology is particularly suitable for high output as well as high
input voltages. The proposed converter is having the following
performance features: 1) low switching losses over a wide range
of load, 2) low idling and circulating currents, resulting in low
conduction losses in switching devices and low copper losses
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1226
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 3, MAY 2008
Fig. 24. TPTL secondary rectifier configurations for different output voltages (same transformer can be used, as volt-second product of primary winding of transformer remains same).
on a 6.6 kW laboratory prototype developed for the purpose. It
has been shown that the proposed TPTL converter topology can
be extended to several multiphase configurations. Additional
suggestions are also provided to employ different output rectifier configurations for effectively generating various levels of
output voltages.
ACKNOWLEDGMENT
The authors would like to thank M. O. Ittoop, A. Sharma, K.
M. Krishnan, and B. K. Arya, for their help.
REFERENCES
Fig. 25. TPTL extension to multiphase configuration for dc to dc converter.
in the transformers, 3) additional passive or active auxiliary circuits are not required to realize ZVS or ZCS, 4) reduced duty
cycle loss is achieved thereby increasing the effective control
range, and 5) presence of the center tapped full wave rectifier
at the three phase transformer secondary side and -connection
on primary side, halves the output voltage, without increasing
the turns ratio of transformer. As a result of the aforementioned
merits, the proposed dc to dc converter can accept high input
voltage while negotiating loads requiring low output voltage and
high currents. Detailed steady state analysis of the converter is
presented. Effectiveness of the proposed converter is confirmed
through detailed simulation studies. Viability of the proposed
scheme is verified by performing detailed experimental studies
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Kishore Chatterjee was born in Calcutta, India,
in 1967. He received the B.E. degree in power
electronics from the Maulana Azad College of
Technology, Bhopal, India, in 1990, the M.E. degree
in power electronics from Bengal Engineering
College, Howrah, India, in 1992, and the Ph.D.
degree in power electronics from the Indian Institute
of Technology, Kanpur, in 1998.
From 1997 to 1998, he was a Senior Research Associate at the Indian Institute of Technology, Kanpur,
where he was involved with a project on power factor
correction and active power filtering, which was being sponsored by the Central Board of Irrigation and Power, India. He was an Assistant Professor in the
Department of Electrical Engineering, Indian Institute of Technology, Bombay,
since 1998 and has been as Associate Professor there since 2005. His current
research interests are modern var compensators, active power filters, utilityfriendly converter topologies, and induction motor drives.
B. G. Fernandes received the B.Tech. degree from
Mysore University, Mysore, India, in 1984, the
M.Tech. degree from the Indian Institute of Technology, Kharagpur, in 1989, and the Ph.D. degree
from the Indian Institute of Technology, Bombay, in
1993.
He then joined the Department of Electrical Engineering, Indian Institute of Technology, Kanpur, as an
Assistant Professor. In 1997, he joined Department
of Electrical Engineering, Indian Institute of Technology, Bombay, where he is currently Professor. His
current research interests are in permanent magnet machines, high-performance
ac drives, quasi-resonant link converter topologies, and power electronic interfaces for nonconventional energy sources.
Dharmraj V. Ghodke (M’07) was born in Solapur,
Maharashatra, India, on October, 20, 1968. He received the B.E. degree in electrical engineering from
W.C.E Sangali, Shivaji University Kolhapur, India,
in 1991, and is currently pursuing the Ph.D. degree
in power electronics at the Indian Institute of Technology Bombay, Mumbai, India.
After graduation he joined 35th Batch Training
School, Department of Atomic Energy, Bhabha
Atomic Research Center, Mumbai. After training in
1992, he joined the Center for Advanced Technology
(CAT), Indore, India, as Scientific Officer. Here, he demonstrated the first
indigenous solid state pulsed modulator for copper vapor laser, a replacement
of thyratron based modulator. He also designed and developed various low
voltage and high voltage isolated switch mode power supply, capacitor charging
power supply, trigger and driver units, power ranging from 1 W to 11 kW
for lasers and control applications a replacement of linear power supply. His
specialty areas includes high frequency, high power switch mode and solid state
pulse power supply, auxiliary controllers and circuits for laser applications. His
current research interest includes simulation and digital controller of PWM
active UPF rectifiers, active filters, and ac to dc and dc to dc converters, for
high power applications.
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