International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print),
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ISSN 0976 – 6553(Online) Volume 4, Issue 5, September – October (2013), © IAEME
TECHNOLOGY (IJEET)
ISSN 0976 – 6545(Print)
ISSN 0976 – 6553(Online)
Volume 4, Issue 5, September – October (2013), pp. 56-77
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IJEET
©IAEME
PLL FOR SINGLE PHASE GRID CONNECTED INVERTERS
Mihail Antchev1, Ivailo Pandiev2, Mariya Petkova3, Eltimir Stoimenov4, Angelina Tomova5,
Hristo Antchev6
1, 3, 5
2, 4
(Power Electronics Dept., Technical University- Sofia, Bulgaria)
(Electronic Engineering Dept., Technical University- Sofia, Bulgaria)
6
(R&D Sector, Technical University- Sofia, Bulgaria)
ABSTRACT
In grid connected applications the synchronization of output signals of the converters to be
connected with grid parameters - frequency and phase is of great importance. Different methods
based on Fourier transforms, zero-crossing detection, Kalman filters, phase-locked loops (PLL) and
others are used for this synchronization. This paper presents a new PLL for synchronization of the
output current of single-phase grid connected inverters with the utility grid voltage. It is based on
trigonometric transformations - sine and cosine functions in a phase detector block. The proposed
method’s simplicity and efficiency are proved by means of computer simulations and experimental
analysis. The practical realization of the PLL is based on analog and digital programmable devices.
Simulation and experimental results show good agreement with the results obtained by the
theoretical analysis. Advantage of the proposed PLL is its insensibility to changes of the amplitude
of the input signal after the synchronization has been achieved with its frequency and phase. Also, in
the proposed PLL, the settling time both at a step change of frequency and phase is decreased.
Keywords- DDS, FPAA, single-phase inverter, phase detector, phase locked-loop, utility grid, VCO
1. INTRODUCTION
In recent years, energy demand increases due to change of a lifestyle using more and more
electronic devices. Contrary to the increased demand, conventional fossil fuels constantly decrease
and in order to reply to the needs, researchers and industry made the utilization of renewable energy
sources very widely spread. Even though renewable energy sources and distributed generation have
been now used for more than twenty years, some major points still need to be improved in order to
enhance distribution and quality of energy in the utility grid at levels required by different standards
and most important, to reply to consumers’ requirements. In that meaning one of the major problem
is the synchronization of the current at the output of an inverter with the voltage of the utility grid
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ISSN 0976 – 6553(Online) Volume 4, Issue 5, September – October (2013), © IAEME
[1].Traditional synchronization methods of the control system and the grid voltage involve widely
used algorithms based on the phase-locked loops (PLL). A PLL is a device providing tracking of one
signal by another one and as a result of this tracking the output signal is synchronized with the input
reference signal in phase and frequency. Various PLL techniques have been proposed and are used
because of the efficiency and robustness for single-phase systems, for three-phase systems as well as
in aircraft electrical systems [2] in case there is a need to track currents and voltages. The technique
of tracing has been used, researched and improved for a long time. Reference [3] contains an
overview of the historical development of the phased-locked loops, general information about their
operation as well as a more detailed review of the three major blocks building the general blockdiagram of a single-phase PLL, presented in Fig.1. It resumes very well the structure of almost every
PLL algorithm that can be found nowadays in the literature. The classic PLL consists of three
general blocks – a phase detector (PD), a loop filter (LF) and a voltage-controlled oscillator (VCO).
Fig.1 Block diagram of a single-phase PLL
Classification and explanation of the basic operation of the most commonly used types of
control and synchronization are presented in [4]. Increasingly in the literature one can find separate
approaches in the implementation of the PLL in three-phase and single-phase applications. In grid
connected three-phase applications the synchronous-reference frame is very commonly used [5], [6].
The main idea of the synchronous-reference frame PLL is the transformation of the input signals in
dq-frame by means of the well-known Park and Clark transformations. A design of such a PLL is
proposed in [5]. In case of operation of the grid-inverter in polluted utility grid to improve the quality
of the energy an adaptive synchronous reference frame PLL is presented in [7]. Specificity of this
PLL consists of rejection of disturbances even in case of variable fundamental frequency which is
obtained by the use of several in number and type filters - such as notch filters and others. In the
literature, there are also some three phase PLLs which fulfill the standard pq- theory and with simple
addition of feed forward action a higher performance is easily reached at the start-up stage [8]. There
are also single-phase phase-locked loops based on modified pq theory [9].
A new approach for three-phase systems is presented in [9] and [10]. It is based on a
preliminary estimation of the main parameters of the input signal - frequency, phase, magnitude, etc.
It uses three different enhanced PLLs for each of the three phases of the input signals which are in
the abc-frame. One of the major advantages of this method is its simplicity and introduction of
parameter independency which can be applied to the other PLL methods, too. A similar approach for
single-phase applications is presented in [11]. Other PLLs for frequency variable signals are
proposed in [12], [13].
In order to decrease phase error problems in some PLLs for grid applications, methods with
Selective Harmonics Elimination (SHE) operating in single and three-phase systems have been
developed [14]. A harmonics approach is also used in the digital phase-locked loop (DPPL) [15]. It
consists of even harmonics elimination and thus the grid fundamental harmonic is extracted which is
used as unity reference signal.
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As it happens that the utility grid operates under distorted conditions and its voltage is not
always balanced, some PLL techniques for this kind of operation have been also researched [8], [12],
[16], [17], [18], [19], [20]. The common for the first four quoted methods is that all of them use
estimation of positive and negative sequences of the input signal at an uncertain frequency value.
Such a method is used also in the fixed reference frame phase-locked loop (FRF-PLL) [21], [9] but
the sequences are in stationary coordinates. There is also a research proving by mathematical
analysis that the SOGI-PLL [16], [22] and the Park-PLL are equivalent in terms of control [23]. In
the fifth article not only the same sequences are estimated but also harmonic components are found
in order to use a selective approach for a selective compensation. Another topology of PLL based on
the FPGA implementation [24], can also separate the components and detect harmonic components
in three-phase signals. The last one uses lead compensators cascaded with the PI controller in order
to reject some harmonics of the synchronous-reference-frame without reducing the bandwidth of the
PLL.
A novel hardware-based all-digital PLL presented in [25] has a zero-crossing detection
function of the PD block. Philosophy of its operation is similar to the one of [8] in terms of the added
feed forward loop due to which the frequency can vary and the PLL performance in terms of speed
increase. This PLL is very suitable for use in synchronized PWM applications.
In [25] a PLL is described with a phase-detector which rejects a ripple noise of the second
order harmonics, without using any classical loop-filters, which can decrease the PLL performance
in terms of response to dynamic changes as well as it can decrease of about 50% of the settling time
of the PLL. The method is called modified mixed PD (MMPD) and it uses a filter with frequency
feedback (FFB) term.
Reference [27] presents a modified power based PLL for single-phase systems, which is
based on a so called double-frequency and amplitude compensation (DFAC) method in order to
overcome some of the disadvantages of the standard PLL such as sensitivity to grid frequency
variation, double-frequency, etc.
In [28] three PLL algorithms are presented, namely, pPLL, parkPLL and EPLL. Experimental
study and comparison among the indicators of the transient process at a step change of the frequency,
phase and amplitude of the input signal are made. The smallest time of the transient process is 2.5
periods of the input signal.
In [29] an open-looped structure is described that processes the input signals and as results
the frequency and amplitude of its first-order harmonic and the higher-order harmonics are obtained.
The scheme is characterized by an increased number of processing blocks – 4 multipliers and 3
integrators. The quality of the transient response is characterized by two additional parameters when
compared to conventional methods. The way to define these two parameters is not clarified.
In [30] a new detection method to find the phase and amplitude of the first-order and higherorder harmonics is described. The method is based on ant conjugate harmonic decomposition and
cascaded delayed signal cancelation. The system has a completely open-looped structure and
requires an additional generation of a sine wave for an on-grid inverter.
A single-phase PLL proposed in [31] uses a phase detector multiplier and a phase shifter to
obtain cosine from a sine function. Thus the PLL contains a low pass filter that decreases its
response. The same filter is in the structure of the described PLL in [32], where the output signal is
generated from a post-processor.
The aim of this paper is to propose a new simplified realization of a PLL for single-phase ongrid inverters based on trigonometric equations. The authors also studied the dynamic and steadystate characteristics of the proposed PLL. Different disturbances of the quality of the grid voltage are
possible at operation of power electronic converters connected to the distribution network. More
often the disturbances are short durational changes of the instantaneous and effective values of
voltage either increasing or decreasing these values. Therefore, a major advantage of the proposed
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PLL is its insensibility to changes in values of the input signal after the synchronization has been
achieved.
The most similar structure to the one presented in this paper is illustrated in [33]. However, in
[33] two input signals, obtained from Hall sensors, displaced in 90° are used. Because the third
harmonic has to be decreased in the particular application, an adaptive notch filter (ANF) forming
the settling time of the phase angles equal to several seconds is used.
Different PLL methods for renewable energy system applications are presented in [34], [35],
[36], [37], [38].
This paper is organized as follows. The proposed algorithm is described in the Section 2. The
Section 3 presents results of the computer simulation of the PLL. In the Section 4, the practical
realization of the model, as well as the features of some of the used elements, are described. In the
Section 5, results of the experimental research of the system which are in compliance with the same
cases studied during the computer simulation of the model are presented. Finally, the Section 6
concludes the paper.
2. MATHEMATICAL DESCRIPTION
Fig.2 presents a block diagram of the phase-locked loop circuit.
PI controller
VCO
KP
K
I
ωF
+
p
(
U M sin ϑ − ϑˆ
∆ω
)
ϑˆ = ωˆ + ϕˆ
+ ω̂
1
sin ϑˆ
X
ϑˆ
p
sin
Output
1 . sin ϑˆ
∑
Input
U M sinϑ
cos ϑˆ
X
Phase
shift
− 90
cos
−U M cosϑ
o
Phase
Detector
Fig.2. Block diagram of the phase-locked loop circuit.
The operation is based on the following mathematical equations:
[ ( ) ( )]
[ ( ) ( )]
1
sin ϑ − ϑˆ + sin ϑ + ϑˆ
2
1
− U M cos ϑ . sin ϑˆ = −U M sin ϑˆ − ϑ + sin ϑ + ϑˆ
2
U M sin ϑ . cos ϑˆ = U M
(1)
(2)
After summing the equations (1) and (2), the basic trigonometric relationship used in the
proposed PLL is gained:
U M sin ϑ cos ϑˆ − U M cos ϑ sin ϑˆ = U M sin ϑ − ϑˆ
(3)
The operation is based on the idea that the signal described with the right side of the equation
(3) is used as an error signal in the closed-loop of the automatic control system. The PLL is such a
system. Controlled by this signal during transient operation modes (initial start, frequency variation,
phase variation) the PI controller constantly changes the input signal of the Voltage Controlled
Oscillator (VCO) until the difference in frequency and phase - ϑ = ϑˆ between the input and output
signals disappears. Afterwards, the input signal of the PI controller is equal to zero and the steady
(
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International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print),
ISSN 0976 – 6553(Online) Volume 4, Issue 5, September – October (2013), © IAEME
state is established. As a result after the transient processes have settled at initial start, variations of
the input voltage value do not affect the steady state of the output signal.
3. COMPUTER SIMULATION
Fig.3. Simulation model of the proposed PLL for single phase grid connected inverter
The simulation results are gained using PSIM software. The simulation model shown in Fig.3
consists of several blocks – PI, cos, sin, multiplication block, summer block, time delay, sine wave
voltage sources, bi-directional switches and their control. After the time delay, a cosine wave of the
input signal is obtained. The sign of the cosine wave is minus, that is why it is afterwards directly
The PI block
multiplied by cosine and sine of ϑ to satisfy the mathematical equation (3).
performs the operation of the PI regulator in the PLL. Using the two bi-directional switches shown in
the figure with normally closed or normally opened terminals, all required step changes are
simulated – in amplitude, in phase, in frequency of the input signal. The changes are simulated by
setting appropriate values of the voltage sources’ parameters.
The simulation results are presented in the following way: first, a diagram is plotted with a
narrow span on the X-axis for a clearer starting reaction of the output signal; second, a diagram is
plotted with a wider span on the X-axis corresponding to the transient process settlement until the
output signal synchronizes with the input signal. The results in the part IV “Practical Realization” are
presented in the same way. The simulation and experimental results show that after this settling time,
a steady state of the system is set. The steady state is described by the diagrams in the simulation and
experimental parts.
3.1.
Steady state operation
Fig.4 shows the operation of the PLL in a steady state. The output signal (the synchronized
signal) has the amplitude of unity, regardless of the amplitude of the input signal.
Fig.4. Simulation results for the operation of the PLL in a steady state – the input voltage and the
synchronized voltage. The time span is (400ms,480ms)
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3.2.
Initial start
(a)
(b)
Fig.5. Simulation results for the operation of the PLL with the input signal displaced 180 degrees – the
input voltage and the synchronized voltage: (a) time span is (0,40ms), (b) time span is (0.10,0.225s)
Fig.5 and Fig.6 display the simulation results for the operation of the PLL. In Fig.5(a) one
can observe the input signal and a signal displaced 180 degrees related to the input signal. The time
span is (0,40ms). In Fig.5(b) the same signals for the time span of (0.10,0.225s) can be observed. In
Fig.6(a) and Fig.6(b) the input signal and signal with a random phase difference can be observed.
(a)
(b)
Fig.6. Simulation results for the operation of the PLL with the input signal with the random phase – the
input voltage and the synchronized voltage: (a) time span is (0,40ms), (b) time span is (120ms,160ms)
From both simulations, it is obvious that the time necessary for the synchronization of the
signal depends on its phase. The signal displaced 180 degrees related to the input signal is getting
synchronized for about 150ms, and the signal with the random phase is synchronized for about
125ms, or significantly quicker.
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3.3.
Step variation of the amplitude
(a)
(b)
Fig.7 Simulation results for the operation of the PLL with the input signal with step-down variation of the
amplitude – the input voltage and synchronized voltage: (a) time span is (780 ms,840ms), (b) time span is
(0.76,0.86s)
Fig.7 and Fig.8 display simulation results for the operation of the PLL with step variation of
the amplitude of the input voltage. In Fig.7(a) one can observe the input signal with step-down
variation of the amplitude and a signal to be synchronized. Time span is (790 ms, 840ms). In
Fig.7(b) the same signals but for different time spans can be observed. In Fig.8(a) and Fig.8(b) the
input signal with step-up variation of the amplitude and a signal to be synchronized can be observed.
From these 4 simulation results we can conclude that the step variation of the amplitude
whether it is a step-up or a step-down variation does not influence the synchronization of the signals
and the operation of the PLL.
(a)
(b)
Fig.8 Simulation results for the operation of the PLL with the input signal with step-up variation of the
amplitude – the input voltage and synchronized voltage: (a) time span is (780 ms,830ms), (b) time span is
(0.76,0.86s).
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3.4.
Step variation of the phase
(a)
(b)
Fig.9 Simulation results for the operation of the PLL with the input signal with step leading variation of the
phase – the input voltage and synchronized voltage: (a) time span is (390 ms,420ms), (b) time span is
(0.375,0.475s).
Fig.9 andFig.10 display the simulation results for the operation of the PLL with step variation
of the phase of the input voltage. In Fig.9(a) an input signal with step leading variation of the phase
and a signal to be synchronized for the time span (397.5ms, 420ms) can be observed. In Fig.9(b) the
same signals for different time span can be observed. In Fig.10(a) and Fig.10(b) the input signal and
a signal with leading phase to the input signal phase with step lagging variation of the phase and the
signal to be synchronized can be observed.
(a)
(b)
Fig.10 Simulation results for the operation of the PLL with the input signal with step lagging variation of the
phase – the input voltage and synchronized voltage: (a) time span is (390 ms,420ms), (b) time span is
(0.375,0.475s).
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3.5.
Step variation of the frequency
In Fig.11 the input signal with step-up variation of the frequency from 50Hz to 50.5Hz and a
signal to be synchronized can be observed.
(a)
(b)
Fig.11 Simulation results for the operation of the PLL with the input signal with step-up variation of
the frequency from 50Hz to 50.5Hz – the input voltage and synchronized voltage: (a) time span is
(360ms,420ms), (b) time span is (0.38,0.54s).
4. PRACTICAL REALIZATION
4.1.
Structure of the PLL circuit
In Fig.12 a block diagram for realization of the phase-locked loop (PLL) is presented. Circuit
is based on digital and analog programmable devices. Main elements of the diagram are VCO, phase
detector (PD) and PI-controller. Operation of the VCO is based on the direct digital synthesis (DDS)
methodology [39] which consists of reading from two look-up tables (LUT) up to 256 referent values
describing a quarter of the period (from 0 to π / 4 ), respectively of sine and cosine waves. Number of
the read values depends on the factor of the phase accumulator. The value of the factor is formed by
the magnitude of the input control voltage V (∆ω) . For that purpose the control voltage is transformed
in a digital value by a 10-bit analog-to-digital converter (ADC). In order to increase accuracy of the
measurement the average value of 64 measured results is taken. Input voltage range of the ADC is
from 0 to +3,3V. The conversion of the digital values for the sine and cosine waves in analog form is
done by 12-bit digital-to-analog converter (DAC). Reference voltage of the DAC, formed by an
internal voltage source, is equal to 2,5V. For the realization of the VCO the following integrated
circuits (ICs) are used: 1) microcontroller MSP430G2553TI Inc. (with the following basic
parameters: 16-bit RISC architecture, 16 MHz clock signal frequency of the central processor unit
(CPU), internal clock signal generator typical tolerance ±3%, 10-bit/ 8-channels ADC with internal
clock generator); and 2) DAC DAC7565TI Inc. (with the following basic parameters: 12-bit/4channels, relative accuracy: 0,5LSB, internal reference source with output voltage 2,5 V, serial SPI
communication interface).
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International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print),
ISSN 0976 – 6553(Online) Volume 4, Issue 5, September – October (2013), © IAEME
The microcontroller block executes a DDS algorithm and by its SPI peripheral module sends
the information to the DAC for conversion. In Fig.15 is presented the VCO program algorithm. The
algorithm can be separated in two basic parts- main loop and interrupt service routines (ISR). In the
main loop values of successive points of the output sine and cosine waves are calculated, then the
values are sent through the SPI to the DAC for conversion. The ISR is requested by the ADC module
approximately every 500µs. On every request, an average value of 64 measures is calculated and the
result is loaded in the DDS phase accumulator.
Phase detector (PD) and PI-controller are realized by two FPAAs (Field Programmable
Analog Arrays). Structure of the PD and the PI-controller match up with an equivalent circuit of the
block diagram presented in Fig.2. A description of the used configurable analog modules (CAM) and
their main parameters and clock frequencies can be found in Table I. As the FPAA are still not so
popular in the electronics field, it worth to present them briefly. In general FPAA is analog
equivalent of the widely known field programmable gate arrays (FPGA). FPAA are based on
switched-capacitors (SCs) technology. By specialized EDA software, the FPAA can be programmed
with an arbitrary analog transfer function. It is important to point out that all input and output signals
as well as the internal ones for FPAA are differential ones. All voltages are referred to a voltage
(Voltage Mid-Rail − VMR) equal to the half of the power supply voltage. The use of differential
inputs and outputs improves the noise immunity of the realized devices.
Major advantages of the use of FPAA are lower design time, no variation of the parameters
due to component aging, a few used elements and the possibility for programmable set up of the
CAMs functional parameters. Basic disadvantage of the FPAA in comparison with ASIC is increased
consumption [40], [41] which is important only for the battery powered devices. For the
implementation of the system is used FPAA AN231E04Anadigm Inc. FPAA AN231E04 has the
following basic electrical parameters: input offset voltage less than 250µV, input voltage range: 0 –
3V; bandwidth – DC – 2MHz (depends on the used CAM); SNR – 90dB; THD – 100dB; power
supply voltage +3,3V.
The PD is realized in FPAA1 and is built by means of two analog multipliers, one secondorder low-pass filter (used for implementation of the time delay block) and one two-input noninverting summing block. In addition some auxiliary blocks as sample and hold and bilinear lowpass filter (LPF) are used. The second-order low-pass filter is SC- circuit with differential
input/output for which the first pole frequency is equal to 5Hz and the second pole frequency is
500 Hz . These two values are equally spaced from the working frequency equal to 50Hz , which
allows to assume that the phase shift around frequency 50Hz is approximately 90 degrees. The
second-order low-pass filters that implement the time delay is a cascade structure of two bilinear
(first-order) low-pass filters. The first bilinear filter, that realizes the pole frequency is equal to 5Hz ,
is with external capacitors. The external filtering capacitors, connected between nodes n12 and n13
according to the pole frequencies are chosen with values equal to 1,65nF . The second bilinear filter is
with pole frequency is equal to 500 Hz . The transfer function for the second-order low-pass filter
CAM is
TLP ( s) = −
1
( s + 2πf p1)( s + 2πf p 2 )
(4)
Where f p1 and f p 2 are values of the first and second pole frequencies, respectively.
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Based on equation (4) for the phase shift is found
 f 


 − arctan f 
 f p1 
 f p2 




ϕ = 180° − arctan
Phase detector
(5)
PI Controller
10kΩ
ˆ)
UМ.sin(ϑ−ϑ
10kΩ
VMR
−UМ.cos(
ϑ)
7,8nF
7,8nF
UМ.sin(ϑ)
VMR
10kΩ
Input
signal
2 X 10kΩ
VMR
VMR
1.65nF
1.65nF
DDS-based VCO
DAC7565
ˆ)
cos(ϑ
12 -Bit DAC 1
Vref
2.5V
ˆ)
sin(
ϑ
12 -Bit DAC 2
Vref
2.5V
Microcontroller
MSP430G2553
Vcc
SPI
DDS
+vref
10-Bit ADC
-vref
V(∆ω)
Vss
Output signal
Fig.12. Structure scheme of the practical realization of the PLL
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By varying the value of the input signal frequency f , the phase delay can be adjusted to
values from 180° to 0. For the frequencies between f p1 and f p 2 the phase shift is approximately
equal to 90 degrees. Our experiment shows a phase deviation smaller than ±0.1% if the input signal
frequency is varying between 49.8Hz to 50.2Hz.
The input signals of the PD are singled-ended and they are applied to the non-inverting inputs
only (pins 01 and 09 of the FPAA). On the other hand the inverting inputs are connected to the signal
ground (VMR) through 10 kΩ resistors. The output signal
U M . sin( ϑ − ϑˆ ) Of the PD is applied differentially to the inputs of the PI-controller (pins 01 and 02 of
FPAA2).
The PI-controller realized in FPAA2, is composed of two summing blocks and one LPF with
external capacitors. In the circuit the LPF operates as an integrator with f c << f (where f c is the cut
off frequency of the LPF). This way the realization of the transfer function is simplified as the LPF
with external capacitors allows the usage of relatively low cut off frequency (<1Hz) and respectively
large time constant. The reference voltage of the regulator is set to signal ground (VMR=1,5V).
4.2.
Operation
The circuit operation (Fig.12) can be described as follows. In quiescent mode (without input
signal) the VCO produces two periodical signals with sine and cosine waveforms. Amplitude of the
signals is equal to1,25V and frequency is strictly 50Hz. When a sine wave input signal U M . sin(ϑ )
with frequency between 49Hz and 51Hz is applied, the PD compares the phase angle between the
signal and the output signal of the VCO - U M . sin(ϑˆ) . Then the PD generates voltage, proportional to
the phase difference of the two signals.
The output voltage of the PD is applied to the PI-controller as high order harmonics are
rejected. The output voltage V (∆ω) of the PI-controller (in pin 19) is applied asymmetrically as
control voltage to the VCO. The V ( ∆ω) changes the frequency of the VCO according to the following
expression:
(6),
f out = f 0 + K f ⋅V ( ∆ ω )
Where f 0 = 50 Hz is the center frequency of the VCO when there is no input signal, and K f = 3,33 Hz / V
is the VCO gain (sensitivity).
The phase difference between the output signal of the VCO and the input signal is varying
and when it reaches a constant value there is synchronization in the PLL circuit. In the
synchronization mode of operation the two frequencies - f out and fin become equal. If the frequency
variation of the input signal is within the lock frequency range of the PLL the synchronization will
remain.
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Table 1. FPAA CAMs for PLL circuit
FPAA1 – Phase Detector
Name
Symbol
Multiplier1
Options
Parameters
Clocks
Sample and hold: off
Multiplication factor: 1,00
Clock A: 83.3333kHz
(Clock 0)
Clock B: 1333.33kHz
(Clock 1)
Multiplier2
Sample and hold: off
Multiplication factor: 1,00
Clock A: 83.3333kHz
(Clock 0)
Clock B: 1333.33kHz
(Clock 1)
Hold 1
Input sampling phase: phase1
none
Clock A: 83.3333kHz
(Clock 0)
Hold 2
Input sampling phase: phase1
none
Clock A: 83.3333kHz
(Clock 0)
FilterLowFreqBili
near1
Independent variable: Corner
frequency
Polarity: Inverting
Input sampling phase: Phase1
Corner frequency [kHz]:
0.005
Gain: 1.00
External cap value [nF]: 1.65
Clock A: 83.3333kHz
(Clock 0)
Filter type: Low Pass
Input sampling phase: Phase1 Corner frequency [kHz]: 0.5
Polarity: Non-inverting
Gain: 1.00
Resource usage: Min. resources
Clock A: 83.3333kHz
(Clock 0)
FilterBilinear1
Output Changes On: Phase 2
Input 1: Non-inverting
Input 2: Non-inverting
Input 3: Off
Corner frequency [kHz]: 1
Gain 1 (UpperInput): 1
Gain 2 (LowerInput): 1
Clock A: 83.3333kHz
(Clock 0)
Options
Parameters
Clocks
SumDiff2
Output Phase: Phase 1
Input 1: Inverting
Input 2: Non-inverting
Input 3: Off
Input 4: Off
Gain 1 (UpperInput): 1
Gain 2 (LowerInput): 1
Clock A: 250kHz
(Clock 3)
SumDiff1
Output Phase: Phase 1
Input 1: Inverting
Input 2: Inverting
Input 3: Off
Input 4: Off
Gain 1 (UpperInput): 1
Gain 2 (LowerInput): 1
Clock A: 250kHz
(Clock 3)
FilterLowFreqBili
near1
Independent variable: Corner
frequency
Polarity: Non-inverting
Input sampling phase: Phase1
Corner frequency [kHz]:
0.00318
Gain: 10
External cap value [nF]: 7.81
Clock A: 250kHz
(Clock 3)
FilterBilinear1
Filter type: Low Pass
Input sampling phase: Phase1
Polarity: Non-inverting
Resource usage: Min. resources
Corner frequency [kHz]: 1
Gain: 1,00
Clock A: 250kHz
(Clock 3)
SumFilter1
FPAA2 – PI regulator
Name
Symbol
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International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print),
ISSN 0976 – 6553(Online) Volume 4, Issue 5, September – October (2013), © IAEME
Fig.13
3. VCO operation block algorithm
5. EXPERIMENTAL RESULTS
In order to verify the simulation results and prove the effective operation of the proposed
PLL algorithm an experimental platform was built
built-in.
in. A photograph of this platform is presented in
Fig.14.
Fig.14. Photograph
Photogra of the experimental platform
5.1.
Steady state operation
Fig.15. Experimental results after initial start of the PLL in steady state operation: Ch1 denotes the
input signal, Ch2 denotes the output signal. The time span is (-25ms,25ms)
25ms,25ms)
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International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print),
ISSN 0976 – 6553(Online) Volume 4, Issue 5, September – October (2013), © IAEME
In Fig.15 experimental results for the operation of the PLL in steady state are shown. Ch1
denotes the input signal as Ch.2 the output synchronized signal. A complete coincidence of the
frequency and the phase of both signals can be observed on this steady state experimental result after
the initial start of the system.
5.2.
Initial start
Fig.16 and Fig.17 display the experimental results for the operation of the PLL. In Fig.16(a)
and Fig. 16(b) one can observe the input signal displaced to 180 degrees and the output signal for
two different time spans. In Fig.17(a) and Fig.17(b) an input signal with random phase difference
and the output signal for two different time spans can be observed.
(a)
(b)
Fig.16 Experimental results for initial start of the PLL with the input signal displaced of 180 degrees: Ch1
denotes the input signal, Ch2 denotes the output signal: (a) time span is (-50ms,50ms), (b) time span is
(136ms,236ms).
These experimental results confirm the results for the same type of signals analyzed via
computer simulation in the Section III of the paper. The signal displaced 180 degrees related to the
input signal is getting synchronized for about 216ms, and the signal with random phase is
synchronized for about 30ms, or significantly quicker.
(a)
(b)
Fig.17 Experimental results for initial start of the PLL with the input signal with random phase: Ch1
denotes the input signal, Ch2 denotes the output signal: (a) time span is (-50ms,50ms), (b) time span is
(66.4ms, 166.4ms)
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International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print),
ISSN 0976 – 6553(Online) Volume 4, Issue 5, September – October (2013), © IAEME
5.3.
Step variation of the amplitude
Fig.18 and Fig.19 display the experimental results for the operation of the PLL with step
variation of the amplitude of the input voltage. In Fig.18(a) and Fig.18(b) one can observed the input
signal with step-down variation of the amplitude and a signal to be synchronized. In Fig.19(a) and
Fig.19(b) the input signal with step-up variation of the amplitude and a signal to be synchronized can
be observed. In both figures there is one more signal which indicates the beginning of the variation –
channel 3 CH3.
(a)
(b)
Fig.18 Experimental results for the operation of the PLL with the input signal with step-down
variation of the amplitude: Ch1 denotes the input signal, Ch2 denotes the output signal, and Ch3
denotes the beginning of the variation: (a) time span is (-25ms,25ms), (b) time span is
(-50ms,50ms)
In this case there is also confirmation of the mathematical description given in the Section 2
and simulation results of the Section 3 - the variation of the amplitude does not affect the
synchronization process. An explanation is derived from Fig.2 and equation (3) – after the catching
up of the frequency and phase - sin ϑ − ϑˆ = 0 and the input signal of the PI controller is also equal to
0, regardless of the change of U M . Therefore, the output signal will not change. The maximum value
of the input signal U M affects the process of the initial start and takes effect at a step-change of the
frequency and phase. At a higher value of the input signal, a higher value as input signal of the PI
controller is obtained. As a result, the duration of the transient process decreases. For that reason, it
is recommended the operation of the PLL to be set with the highest possible value of the input signal,
suitable to the used electronic components.
(
)
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International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print),
ISSN 0976 – 6553(Online) Volume 4, Issue 5, September – October (2013), © IAEME
(a)
(b)
Fig.19 Experimental results for the operation of the PLL with the input signal with step-up
variation of the amplitude: Ch1 denotes the input signal, Ch2 denotes the output signal, and Ch3
denotes the beginning of the variation: (a) time span is (-25ms,25ms), (b) time span is
(-50ms,50ms)
5.4.
Step variation of the phase
Fig.20 and Fig.21 display the experimental results for the operation of the PLL with step
variation of the phase of the input voltage. In Fig.20(a) and Fig.20(b) the input signal with step
lagging phase, the signal to be synchronized and the signal indicating the begging of the change can
be observed. In Fig.21(a) and Fig.21(b) one can observe the input signal with step leading phase, the
signal to be synchronized and the signal indicating the begging of the change.
(a)
(b)
Fig.20 Experimental results for the operation of the PLL with the input signal with step-down
leading variation of the phase: Ch1 denotes the input signal, Ch2 denotes the output signal, and Ch3
denotes the beginning of the variation: (a) time span is (-25ms,25ms), (b) time span is
(-50ms,50ms).
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International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print),
ISSN 0976 – 6553(Online) Volume 4, Issue 5, September – October (2013), © IAEME
(a)
(b)
Fig.21 Experimental results for the operation of the PLL with the input signal with step-up lagging
variation of the phase: Ch1 denotes the input signal, Ch2 denotes the output signal, and Ch3
denotes the beginning of the variation: (a) time span is (-25ms,25ms), (b) time span is
(-50ms,50ms)
As it is in the simulation results, it is obvious that the variation of the phase of the input
signal affects the synchronization process- when it is step leading the synchronization process is
quicker -it is done in 40ms, than if the variation is step-lagging- the synchronization is done for more
than 40ms.
5.5.
Step variation of the frequency
In Fig.22 one can observe the input signal with step-up variation of the frequency from 49Hz
to 52Hz and a signal to be synchronized as well as a third signal marking the beginning of the
variation. In this case a synchronization of the output signal after the change of the frequency is done
for about 20ms.
(a)
(b)
Fig.22 Experimental results for the operation of the PLL with the input signal with step variation of the phase
with the increase of the frequency from 49 to 52 Hz: Ch1 denotes the input signal, Ch2 denotes the output
signal, and Ch3 denotes the beginning of the variation: (a) time span is (-25ms,25ms), (b) time span is (50ms,50ms)
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International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print),
ISSN 0976 – 6553(Online) Volume 4, Issue 5, September – October (2013), © IAEME
Table 2 shows a summary regarding the settling time prepared based on the simulation and
experimental results.
Table 2. Settling time- Summary
Simulation
160ms
Init.start 180 o
o
120ms
Init start 45
Voltage step -30%
0
Voltage step +30%
0
40ms
Phase step + 45 o
50ms
Phase step − 45 o
Frequency step
70ms
50Hz-50.5Hz
Experiment
200ms
100ms
0
0
40ms
40ms
50ms
49Hz-52Hz
There is a good coincidence between the simulation and experimental results when the phase
of the input signal was changed. The difference in the results is higher at initial start and at a change
of the frequency.
The experimental results show settling time of 2 periods of the input signal at a step change
of the phase, which is less than the time shown in [28], and 2.5 periods of the input signal at a change
of the frequency. At a step-change of the effective value of the input signal, there is no change of the
output signal.
6.
CONCLUSION
A new PLL for single phase on-grid connected inverters, based on trigonometric
transformations, is presented in the paper. The major conclusions are done on the basis of a
mathematical analysis and computer simulation by means of the PSIM software. They have been
proved by a practical realization based on analog and digital programmable devices. The research
shows very good operation of the PLL at its initial start as well as in the steady state operation and in
case of variation of the magnitude, phase or frequency of the input voltage.
The main advantage of the proposed PLL is the lack of reaction of the output signal at a stepchange of the amplitude of the input signal. The lack of reaction is that practically there is no
deviation in the phase, frequency and amplitude of the output signal, and there is no time for settling.
It is worthy to be mentioned that the change of the amplitude value of the grid voltage is more often
met than the change of its frequency or phase. Another advantage is the decreased settling time at a
step-change of the phase, which does not exceed two periods of the input signal. An additional
advantage of this PLL is its simple scheme. It contains a standard blocks – PI controller, VCO. To
implement the phase detector two multipliers, a block to sum signals and a block to change the phase
are used.
The future work is focused on the application of this method for three-phase grid connected
inverters.
ACKNOWLEDGMENT
The authors thank the European Commission for the support of the DERRI (SP4 CapacitiesGA 228449) see also http://www.der-ri.net. The authors are solely responsible for the content of this
publication, it does not represent the opinion of the European Community and the European
Community is not responsible for any use that might be made of data appearing therein.
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International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print),
ISSN 0976 – 6553(Online) Volume 4, Issue 5, September – October (2013), © IAEME
REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
J. Rocabert, A. Luna, F. Blaabjerg and P. Rodriguez, Control of Power Converters in AC
Microgrids, IEEE Trans. Power. Electron. 27(11), 2012, 4734-4749.
F. Cupertino, E. Lavopa, P. Zanchetta, M. Sumner and L. Salvatore, Running DFT-based
PLL algorithm for frequency, phase, and amplitude tracking in aircraft electrical systems,
IEEE Trans. Ind. Electron., 58(3), 2011, 1027-1035.
G.-C. Hsieh and J. C. Hung, Phase-locked loop techniques- A survey, IEEE Trans. Ind.
Electron., 43(6), 1996, 609–615.
F. Blaabjerg, R. Teodorescu, M. Liserre and A. V. Timbus, Overview of control and grid
synchronization for distributed power generation systems, IEEE Trans. Ind. Electron., 53(5),
2006, 1398–1209.
S. Golestan, M. Monfared and F. D. Freijedo, Design-oriented study of advanced
synchronous reference frame phase-locked loops, IEEE Trans. Power. Electron., 28(2), 2013,
765–778.
D. Velasco, C. Trujillo, G. Garcera and E. Figueres, An Active Anti-Islanding Method Based
on Phase-PLL Perturbation, IEEE Trans. Power. Electron., 26(4), 2011, 1056-1066.
F. Gonzalez-Espin, E. Figueres and G. Garcera, An adaptive synchronous-reference-frame
phase-locked loop for power quality improvement in a polluted utility grid, IEEE Trans. Ind.
Electron., 59(6), 2012, 2718–2731.
P. Roncero-Sanchez, X. del Toro Garcia, A. P. Torres and V. Feliu, Fundamental Positiveand Negative-Sequence Estimator for Grid Synchronization Under Highly Distributed
Operating Conditions, IEEE Trans. Power. Electron., 28(8), 2013, 3733-3746.
S. A. Oliveira da Silva, R. Novochadlo and R.A. Modesto, Single-phase PLL structure using
modified p-q theory for utility connected systems, in Proc. IEEE Power Electron. Spec. Conf.
(PESC 2008), 2008, 4706-4711.
M. Karimi-Ghartemani, M. Mojiri, A. Safaee, J. A. Walseth, S. A. Khajehoddin, P. Jain and
A. Bakhshai, A new phase-locked loop system for three-phase applications, IEEE Trans.
Power. Electron., 28(3), 2013, 1208-1218.
I.Carugati, P. Donato, S. Maestri, D. Carrica and M. Benedetti, Frequency adaptive PLL for
polluted single-phase grids, IEEE Trans. Power. Electron., 27(5), 2012, 2396-2404.
F. Liccardo, P. Marino and G. Raimondo, Robust and fast three-phase PLL tracking system,
IEEE Trans. Ind. Electron., 58(1), 2011, 221-231.
Y. F. Wang , and Y. W. Li, Grid Synchronization PLL Based Cascaded Delayed Signal
Cancellation, IEEE Trans. Power. Electron., 26(7), 2011,1987-1997.
N. R. N. Ama, F. O. Martinz, L. Matakas, Jr. and F.Kassab Junior, Phase-locked loop based
on selective harmonics elimination for utility applications, IEEE Trans. Power. Electron.,
28(1), 2013, 124-153.
Q. Zhang, X .-D. Sun, Y.- R. Zhong, M. Matsui and B.-Y. Ren, Analysis and design of a
digital phase-locked loop for single-phase grid-connected power conversion systems, IEEE
Trans. Ind. Electron., 58(8), 2011, 3581-3592.
P. Rodriguez, A. Luna, R. S. Munoz-Aguilar, I. Etxeberria-Otadui, R. Teodorescu and F.
Blaabjerg, A Stationary Reference Frame Grid-Connected Power Converters
UnderDdverseGridConditions, IEEE Trans. Power. Electron., 27(1), 2012, 99-112.
X. Guo, W. Wu and Z. Chen, Multiple-Complex Coefficient-Filter-Based Phase-LockedLoop and Synchronization Technique for Three-Phase Grid-Interfaced Converters in
Distributed Utility Networks, IEEE Trans. Ind. Electron., 58(4), 2011, 1194-1204.
75
International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print),
ISSN 0976 – 6553(Online) Volume 4, Issue 5, September – October (2013), © IAEME
[18] G. Escobar, M. F. Martinez-Montejano, A. A. Valdez. P. R. Martinez and M. HernandezGomez, Fixed-reference-frame phase-locked loop for grid synchronization under unbalanced
operation, IEEE Trans. Ind. Electron., 58(5), 2011, 1943-1951.
[19] F. D. Freijedo, A. G. Yepes, O. Lopez, A. Vidal and J. Doval-Gandoy, Three-Phase
PLLsWith Fast Postfaultretracking and Steady-State Rejection of Voltage Unbalance and
Harmonics by Means of Lead Compensation, IEEE Trans. Power. Electron., 26(1), 2011, 8597.
[20] P. Rodriguez, J. Pou, J. Bergas, J. I. Candela, R. P. Burgos and D. Boroyevich, Decoupled
double synchronous reference frame PLL for power converters control, IEEE Trans. Power.
Electron., 22(2), 2007, 584-592.
[21] M. F. Martinez-Montejano, G. Escobar and R. E. Torres-Olguin, Fixed reference frame
phase-locked Loop for unbalanced line voltage conditions, in Proc. IEEE Power Electron.
Spec. Conf. (PESC 2008), 2008, 4723-4729.
[22] M. Ciobotaru, R. Teodorescu and F. Blaabjerg, A new single-phase PLL structure based on
second order generalized integrator, in Proc. IEEE Power Electron. Spec. Conf. (PESC 2006),
2006.
[23] S.Golestan, M. Monfared, F. D. Freijedo and J.M. Guerrero, Dynamics assessment of
advanced single-phase PLL structures, IEEE Trans. Ind. Electron., 60(6), 2013, 2167–2177.
[24] P. S. B. Nascimento, H. E. P. de Souza, F. A. S. Neves and L. R. Limongi,
FPGAImplementation of the Generalized Delayed Signal Cancelation- Phase Locked Loop
Method for Detecting Harmonic Sequence Components in Three-Phase Signals, IEEE Trans.
Ind. Electron., 60(2), 2013, 645–658.
[25] H. Geng, D. Xu and B. Wu, A Novel Hardware-Based All-Digital Phase-Locked Loop
Applied to Grid-Connected Power Converters, IEEE Trans. Ind. Electron., 58(5), 2011, 17371745.
[26] T. Thacker, D. Boroyevich, R. Burgos and F. Wang, Phase-locked loop noise reduction via
phase detector implementation for single-phase systems, IEEE Trans. Ind. Electron., 58(6),
2011, 2482-2490.
[27] S. Golestan, M. Monfared, F. D. Freijedo and J. M. Guerrero, Design and Tuning of a
Modified Power-Based PLL for Single-Phase Grid-Connected Power Conditioning Systems,
IEEE Trans. Power. Electron., 27(8), 2012, 3639-3650.
[28] R. Santos Filho, P. Seixas, P. Cortizo, and A. Souza, Comparison of three single-phase PLL
algorithms for ups applications, IEEE Transactions on Industrial Electronics, 55(8), 2008,
2923–2932.
[29] D. Yazdani, A. Bakhshai, G. Joos, and M. Mojiri, A nonlinear adaptive synchronization
technique for grid-connected distributed energy sources, IEEE Trans. Power Electron., 23(4),
2008, 2181–2186.
[30] Y. Wang and Y. W. Li, A Grid Fundamental and Harmonic Components Detection Method
for Single-Phase Systems, IEEE Trans. Power Electron., 28(5), 2013, 2204-2213.
[31] T.Hirose and H.Matsuo, Standalone Hybrid Wind-Solar Power Generation System Applying
Dump Power Control Without Dump Load, IEEE Trans. Ind. Electron., 59(2), 2012, 988-997.
[32] Z. Shu, S.Xie,K.Lu,Y.Zhao,X.Nan,D.Qiu, F.Zhou and Q.Li, Digital Detection, Control, and
Distribution System for Co-Phase Traction Power Supply Application, IEEE Trans. Ind.
Electron., 60(5), 2013, 1831-1839.
[33] S.Y. Jung and K.Nam, PMSM Control Based on Edge-field Hall Sensor Signals Through
ANF-PLL Processing, IEEE Trans. Ind. Electron., 58(11), 2011, 5121-5129.
[34] B.Sivaprasad, O.Felix, K.Suresh, G.Pradeep Kumar Reddy And E.Mahesh, A New Control
Methods For Offshore Grid Connected Wind Energy Conversion System Using Doubly FedInduction Generator And Z-Source Inverter” International Journal of Electrical Engineering
76
International Journal of Electrical Engineering and Technology (IJEET), ISSN 0976 – 6545(Print),
ISSN 0976 – 6553(Online) Volume 4, Issue 5, September – October (2013), © IAEME
[35]
[36]
[37]
[38]
[39]
[40]
[41]
& Technology (IJEET), Volume 4, Issue 2, 2013, pp. 305 - 323, ISSN Print : 0976-6545,
ISSN Online: 0976-6553, Published by IAEME.
M.Saisesha, V.S.N.Narasimharaju, R.Madhu Sudanarao And M.Balaji, “Control Of Power
Inverters In Renewable Energy And Smart Grid Integration” International Journal of
Electrical Engineering & Technology (IJEET), Volume 4, Issue 1, 2013, pp. 200 - 207, ISSN
Print : 0976-6545, ISSN Online: 0976-6553, Published by IAEME.
Tran Quang Tho, Truong Viet Anh, “Three-Phase Grid-Connected Inverter Using Current
Regulator” International Journal of Electrical Engineering & Technology (IJEET), Volume 4,
Issue 2, 2012, pp. 293 - 304, ISSN Print : 0976-6545, ISSN Online: 0976-6553, Published by
IAEME.
Narayan G. Apte And Dr. Vishram N. Bapat, “Indirect Current Controlled Single Phase
Shunt Active Filter” International Journal of Electrical Engineering & Technology (IJEET),
Volume 4, Issue 4, 2013, pp. 264 - 273, ISSN Print : 0976-6545, ISSN Online: 0976-6553,
Published by IAEME.
Smt. Smita Singhai And Prof. Bharti Dewani, “Pll Based Shunt Active Harmonic Filter To
Compensate Multiple Non-Linear Loads” International journal of Electronics and
Communication Engineering &Technology (IJECET), Volume 4, Issue 4, 2013, pp. 198 205, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472, Published by IAEME.
W. Kester, (2005). TheDataConversionHandbook, Chapter 8, Newnes, Retrieved. [Online].
Available:http://www.analog.com/library/analogDialogue/archives/39-06/data_conversion_
handbook.html
AnadigmApexdpASP
Family
User
Manual
(2006).
[Online].
Available:
http://www.anadigm.com/_doc/UM000231-U001.pdf.
Morales, D., A. Garcia, E. Castillo, M. Carvajal, J. Banqueri and A. Palma, Flexible ECG
acquisition system based on analog and digital reconfigurable devices, Sensors and
Actuators, 165, 2011, 261–270.
77