Proceedings
of IPACK2005
Proceedings
of IPACK2005
ASME InterPACK
‘05
ASME InterPACK
'05
July 17-22,
San Francisco,
California,
USA
July 17-22,
San Francisco,
California,
USA
IPACK2005-73018
InterPack2005-73018
REDESIGNS OF HSOP PACKAGE FOR HIGH POWER CONSUMPTION BASED ON THE
NUMERICAL THERMAL SIMULATION ANALYSIS
Jinfa Chen
Department of Technology Management
Kao Yuan Institute of Technology
Kaohsiung, Taiwan
John Chia
Department of Technology Management
Kao Yuan Institute of Technology
Kaohsiung, Taiwan
Keywords: FEM, Thermal Analysis, Multilayer Design, HSOP, DOE
ABSTRACT
A Heat Slug Outline Package (HSOP) with different design
concepts to improve its thermal performance is investigated.
The thermal performance of the standard designs of TSSOP
usually could not pass the requirements for greater functional
integration in wireless frquency and reduction in power
consumption, e.g. for a radio frequency (RF) front-end IC’s in
silicon its power consumption can be increased about twice
when the design frequency increases from 2.0 GHz to 3.5 GHz.
The configuration of HSOP28 proposed here is redesigned
based on the Thin Shrink Small Outline Package (TSSOP) that
is a plastic encapsulated semiconductor device complied with a
standard Surface Mount Technology (SMT). In order to
accommodate a chip with the same size but double it power
consumption, various types of lead frame design for HSOP
packages are studies. It is therefore an object of the present
study to investigate what will be the maximum thermal
improvement of HSOP package compared to the corresponding
same size of TSSOP package, which is also related to further
reliability issue of this type of IC package, i.e. the thermal
fatigue life calculation. Studies presented here are also taken
into account the thermal performance of HSOP package
associated with different multi-layers PCB designs and the
thermal conductivity variations, where the package internal
heat conduction as function of board thermal conductivity can
be made.
INTRODUCTION
The configuration of thin shrink small outline package
(TSSOP) is a plastic encapsulated semiconductor device. It
comprises a die pad, die pad support pins suspending the die
pad, and an IC chip mounted on the die pad. Thin metal wire is
then utilized for connecting the electrode of the IC chip to
leads. A sealing resin is used for sealing the whole components,
in which the perimeter of leads are trimmed and formed, and
can be soldered directly to the PCB to provide the direct
electrical and heat paths (Lau and Lee, 1999). The TSSOP
package is usually used in many low lead-count applications
involving surface mount packages for RFIC. The thermal
performance of TSSOP packages has required to increase it
power consumption, but not allowable junction temperatures.
This offers significant challenges to package designers in
thermal reliability concerns with a newer package structure and
smaller geometry in complying with the current SMT (Barcohen, Watwe and Seetharamu, 2001). Thermal resistance
analysis of TSSOP package is a quick way and is most often
used to determine package thermal characterization in an
attempt to account for end-use environments. In addition to
laboratory measurement, the thermal resistance of TSSOP
package involves geometry, material and IC power variations,
all of which are calculated differently and current can be
estimated accurately by dedicated finite element analysis
(FEA). In this study, the thermal resistance of HSOP28
compared to TSSOP42 package with different lead-frame
designs follow instructions specified in MIL-STD-833 Method
1012.1, EIA/JESD 51-3, and EIA/JESD 51-7 and are examined
by different thickness of multi-layers PCB designs with thermal
conductivity variations.
The thermal performance of HSOP packages in high
precision power applications is required to maximize it power
consumption while decreasing the package size, but the
increase of junction temperatures is not allowable. The thermal
performance of the standard designs of TSSOP usually couldn't
pass the common industrial requirement for high power
dissipation, especially, for applications such as higher
frequencies of RF devices. This offers significant challenges to
package designers in thermal reliability concerns with a newer
package structure and smaller geometry (Kamath and
Tummala, 2001). Here thermal analysis of HSOP package and
the Junction-to-Ambient θJA is used as a quick way to
determine package thermal characterization in an attempt to
account for the end-user environments.
REDESIGN OF PACKAGE CONFIGURATION
In order to accommodate higher power chip and increase
the package heat dissipation without much change in current
1
Copyright © 2005 by ASME
TSSOP package configuration that complies with a standard
Surface Mount Technology (SMT), there are 7 dummy leads
were welded together with the die pad to form a wing at the
sides which function as a heat slug. The variations of width of
the die pad wing welded with the lead section are given in a
range of 2.6~4.4 mm. Figure 1 shows the details outline
drawings of lead frame illustration for TSSOP42 and two
HSOP28 package designs. The finite element models of
TSSOP42 and HSOP28 are then created based on the package
outline specifications for the thermal analysis.
0.350
0.350
0.800
0.800
8.000
8.000
7.500
7.500
2.800
2.800
4.388
6X0.8+0.35=5.150
18.500
18.500
0.350
0.800
7.500
8.000
2.800
2.575
Unless Otherwise
Specified
Unit
International Semiconductor Technology LTD. Scale
mm
15 : 1
Package Code
HSOP42(2.8X8.0)
Material
C194 FH
Tolerance
Drawn
Checked Approved
Copper foil
Proj
飛信半導體股份有限公司
General
Roughness
Drawing No
MULTI-LAYERS OF PCB DESIGN ALTERNATIVES
It is known that not only the geometry of package but also
the design of printed circuit board (PCB) will greatly influence
how much the heat is transferred to the PCB and away from the
chip (Romm and Purdom, 1999; Chia and Yang, 2003). Here
we provide a series of package thermal data based on different
test-board PCB profiles and designs, the package heat flow path
as a function of board thermal conductivity is included in the
numerical model. Therefore, meaningful comparisons of
package thermal data between suppliers can be made by our
thermal analysis. The drawings shown in Figure 2 represent one
of three types of multi-layer PCB designs in our Design of
Experiment (DOE) simulations. The build-up thickness for
these three types of multi-layer PCB is proposed by 1.6mm, 1.0
mm and 0.6 mm; respectively. The copper mass per unit area
range is specified in the JEDC and IEC publications. Here, for
external layers a copper foil with a mass of 152 g/m2 (thickness
18 µm) thickness, whereas 35 µm thickness for internal layers
is adopted in our analysis. The area percentage of copper trace
layout design in density is assumed to be a range of 20% ~
50%.
18 um
.25 mm
35 um
Rev
6x0.8+0.35=5.150
Dimension ± 0.025
By
Jemi Wu
Date
09-06-00'
1
18.500
Angle
± 30'
Sheet 1 of 1
Size
A4
18 um
0.15 mm
Figure 1 TSSOP42 (upper right) and HSOP28 Package
Outline Drawings
35 um
1.0 mm
18 um
0.15 mm
35 um
0.6 mm
THERMAL PROPERTIES OF MATERIAL ASSEMBLIES
The materials involved a thermal computation, which are
the package assembly composition and an EIA standard PCB,
have different thermal properties. At present study, through the
collection and analysis of historical data, only the properties are
sensitive to thermal resistance computation is listed in Table 1.
It is well known that silicon thermal conductivity can be highly
temperature dependent. However, for simplicity, a temperature
dependence of chip thermal conductivity was not included in
current study.
Table 1 Material Properties of HSOP/TSSOP Package
Assembly
Conductivity
Material
(W/ mm oC)
Chip
1.48x10-1
Glue
1.10x10-3
Leadframe
1.70x10-1
Molding
5.86x10-4
Solder
5.06x10-2
Copper Foil
3.89x10-1
FR4
3.50x10
-4
0.2 mm
35 um
35 um
.25 mm
0.15 mm
35 um
0.15 mm
18 um
18 um
0.6 mm
1.0 mm
1.6 mm
18 um
Figure 2 Four Layers of PCB Build-up Designs
(t=1.6mm, 1.0mm and 0.6mm)
TAGUCHI ORTHOGONAL ARRAY FOR SIMULATIONS
Parameters effecting on the thermal performance of
package concerned here are the widths of the die pad wing
fused with lead section, the number of PCB layers and
thickness, the copper mass per unit area, and die size. Each
parameter is given three levels of design alternatives. The width
of the die pad wing fused with lead section is given 2.6, 3.5 and
4.4 mm. Levels for number of PCB layers are 2, 4 and 6 layers.
Levels for the percentage of Cu mass per unit are 20%, 30%
and 50%. The three levels of PCB thickness are 1.6 mm, 1.0
mm and 0.6 mm. Table 2 shows 3 different sizes of
accommodable IC and their thermal requirements.
Table 2 Thermal Resistance Value (θJA) Requirements
for HSOP28
θJA Unit: (0C/W)
Size of
IC
θJA for
θJA for
Chip package Power Tj=125oC
Tj=150oC
(mmxmm) (W) Requirement Requirement
A
B
C
2
2.76 x 3.33
2.69 x 1.98
3.57 x3.76
2.2
1.7
1.7
34.1
44.1
44.1
45.5
58.8
58.5
Copyright © 2005 by ASME
A series of statistical numerical simulations based on the
Taguchi’ experimental designs is conducted. There are five
parameters with three levels were selected in our design of
experiment of numerical simulations. The above conditions
necessitate an eighteen trials, i.e. L18 orthogonal array is
required to cover all necessary factor variations. However, the
variations of the die pad wing fused with lead section given 2.6
~4.4 mm in width are neglectable compared to other factors,
such as the dimension of PCB. Here only four parameters with
3 levels of variation were adopted in our study. A detailed
design matrix is reduced to be L9 array and shown in Table 3
(Krottmaier, 1994), which are total eighteen simulations are
needed to perform for both HSOP and TSSOP packages. The
number of trial is then less required simulations. With these
number of parameter combinations, numerical results will not
neglect one of the main effects from our concerns.
Table 3 Simulation Sequence from Layout of
Orthogonal Array, L9
Table 4. Heat Transfer Coefficients on BC surfaces
Item
Position
W/mm2 oC
Upper surface
2.98x10-6
PCB Test Board Lower surface
5.96x10-6
Vertical surface 1.93x10-6
Mold Compound Upper surface
-5
1.03x10
Vertical surface 3.54x10-5
Typical thermal simulations of a TSSOP package that is
direct soldered to PCB are performed as the first trial, where
Figure 3(a), (b) and (c) illustrates the temperature distribution
of package after computation, can be used for the thermal
resistance calculation. A series of thermal resistance values
(θJA) of HSOP and TSSOP package are then obtained from
numerical simulations.
Parameter
A
B
C
D
Test No. PCB
PCB/
Cu
Die size
/number of thickness Percentage
layer
1
1
1
1
1
2
1
2
2
2
3
1
3
3
3
4
2
1
2
3
5
2
2
3
1
6
2
3
1
2
7
3
1
3
2
8
3
2
1
3
9
3
3
2
1
SIMULATION AND RESULT INTERPRETATIONS
A steady-state thermal analysis is performed by the
commercial code ANSYS. A quarter of TSSOP42 and HSOP28
packages soldered on different PCB designs are modeled and
simulated by the analysis. Based the homing-in methods, the
chip power consumption and its size given by the IC providers
shown in the fifth column of Table 2 are considered to be the
last concerning factor. The temperature boundary conditions
applied on the surfaces of package and PCB, on which the
surfaces adjoining air Tambient, are assumed to be 50 oC. The
corresponding temperature B.C. shown in Table 4 is calculated
based on natural convection on isothermal heated vertical/
horizontal plate, which is given by (Holman, 1990; Chia and
Yang, 2003).
(for vertical )
(1)
h = Nu ∗ k / H
h = N u ∗ k /((W ∗ L) /( 2W + 2 L)) (for face down or up)
(2)
where N u is the Nusselt Number that is a function of Reynolds
Number, Re and the Prandtl number, Pr . k is the conductivity,
W and L are the width and length of PCB, respectively.
Figure 3 (a) Temperature Distribution of PCB with
TSSOP42 (1/4 model)
Figure 3 (b) Temperature Distribution of TSSOP42
(1/4 model)
3
Copyright © 2005 by ASME
Figure 3 (c) Temperature Distribution of TSSOP42
Leadframe (1/4 model)
Figure 4 (a) Temperature Distribution of PCB with
HSOP28 (1/4 model)
It is our first concern on the PCB designs that can alter the
thermal performance of an IC package in use. In our studies,
the number of layers of PCB illustrated in Figure 1 was altered
from 2 to 6 layers, the copper trace density changed from 20%
to 50%, and its thickness was altered from 1.6 mm, 1.0 mm to
be 0.6 mm, respectively. It was found that the thermal
resistance, θJA is decreased while increasing number of layers
of PCB or trace density of PCB. To address the issues of PCB
thickness h, and copper trace density d, numerical simulations
were performed again by altering the thickness of PCB.
Numerical results depict the thinner PCB with a higher copper
foil density yields higher thermal effective by a lower thermal
resistance value.
In order to investigate the thermal improvement of TSSOP,
an alternative lead-frame design as HSOP, with respect to same
material properties and boundary conditions, in comparison
with TSSOP is analyzed under conditions stated above. Figure
4(a) shows a typical temperature distribution of the HSOP
package by ANSYS where HSOP is direct soldered to PCB. To
look into the temperature distribution of HSOP package and
lead frame inside as shown in Figure 4(b) and 4(c) illustrates
the redesign of HSOP package can yield better thermal
performance than TSSOP, however, simple redesign TSSOP
package structure may not fulfill the requirements of thermal
value θJA decrease in half. It was found that the thermal
performance of package could be significantly changed by the
number of layers and thickness of PCB designs. To fulfill such
a requirement, an optimum of thermal value θJA for a given
package structure that is a function of thickness h, copper trace
density d, and number of layers, N was taken into account.
Figure 4 (b) Temperature Distribution of HSOP28
(1/4 model)
Figure 4 (c) Temperature Distribution of HSOP28
Leadframe (1/4 model)
Numerical results computed θJA values of HSOP42 and
HSOP28 attached on a multi-layers of PCB from the
simulations are typical listed on Tables 5 and 6, where only the
4
Copyright © 2005 by ASME
values (θJA) for PCB thickness = 1.6 mm with a range of 20%
~50% copper trace density are given. It can be expected the
thinner PCB and higher percentage of copper density will
provide the better heat dissipation path in which the lower
thermal resistance can be obtained. Table 7 is the summary of
simulation results based on the sequences shown on Table 3.
The results show that HSOP yields better thermal performance
than TSSOP. The parameter D shown in Table 8, the chip size
significantly influences the thermal performance of package
compared to other parameters in our calculations, where D3 is
the smallest die size in design..
Finally, the locations of socket for package mounted on the
PCB affecting on thermal performance were considered in our
analysis too. Figures 5 (a) and (b) show the results from the
socket located on the edge of PCB. It was found that a package
at the center of PCB yields the best thermal performance since
the PCB can provide the best thermal dissipation path. In our
case as shown in Tables 5 and 6, for 30% of copper trace of
density the thermal resistance values (θJA) can be decreased
from 73.18 to 50.07 for a TSSOP while decreasing from 56.03
to 29.52 for a HSOP if the location of socket is designed from
the edge of PCB moving to center of PCB.
Table 8 Effects of Individual parameters of DOE
simulation
Parameter
Total Result, θJA
Average, θJA
TSSOP HSOP TSSOP HSOP
PCB layer
A1
162.4
90.2
54.1
30.1
A2
142.8
69.7
47.6
23.2
A3
133.9
61.2
44.6
20.4
PCB
B1
155.4
84.1
51.8
28.0
thickness
B2
150.9
76.2
50.3
25.4
B3
132.7
60.9
44.2
20.3
Cu
C1
151.4
80.2
50.5
26.7
percentage
C2
148.3
75.7
49.4
25.2
C3
139.3
65.2
46.4
21.7
Die size
D1
130.6
67.8
43.5
22.6
D2
220.0
110.8
73.3
36.7
D3
88.4
43.2
29.5
14.4
Table 5 Thermal Resistance Values (θJA) of TSSOP42
(1.6 mm PCB thickness)
θJA Unit: (0C/W)
Copper Foils
20%
30%
50%
2 lyrs PCB
53.58
50.07/73.18
46.65
4 lyrs PCB
47.68
45.60/67.24
43.72
Table 6 Thermal Resistance Values (θJA) of HSOP28
(1.6 mm PCB thickness)
θJA Unit: (0C/W)
Copper Foils
20%
30%
50%
2 lyrs PCB
33.70
29.52/56.03
25.40
4 lyrs PCB
27.15
24.59/51.76
22.15
Table 7 Results of Thermal Resistance Values (θJA)
based on L9 Orthogonal Array
Test No. Parameter, (θJA) of TSSOP42 (θJA) of HSOP28
ABCD
1
1111
53.58
33.70
2
1222
80.86
43.66
3
1333
27.92
12.80
4
2123
31.92
17.21
5
2231
41.53
19.27
6
2312
69.30
33.23
7
3132
69.86
33.14
8
3213
28.54
13.23
9
3321
35.48
14.87
Figure 5 (a) Temperature Distribution of PCB and
HSOP with a Socket located at Edge
Figure 5 (b) Temperature Distribution of Leadframe
with a Socket located at Edge
CONCLUSIONS
This study based on thermal computation has described
thermal improvement of HSOP package design compared to
TSSOP that encourage the modification of package design for
5
Copyright © 2005 by ASME
higher power IC in complying with standard SMT processing
while yielding much cost effective.
About 30% ~ 40% reduction in the thermal resistance
values of HSOP28 package lower than TSSOP42 with a same
size and similar package structure can be obtained. The further
improvement of thermal resistance values of HSOP28 package
can be obtained when it is soldered on more layers and higher
percentage of copper foil area but less thickness of PCB design.
The thermal data of HSOP28 package presented here give
simple representative thermal performance of the package in
use. It significantly depends on the end-user PCB designs and
chip size for checking the maximum power dissipation of IC
package in field.
ACKNOWLEDGMENTS
The author gratefully thanks people from Package
Development Center, International Semiconductor Tech. for
their helps and comments. This paper is based on a research
conducted at the IST Package Development Center.
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Bar-Cohen, A.., A. Watwe and K. N., Seetharamu,
“Fudamentals of Thermal Management” Chapter 6,
Fundamentals of Microsystems Packaging, Editor, R. R.,
Tummala, McGraw-Hill, 2001.
Chia, J. and C., Yang, “ Thermal Management of QFN48
Package Attached to Different Multilayers of Printed Circuit
Board Designs” Pro. Of Interpack03, Hawaii, USA, 2003.
Holman, J. P., “Heat Transfer,” 7th ed., McGraw Hill, New
York, pp. 333-352.
Hunter S., "Statistical Design Applied to Product Design,"
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Kamath, S. M. and R. R. Tummala, “Fudamentals of
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Krottmaier, J., "Optimizing Engineering Designs,"
McGraw-Hill, UK, 1994.
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New York, 1999.
Romm, D. W. and R. H., Purdom, “Thermal
Characteristics of Linear and Logic Packages using JEDEC
PCB Designs,” report SZZA017A, Texas Instruments, 1999.
EIA/JESD 51-3, "Low Effective Thermal Conductivity
Test Board for Leaded Surface Mount Packages, "1996.
EIA/JESD 51-7, "High Effective Thermal Conductivity
Test Board for Leaded Surface Mount Packages," 1999.
"Plastic Encapsulated Semiconductor Device and Method
of Manufacturing the Same," US patent 5,942,794, Aug. 24,
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