TZ2100 Series
Technical Data Sheet
CMOS Digital Integrated Circuit Silicon Monolithic
TZ2100 Series
Application Processor Lite ApP Lite™
Overview
TZ2100 series are application processors utilizing a single 600 MHz ARM® Cortex® -A9 core with a floating
point unit (FPU), a 2D graphics, a parallel LCD controller interface, camera input interface and an 1 MB of
integrated SRAM. This device is highly integrated, as a main processor for various applications with integrated a
USB host or device controller (optional), an Ethernet controller, an extended external buses, and rich interfaces.
The TZ2100 processors are supported a security service with an encryption and decryption capability (optional)
and a secure boot function (optional) to enable construction of a robust secure system. These products are suitable
for various applications, in addition, an SRAM and a RTC for back-up mode of power state are incorporated.
The TZ2100 series are family products of ApP Lite™.
Applications
This product is leveraged to meet needs of following applications; human machine interface, machine to machine
interface, single-board computing and portable data terminal.
Features
● Host CPU
‒ ARM Cortex-A9 MP Core (Revision r4p1p)
Up to 600 MHz operation frequency
‒ ARMv7-A instruction set architecture
‒ Floating point unit (FPU)
‒ 32 KB L1 I cache/ D cache
‒ 128 KB L2 cache
‒ Memory management unit: 128-entry TLB
‒ Debug technology:
CoreSightTM (revision: r2p0-01)
v7 debug architecture, JTAG debug interface
‒ Proprietary low power mode for WFI
● System contoller
‒ System management unit (SMU):
Reset management, clock controller
‒ Power management unit (PMU):
External and internal power management
‒ Secure boot (optional)
‒ Secure services (optional)
AES, SHA-1, SHA-256, RSA
Random number generator (RNG)
‒ Interruption controller
● SDRAM controller
‒ DDR3 / 3L memory interface (16-bit width)
‒ Data rate:
800 Mbps
‒ Memory size: up to 512 MB
‒ ODT control
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● Integrated SRAM
‒ 1 MB SRAM
‒ 32 KB SRAM for data backup
Low power dissipation for data retention
● Real time clock (RTC)
Low power dissipation
‒ Clock frequency:
32.768 kHz
‒ Clock timer, Calendar
‒ Time adjustment, alarm interrupt, Periodic interrupt,
BCD format
● DMA controller
‒ AXI protocol DMA with DMA330 supported
‒ Multiple transfer mode
Memory to Memory, Memory to Peripheral, and
Peripheral to Memory
‒ 8 channels thread for DMA transfer and one channel
thread for DMA management
● Timer
‒ 16 channels of 32-bit down counter
enable one channel as watch dog timer
● 2D graphics accelerator
‒ Toshiba original graphics accelerator
‒ Blitting, Rotation, Transforming, Drawing
● YUV to RGB converter
‒ Input format: YUV 4:2:0 8bit, YUV 4:2:2 8bit
‒ Input resolution: QVGA, VGA, up to 2048×2048
‒ Output format: RGBA8888, ARGB8888, RGB565,
RGB888
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Rev. 1.6
© 2015 Toshiba Corporation
TZ2100 Series
Technical Data Sheet
● LCD controller
‒ Parallel output:
‒ Output resolution:
‒ Frame rate:
‒ Input format:
●
●
●
●
●
●
RGB 24 bits
up to WVGA
up to 60 fps
RGBA8888, ARGB8888,
RGB565, ARGB1555
‒ Alpha blending: up to five planes
Camera input:
‒ One channel
‒ Parallel input:
8-bit Data
‒ Frame rate:
up to 60 fps
‒ Resolution (by 8-pixel): up to 2048 × 2048
‒ Input format:
YUV 4:2:2 8-bit,
RAW8, RGB565,
ITU-RBT.656
Audio interfaces
‒ Two channels: 1 channel dedicated for output
1 channel for input and output
‒ Format:
I2S stereo, LR stereo, PCM monaural
‒ Sampling clock:
192 kHz, 96 kHz, 48 kHz,
44.1 kHz, 32 kHz, etc.
USB2.0 host interface (optional)
‒ One port USB 2.0 (EHCI rev 1.0, OHCI)
‒ Data transfer rate: 480 Mbps / 12 Mbps / 1.5 Mbps
‒ Transmission mode:
control, interrupt,
bulk, isochronous
USB2.0 device interface (optional)
‒ One port (exclusively used by Host / Device)
‒ Data transfer rate: 480 Mbps / 12 Mbps / 1.5 Mbps
‒ Transmission mode:
control, interrupt,
bulk, isochronous
10/100 Ethernet MAC
‒ One Ethernet MAC channel for 10/100 Mbps
‒ IEEE Standard 802.3,2000 Edition
‒ Support full duplex/half duplex communication
‒ RMII (10/100 Mbps) interface to Ethernet PHY
device
‒ IEEE802.3x flow control function
‒ Support Jumbo Frame (up to 4 KB)
eMMC / SD Card / SDIO interface
‒ Two channels for 4-bit data width.
‒ One channel for 8bit-data width.
‒ Data transmission rate: 150 MHz (max)
‒ Supported standard:
eMMC Ver. 4.5, SD Ver. 3.0, and SDIO Ver. 3.0
DS, HS, SDR12, SDR25, SDR50, SDR104 modes.
‒ SD card control terminals
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● SPI Flash Memory Controller interface
‒ Chip select: 2-bit
‒ Data bus width: Single, Dual or Quad mode interface
‒ Data transmission rate: up to 50 MHz
‒ Memory size: from 64 KB to 128 MB
● SPI interfaces (for master controller and transmission)
‒ Seven channels for transmission or two for master
controller can be selected.
Data transmission rate: up to 25 MHz
‒ One channel for slave controller
Data transmission rate: up to 5 MHz
● External BUS interface
‒ Data BUS width:
32 bits, 16 bits and 8 bits Coexistence is allowed.
‒ Address BUS width:
27 bits
‒ Memory capacity:
up to 768 MB
‒ Chip select:
4-bit
‒ Asynchronous read/write, asynchronous page read,
synchronous burst read/write.
‒ Asynchronous boot devices are supported.
● UART interfaces
‒ Four channels. One channel without flow control
port.
‒ Data transmission rate: up to 1.5 Mbps
‒ Flow control ports
Compatible with UART 16550 data format
Support external clock input.
Full duplex transmission mode and DMA
transfer mode
● I2C bus interfaces
‒ Four channels
‒ Open drain output and Schmidt-trigger input
‒ Support fast mode plus (up to 1000 kbps), Fast
mode, Standard mode
‒ A master (compatible with a multi-master) or a slave
is selectable.
● Parallel port input interface
‒ One channel
‒ Data width: 8-bit
‒ Data FIFO: 8-bit × 16-stage
● GPIO interface
‒ Up to 128 channels
‒ External inputs can be used as interrupt signals.
● AD converter inputs
‒ Four input channels
‒ 12-bit successive AD converter
‒ Sampling rate: up to 1.07 MHz
● PWM outputs
‒ Six channels
‒ Frequencies and duty ratios can be arbitrarily set.
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TZ2100 Series
Technical Data Sheet
List of Products
This table shows TZ2100 Series lineups. The following table shows the items which have a difference in
specifications.
Product Number
Maximum
CPU Operation
Frequency (MHz)
TZ2100XBG(O,2)
TZ2100XBG(O,5)
TZ2102XBG(O,3)
TZ2102XBG(O,6)
TZ2101XBG(O,6)
300
300
600
600
600
Operating
Temperature
Range
Ta （°C）
-40～85
-20～80
-20～80
-40～85
-40～85
Internal
Voltage
Range （V）
Security
service
availability
USB 2.0
Interface
1.00～1.20
1.00～1.20
1.06～1.21
1.10～1.20
1.10～1.20
—
—
—
—
Available
—
Host / Device
Host
Host / Device
Host / Device
ApP Lite is a trade mark of Toshiba corporation.
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TZ2100 Series
Technical Data Sheet
List of Contents
Overview............................................................................................................................................................... 1
Applications .......................................................................................................................................................... 1
Features ............................................................................................................................................................... 1
List of Products..................................................................................................................................................... 3
Preface ................................................................................................................................................................. 8
References ........................................................................................................................................................... 8
Conventions in this document .......................................................................................................................... 8
1. Features ........................................................................................................................................................... 9
1.1. CPU ........................................................................................................................................................... 9
1.2. System controller ....................................................................................................................................... 9
1.3. SDRAM controller ...................................................................................................................................... 9
1.4. Integrated Memory .................................................................................................................................. 10
1.5. Real time clock (RTC) ............................................................................................................................. 10
1.6. Peripheral functions ................................................................................................................................. 10
1.7. Graphics Accelerator, YUV Conversion and LCD Controller.................................................................. 10
1.8. Camera Input ........................................................................................................................................... 11
1.9. Audio interfaces ....................................................................................................................................... 11
1.10. High-speed interface Controller ............................................................................................................ 11
1.11. Peripheral Interfaces ............................................................................................................................. 12
2. Block Diagram ................................................................................................................................................ 14
3. Pin Information ............................................................................................................................................... 15
3.1. Pin Alignment .......................................................................................................................................... 15
3.2. Pin List (Ball number order)..................................................................................................................... 16
3.3. Signal description (in order of pin function)............................................................................................. 20
Clock Sources and Reset ........................................................................................................................................... 20
DDR3/DDR3L Memory Interface ................................................................................................................................ 20
SPI Flash Memory Controller Interface....................................................................................................................... 22
eMMC / SD card / SDIO Interfaces............................................................................................................................. 22
External BUS interface ............................................................................................................................................... 23
UART interface ........................................................................................................................................................... 24
I2C bus interface ......................................................................................................................................................... 25
SPI Interfaces (for Master Controller) ......................................................................................................................... 26
SPI Interfaces (Dedicated for Transmission) .............................................................................................................. 26
SPI Interface (for Slave Controller) ........................................................................................................................... 27
USB2.0 Host or Device Interface .............................................................................................................................. 27
Ethernet MAC Interface ............................................................................................................................................ 27
Camera Input ............................................................................................................................................................ 28
Display Output .......................................................................................................................................................... 28
Audio Interface ......................................................................................................................................................... 29
PWM Output ............................................................................................................................................................. 29
Parallel Port Input Interface ...................................................................................................................................... 29
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Technical Data Sheet
GPIO Interfaces ........................................................................................................................................................ 30
AD Converter Input ................................................................................................................................................... 33
JTAG interface for debugging ................................................................................................................................... 33
Others ....................................................................................................................................................................... 33
VDDs and VSSs ....................................................................................................................................................... 34
3.4. Setting Pin Functions............................................................................................................................... 35
Setting pin function with Registers.............................................................................................................................. 35
4. Electrical characteristics................................................................................................................................. 38
4.1. Absolute Maximum ratings ...................................................................................................................... 38
4.2. Recommended Operating Conditions ..................................................................................................... 38
Operating Conditions of the TZ2100XBG ................................................................................................................... 38
Operating Conditions of TZ2102XBG ......................................................................................................................... 39
Operating Conditions of TZ2101XBG/TZ2102XBG (Extended Temperature Products) ............................................. 40
4.3. Current Dissipations ................................................................................................................................ 41
4.4. DC Characteristics................................................................................................................................... 42
Digital I/O pins ............................................................................................................................................................ 42
eMMC/SD Card/SDIO pins ......................................................................................................................................... 43
4.5. AC Characteristics ................................................................................................................................... 44
Clock Inputs ................................................................................................................................................................ 44
DDR3/DDR3L Memory Interface ................................................................................................................................ 45
SPI Flash Memory Controller Interface....................................................................................................................... 46
eMMC / SD Card / SDIO Interface.............................................................................................................................. 47
External Bus Interface ................................................................................................................................................ 50
4.5.5.1. Synchronous mode .......................................................................................................................................................50
4.5.5.2. Asynchronous Mode......................................................................................................................................................51
I2C Bus Interface ........................................................................................................................................................ 52
SPI Interface (for Master Controller and Transmission).............................................................................................. 54
SPI Interface (for Slave Controller) ............................................................................................................................. 55
Ethernet MAC interface .............................................................................................................................................. 56
Camera Input ............................................................................................................................................................ 57
LCD Output............................................................................................................................................................... 58
Audio Interface ......................................................................................................................................................... 59
Parallel Data Input .................................................................................................................................................... 61
AD Conversion Input ................................................................................................................................................ 61
5. Package ......................................................................................................................................................... 62
5.1. Package outline ....................................................................................................................................... 62
6. Revision history .............................................................................................................................................. 63
RESTRICTIONS ON PRODUCT USE............................................................................................................... 64
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Rev. 1.6
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Technical Data Sheet
List of Figures
Figure 2.1 Block diagram ......................................................................................................................... 14
Figure 3.1 Pin alignment of this product .................................................................................................. 15
Figure 5.1 Package Outline...................................................................................................................... 62
List of Tables
Table 3.1 Pin List (Ball number order) ..................................................................................................... 16
Table 3.2 Shared Pin Switching Table ..................................................................................................... 35
Table 6.1 Revision History ....................................................................................................................... 63
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Technical Data Sheet
* ARM, AMBA, Cortex, Jazelle, NEON, and TrustZone are registered trademarks of ARM Limited (or its
subsidiaries) in the EU and/or elsewhere. CoreLink and CoreSight are trademarks of ARM Limited (or its
subsidiaries) in the EU and/or elsewhere. All rights reserved.
* All other trademarks and trade names are properties of their respective owners.
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Rev. 1.6
TZ2100 Series
Technical Data Sheet
Preface
References
● Reference standard
‒ DDR3 SDRAM SPECIFICATION
Conventions in this document
● The numerical values are expressed as follows.
Hexadecimal number: 0xABC
Decimal number: 123 or 0d123 - Only when it needs to be explicitly shown that they are decimal numbers.
Binary number: 0b111 - It is possible to omit the "0b" when the number of bit can be distinctly understood
from a sentence.
● "_N" is added to the end of signal names to indicate low active signals.
● It is called "assert" that a signal moves to its active level, "deassert" to its inactive level.
● When two or more signal names are referred, they are described like as [m:n].
Example: S[3:0] shows four signal names S3, S2, S1, and S0 together.
● The characters surrounded by [ ] defines the register.
Example: [ABCD]
● "n" substitutes suffix number of two or more same kind of registers, fields, and bit names.
Example: [XYZ1], [XYZ2], and [XYZ3] to [XYZn]
● The bit range of a register is written like as [m:n].
Example: Bit[3:0] expresses the range of bits 3 to 0.
● The configuration value of a register is expressed by either the hexadecimal number or the binary number.
Example: [ABCD].EFG = 0x01 (hexadecimal), [XYZn].VW = 1 (binary)
● Word and Byte represent the following bit length.
Byte:
8-bit
Half word:
16-bit
Word:
32-bit
Double word:
64-bit
● Properties of each bit in a register are expressed as follows.
R: Read only
W: Write only
W1C:
Write 1 Clear - The corresponding bit is cleared (=0) when "1" is written to this bit.
W1S:
Write 1 Set - The corresponding bit is set (=1) when "1" is written to this bit.
R/W:
Read and Write are possible.
R/W0C:
Read/Write 0 Clear
R/W1C:
Read/Write 1 Clear
R/W1S:
Read/Write 1 Set
RS/WC:
Read Set/Write Clear - Set after read operation, cleared after write operation.
● Unless otherwise specified, register access supports only word access.
● The register defined as reserved must not be rewritten. Moreover, don't use the read value.
● The value read from the bit having default value of "—" is unknown.
● When a register containing both of writable bits and read-only bits is written, read-only bits should be written
with their default value. In the cases that default is "—," follow the definition of each register.
● Reserved bits of the Write-only register should be written with their default value. In the cases that default is
"—," follow the definition of each register.
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Rev. 1.6
TZ2100 Series
Technical Data Sheet
1. Features
1.1. CPU
(1) Host CPU
ARM Cortex-A9 MP Core (Revision r4p1)
Instruction set architecture: ARMv7-A architecture
Operation frequency:
600 MHz (Note 1) / 300 MHz / 150 MHz / 75 MHz etc., selectable
Level-1 instruction cache: 32 KB (4-wait set associative)
Lvevl-1 date cache:
32 KB (4-wait set associative)
Level-2 cache:
128 KB (8-wait set associative)
Data engine:
Floating point unit (FPU)
Support single and double precision data processing
Internal bus:
64-bit AXI master interface
Debug technology:
ARM® CoreSightTM (revision: r2p0-01)
v7 debug architecture, JTAG debug interface
Memory management unit: 128-entry TLB
Pipe line:
Super scalar, out of order
Proprietary low power mode to minimize power consumption in Wait for Interruption command
Note 1:
TZ2101XBG, TZ2102XBG only
1.2. System controller
(1) System management unit (SMU)
Reset management, clock controller
(2) Power management unit (PMU)
External and internal power management
(3) Secure boot (optional)
(4) Secure services (optional)
AES, SHA-1, SHA-256, RSA,
Random number generator (RNG)
(5) Interruption controller
Output interrupt requests to the host CPU
1.3. SDRAM controller
(1) SDRAM controller
DDR3 / 3L memory interface
Bus width:
16-bit
Data rate:
800 Mbps
Memory size:
up to 512 MB
Support self-Refresh mode
ODT controller
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Technical Data Sheet
1.4. Integrated Memory
(1) Internal SRAM
1 MB SRAM is contained for data and programming.
(2) SRAM for data backup
32 KB SRAM for data backup.
Low power dissipation for data retention in a separated power domain
1.5. Real time clock (RTC)
(1) Real time clock (RTC)
Frequency of oscillation:
32.768 kHz
Clock display (hour, minute, second), am-pm / 24-hour
Calendar (month, week, date, and leap year)
Time adjustment, alarm interrupt, Periodic interrupt, BCD format
Low power dissipation in a separated power domain
1.6. Peripheral functions
(1) DMA controller
Multiple transfer mode (Memory to Memory, Memory to Peripheral, Peripheral to Memory)
Original instruction set enables programmable DMA transfer.
Eight channel threads for DMA transfer and one channel thread for DMA management
(2) Timer
16 channels of 32-bit down counter.
One counter can be selected as a watchdog timer (WDT).
1.7. Graphics Accelerator, YUV Conversion and LCD Controller
(1) 2D graphics accelerator
Toshiba original graphics accelerator
Blitting engine (Alpha blending), Transforming engine, Rotation engine (Rotation, Scaling, Transparent),
Drawing engine (Anti-Aliasing)
Output format:
RGBA8888, ARGB8888, RGB565, ARGB1555
(2) YUV converter
YUV to RGB conversion
Input resolution: QVGA, VGA, 2048 × 2048 (max)
Input format:
YUV_4:2:0 8-bit, YUV_4:2:2 8-bit
Output format:
RGBA8888, ARGB8888, RGB565, RGB888
(3) LCD controller
Parallel output:
Output resolution:
Frame rate:
Input format:
Alpha blending:
2016-07-19
24-bit (RGB), Vsync, Hsync, Clock, Valid
up to WVGA (800 × 480 max)
up to 60 fps
RGBA8888, ARGB8888, RGB565, ARGB1555
up to Five planes
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Technical Data Sheet
1.8. Camera Input
(1) 8-bit Parallel
Parallel input:
Frame rate:
Resolution:
Input format:
8-bit Data, Vsync, Hsync/ Enable, Clock
up to 60 fps
up to 2048 × 2048 (by 8-pixel)
YUV 4:2:2 8-bit, RAW8, RGB565, ITU-RBT.656
1.9. Audio interfaces
(1) Audio Interfaces
Two channels:
Audio format:
Sampling frequency:
One channel dedicated for output, and the other one for output and input.
Selectable master or slave
I2S stereo, LR stereo, PCM monaural
192 kHz, 96 kHz, 48 kHz, 44.1 kHz, 32 kHz, 24 kHz
1.10. High-speed interface Controller
(1) USB2.0 host interface (optional)
USB2.0 host:
1 port
Complaint with USB2.0 (EHCI rev 1.0, OHCI supported)
Data transmission rate:
480 Mbps, 12 Mbps or 1.5 Mbps
Transmission mode:
control, interrupt, bulk, isochronous
(2) USB2.0 device interface (optional)
USB2.0 device:
1 port (exclusive use for Host / Device)
Data transmission rate:
480 Mbps, 12 Mbps or 1.5 Mbps
Transmission mode:
control, interrupt, bulk, isochronous
(3) 10/100 Ethernet MAC Interface
One MAC channel for 10/100 Mbps transmission speed
Complaint with IEEE Standard 802.3,2000 Edition
Support full duplex/half duplex communication
RMII (10/100 Mbps) interface to Ethernet PHY device
IEEE802.3x flow control
Jumbo Frame supported (up to 4 KB)
Upper level protocol function supported (automatic checksum calculation for receiving data)
Dedicated controller for PHY device register access
Interruption synchronizing mode
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Technical Data Sheet
1.11. Peripheral Interfaces
(1) External Bus Interface
Chip select:
4 bits
Data width:
32-bit / 16-bit / 8-bit (these widths can coexist)
Address width:
27 bits
Corresponding Memory size: up to 768 MB
Transfer system:
Asynchronous read/write
Asynchronous page read
Synchronous burst read/write
Boot device support:
Chip enable 0 enables use of a 32-/16-bit device as an asynchronous boot
device.
(2) eMMC / SD Card / SDIO Interface
Three channels:
The data width of one channel is 8 bits and two channels are 4 bits.
Data transmission rate:
150 MHz (max)
Boot device support:
One channel of eMMC and one channel of a SD card can be used as boot
devices.
Transmission mode:
DS/HS/SDR12/SDR25/SDR50/SDR104 for SD card/SDIO
Backward-compatibility/High-Speed/HS200 for eMMC
SD card control pins:
card detection, write protection, power, 3.3 V / 1.8 V voltage switch
Supported standard:
eMMC Ver. 4.5, SD Ver 3.0, and SDIO Ver 3.0.
(3) SPI Flash memory controller interface
Chip select:
2-bit
Boot device support
Data bus width:
Single, Dual or Quad mode
Data transmission rate:
50 MHz (max)
Memory size:
from 64 KB to 128 MB
Support four bytes addressing mode
(4) SPI interfaces (for master controller and transmission)
Two channels can be selected for the master controller. Up to seven channels for transmission can be
selected.
BUS width:
Single mode interface
Data transmission rate:
25 MHz as the maximum frequency, and 1/1 to 1/32767 prescaler is available.
Data FIFO:
16-bit × 16-stage
(5) SPI interface (for slave controller)
One channel
Bit width:
Single mode interface
Data transmission rate:
up to 5 MHz
Data FIFO:
16-bit × 16 stage
(6) UART interfaces
Four channels
Data transmission rate:
up to 1.5 Mbps
Three channels with flow control port
Auto flow control (CTS/RTS)
Complaint with UART 16550 data format
Support external clock input
Support full duplex communication, DMA transmission mode
One channel without flow control port (e.g. debug terminal)
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Technical Data Sheet
(7) I2C bus interfaces
Four channels
Open drain output and Schmidt-trigger input
Data transmission rate:
Standard mode:
up to 100 kbps,
Fast mode:
up to 400 kbps
Fast mode plus:
up to 1000 kbps
Operation mode:
Master (support multi-master) or Slave
(8) Parallel port input interface
Operate as a target and receives write data from an external host.
Data width:
8-bit
FIFO:
8-bit × 16-stage
Support the active polarity of a strobe signal.
(9) GPIO interfaces
128 channels
124 channels are shared with other functions (Open drain output at six channels).
Four channels are dedicated pins. The I/O power supply is VDD3V3_PA (described in Section 3.3.18).
Input or output direction configurable
External inputs can be used as interrupt signals.
Configurable to set pull-up or pull-down resister
(10) AD converter
Four channels
12-bit successive conversion
Sampling frequency:
1.07 MHz (max) when using one channel
379 kHz (max) when using four channels
(11) PWM output
Six channels
Configurable frequency and duty of pluses and synchronous output mode is supported.
Configurable pulse generator
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Technical Data Sheet
2. Block Diagram
Figure 2.1 shows a block diagram of the TZ2100 Series.
CPU
LCD Controller
ARM Cortex-A9
(600 MHz / 300 MHz)
(L1: I 32 KB/ D 32 KB)
(L2: 128 KB)
FPU
Peripherals
32bit EBUS I/F
2D Graphics
Accelerator
eMMC/SDIO x3
YUV Converter
SPIM/TX x7, SPIS
SPIB x2
UART x4
SDRAM
controller
1 MB SRAM
High speed I/O
Ethernet MAC
USB EHCI (Note 1)
USB
PHY
(Note 1)
USB OHCI (Note 1)
USB2.0 Dev (Note 1)
Camera Input
I2C x4
I2S x2
Encrypt engine
(Note 1)
ADC x4
Power management
Timer x14 (WDT)
PMU
PWM
Timer x2
GPIO
RTC
DMA Controller
Back up SRAM 32KB
Interrupt controller
Figure 2.1 Block diagram
Note 1:
2016-07-19
There are optional functions as follows:
USB2.0 device, USB2.0 host, security service functions and secure boot.
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Technical Data Sheet
3. Pin Information
3.1. Pin Alignment
Figure 3.1 shows a pin alignment of this product.
TOP VIEW
B
A
1
C
3
EMMC
0_DAT 0_DAT
VSS
EMMC
0
4
EMMC
EMMC
0_DAT 0_DAT
0_CLK
EMMC
1
5
EMMC
EMMC
0_CLK 0_DAT 0_DAT
B
EMMC
2
6
EMMC
EMMC
0_DAT 0_DAT
0_CMD
6
7
8
9
E3_N
LKO
DD2
DD11
DD14
DD19
E2_N
E_N
EB0_C
DD3
DD9
DD13
DD18
EB0_A EB0_A
E1_N
DD4
DD17
E0_N
DD1
DD6
DD7
DD12
DD16
LKB
LK
_15
GPIO0
GPIO0
GPIO0
GPIO0
GPIO0
_16
_17
_19
_20
_18
GPIO0
GPIO0
GPIO0
GPIO0
_21
_22
_24
_23
LKI
GPIO0
GPIO0
GPIO0
GPIO0
_25
_26
_27
_29
_28
DD5
_30
_31
CLK
SPIB0_ SPIB0_
IO2
IO1
MMC
EL2
EL3
_13
_14
R
GPIO0
I2C0_S GPIO0
T
GPIO0
GPIO0
U
XD
DDR0_
V
EL5
DDR0_ DDR0_
CL
_4
GPIO0
_8
_9
VSS
DQ11
DQ13
VSS
DQ15
DDR0_
DQ9
XD
_10
8_3V3
VDD1V
8_3V3
_SD0
3_PL_I
VDD3V
3_PL_I
2C
VDDC_
PA
GPIO0
VSS
_11
GPIO0
GPIO0
GPIO0
_5
_6
_7
DM1
DDR0_
VSS
DQS_N
DDR0_
DQ14
1
VREF
_3V3_E 8_3V3
MMC
_SD1
VDDC_
VSS
PA
VDDC_
PA
VSS
VDDC_
PA
VSS
DD22
DD21
AT0
AT4
16
17
18
19
AT10
AT11
AT13
AT14
AT15
VSS
AT8
AT12
AT16
AT18
AT19
AT20
AT22
EB0_D EB0_D EB0_D EB0_D EB0_D EB0_D EB0_D
VD_N
AT6
DD26
AT3
AT17
AT23
AT24
AT25
AT26
AT27
AT7
AT21
VSS
DQ8
VSS
EB0_B EB0_B
E0_N
E1_N
GPIO1
GPIO1 EB0_W XIN_3 XOUT_
_SD1
EBUS
EBUS
VDDC_
PA
VSS
VSS
VSS
VSS
VSS
VSS
PA
VSS
PA
VSS
1_DDR 1_DDR
VDDC_
PA
VSS
VDD_D VDD_D DDR0_
DRIO
DRIO
E_N
E2_N
VSS
VDDC_
AT31
EB0_B EB0_B
AT2
3_PL_
VSS
AT29
DD25
3_PL_
VSS
AT30
VSS
VSS
ZQ
3_PB
OEN_N RST_N
VDD3V
DBG_T LOWP
3_PB
CK
SYS_R
ESET_
3_PA
N
VDD3V
GPIO0
3_PA
_3
VDDC_ VDDPL
PA
VSS
MS
32K
DBG_S
RST_N
DO
AKEUP
VSS
GPIO0 POR_O
_0
DI
SYS_W
WR
R33
VDDPL
UT_N
WDT_
RSTOU
T_N
GPIO0
GPIO0
_2
_1
XIN
XOUT
R33
3_USB 3_USB
USB0_ USB0_ USB0_ USB0_ USB0_
L0
REXT
CLK
VBUS
DM
DP
VSSUS USB0_ VSSUS VSSUS
L2
B
VDD1V
VPGM
2K
PD_BG PD_PO VDD3V VDD3V
L1
VDDC_ VDDPL
PA
AIT_N
E3_N
BAK_IS DBG_T DBG_T DBG_T DBG_T
VDD3V
VDDC_ VDD3V
PA
_0
TEST
B
B
VDD3V VSSAD SAD0_ SAD0_
1_DDR
3_ADC
PLL
C
DIN2
DIN3
DQS_P
DM0
VSS
DDR0_
DQS_N
0
DQ0
DQ6
RAS_N
WE_N
BA2
VSS
CA0
3_ADC
C
DIN0
DIN1
VSS
VSS
VSS
VSS
DDR0_ DDR0_ DDR0_ DDR0_ DDR0_ DDR0_ DDR0_ DDR0_ DDR0_ DDR0_
0
VSS
AT28
EB0_A EB0_D
8_3V3
VDDC_ VDD1V VDD1V
VSS
DQ2
DQ4
CAS_N
ODT
BA0
DDR0_ DDR0_ DDR0_ DDR0_ DDR0_
DQ3
DQ5
CS_N
CA15
CA8
CA3
DDR0_
RESET
_N
CA2
CA9
CA13
DDR0_ DDR0_ DDR0_
CA5
CA7
BA1
VSS
VSS
DDR0_ DDR0_ DDR0_ DDR0_ DDR0_ DDR0_ DDR0_ DDR0_ DDR0_ DDR0_
DQ1
Figure 3.1
2016-07-19
15
VDD3V VSSAD SAD0_ SAD0_
DDR0_
VSS
DDR0_
DQS_P
DDR0_
DQ10
1
VSS
AT9
DDR0_ DDR0_ DDR0_ DDR0_ DDR0_ DDR0_ DDR0_ DDR0_
DQ12
DDR0_
VSS
AT5
2C
EL4
_12
DDR0_
AT1
VDD3V
I2C0_S GPIO0
VSS
DD23
DD20
_SD0
IO0
DA
DD15
VDD1V
CS0_N CS1_N
N
EL1
DD10
_3V3_E
BOOTS BOOTS BOOTS BOOTS BOOTS
EL0
DD24
VDD1V8 VDD1V8 VDD1V VDD1V VDD3V VDD3V
SPIB0_ SPIB0_
IO3
14
_1
GPIO0 SPIB0_ SPIB0_ SPIB0_
BOOTS UA0_R UA0_T GPIO0
W
DD0
GPIO0
P
M
L
K
J
H
MD
GPIO0
13
EB0_C EB0_A EB0_A EB0_A EB0_A EB0_A EB0_A EB0_A EB0_D EB0_D EB0_D EB0_D EB0_D EB0_D EB0_D EB0_W
AT0
AT1
12
EB0_A EB0_A EB0_A
DD8
SD0_D SD0_C SD0_C SD0_C GPIO0
AT2
11
EB0_C EB0_O EB0_A EB0_A EB0_A EB0_A EB0_A EB0_D EB0_D EB0_D EB0_D EB0_D EB0_D EB0_D EB0_D EB0_D
SD0_D SD0_D SD0_D EB0_C EB0_A EB0_A EB0_A EB0_A EB0_A
AT3
10
EB0_C EB0_C EB0_A EB0_A EB0_A EB0_A EB0_A EB0_D EB0_D EB0_D EB0_D EB0_D EB0_D EB0_D EB0_D
E
7
5
F
3
4
G
D
2
EMMC
DQ7
CKE
CA10
CA6
CA11
CA14
CA4
CA1
CA12
DDR0_
CK_P
DDR0_
CK_N
VSS
VSS
VSS
VSS
Pin alignment of this product
15 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
3.2. Pin List (Ball number order)
Table 3.1 shows a pin list.
Table 3.1 Pin List (Ball number order)
Ball
Number
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
C1
C2
C3
C4
2016-07-19
Pin name
VSS
EMMC0_DAT0
EMMC0_DAT4
EB0_CE3_N
EB0_CLKO
EB0_ADD2
EB0_ADD11
EB0_ADD14
EB0_ADD19
EB0_ADD24
EB0_DAT1
EB0_DAT5
EB0_DAT9
EB0_DAT10
EB0_DAT11
EB0_DAT13
EB0_DAT14
EB0_DAT15
VSS
EMMC0_CLK
EMMC0_DAT1
EMMC0_DAT5
EB0_CE2_N
EB0_OE_N
EB0_ADD3
EB0_ADD9
EB0_ADD13
EB0_ADD18
EB0_ADD23
EB0_DAT0
EB0_DAT4
EB0_DAT8
EB0_DAT12
EB0_DAT16
EB0_DAT18
EB0_DAT19
EB0_DAT20
EB0_DAT22
EMMC0_CLKB
EMMC0_DAT2
EMMC0_DAT6
EB0_CE1_N
Power supply
of pin
—
VDD1V8_3V3_EMMC
VDD1V8_3V3_EMMC
VDD1V8_3V3_SD1
VDD1V8_3V3_SD1
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
—
VDD1V8_3V3_EMMC
VDD1V8_3V3_EMMC
VDD1V8_3V3_EMMC
VDD1V8_3V3_SD1
VDD1V8_3V3_SD1
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD1V8_3V3_EMMC
VDD1V8_3V3_EMMC
VDD1V8_3V3_EMMC
VDD1V8_3V3_SD1
Ball
Number
C6
C7
C9
C10
C11
C13
C14
C15
C16
C17
C18
C19
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
E1
E2
E3
E4
E5
E6
E7
E8
E9
E11
E12
16 / 64
1/4
Pin Name
EB0_ADD4
EB0_ADD8
EB0_ADD17
EB0_ADD22
EB0_AVD_N
EB0_DAT6
EB0_DAT17
EB0_DAT23
EB0_DAT24
EB0_DAT25
EB0_DAT26
EB0_DAT27
EMMC0_CMD
EMMC0_DAT3
EMMC0_DAT7
EB0_CE0_N
EB0_ADD1
EB0_ADD6
EB0_ADD7
EB0_ADD12
EB0_ADD16
EB0_ADD21
EB0_ADD26
EB0_DAT3
EB0_DAT7
EB0_DAT21
EB0_DAT28
EB0_DAT30
EB0_DAT29
EB0_DAT31
EB0_WE_N
SD0_DAT3
SD0_DAT2
SD0_DAT1
EB0_CLKI
EB0_ADD0
EB0_ADD5
EB0_ADD10
EB0_ADD15
EB0_ADD20
EB0_ADD25
EB0_DAT2
Power supply
of pin
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD1V8_3V3_EMMC
VDD1V8_3V3_EMMC
VDD1V8_3V3_EMMC
VDD1V8_3V3_SD1
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD1V8_3V3_SD0
VDD1V8_3V3_SD0
VDD1V8_3V3_SD0
VDD1V8_3V3_SD1
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
Rev. 1.6
TZ2100 Series
Technical Data Sheet
Table 3.1 Pin List (Ball number order) 2/4
E15
E16
E18
EB0_BE2_N
EB0_BE0_N
EB0_BE1_N
E19
EB0_BE3_N
Power supply
Ball
Number
of pin
VDD3V3_PL_EBUS H15
VDD3V3_PL_EBUS H16
VDD3V3_PL_EBUS H18
VDD3V3_PL_EBUS
H19
F1
F2
F3
F4
F5
SD0_DAT0
SD0_CMD
SD0_CLKB
SD0_CLK
GPIO0_15
VDD1V8_3V3_SD0
VDD1V8_3V3_SD0
VDD1V8_3V3_SD0
VDD1V8_3V3_SD0
VDD3V3_PL_I2C
F15
GPIO1_1
VDD3V3_PL_EBUS J7
F16
F17
F18
F19
G1
G2
G3
G4
G5
GPIO1_0
EB0_WAIT_N
XIN_32K
XOUT_32K
GPIO0_16
GPIO0_17
GPIO0_19
GPIO0_20
GPIO0_18
VDD1V8_3V3_EMM
C
VDD1V8_3V3_EMM
C
VDD1V8_3V3_SD1
VDD1V8_3V3_SD1
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PB
BAK_ISOEN_N
DBG_TRST_N
DBG_TMS
DBG_TDI
DBG_TDO
GPIO0_21
GPIO0_22
GPIO0_24
GPIO0_23
VDD1V8_3V3_SD0
VSS
VDDC_PA
VSS
VDDC_PA
VSS
VDD3V3_PB
VDD3V3_PL_EBUS
VDD3V3_PL_EBUS
VDD3V3_PB
VDD3V3_PB
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
—
Ball
Pin Name
Number
G7
G8
G9
G10
G11
G12
G13
G15
G16
G17
G18
G19
H1
H2
H4
H5
H7
H8
H9
H10
H11
H12
H13
2016-07-19
—
—
—
—
—
—
VDD3V3_PB
VDD3V3_PA
VDD3V3_PA
VDD3V3_PA
VDD3V3_PA
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
—
—
—
—
—
—
—
Pin Name
Power supply
of pin
VDD3V3_PA
VDD3V3_PA
VDD3V3_PA
J8
J9
J10
J11
J12
J13
J15
J16
J17
DBG_TCK
LOWPWR
SYS_WAKEUP
WDT_RSTOUT_
N
GPIO0_25
GPIO0_26
GPIO0_27
GPIO0_29
GPIO0_28
VDD1V8_3V3_S
D0
VDDC_PA
VSS
VSS
VSS
VDDC_PA
VDD3V3_PA
SYS_RESET_N
DBG_SRST_N
VSS
J18
GPIO0_2
VDD3V3_PA
J19
GPIO0_1
VDD3V3_PA
K1
K2
K3
K4
K5
K7
K8
K9
K10
K11
K12
K13
K15
K16
K17
K18
K19
L1
L2
L4
L5
GPIO0_30
GPIO0_31
SPIB0_CLK
SPIB0_IO1
SPIB0_IO0
VDD3V3_PL_I2C
VSS
VSS
VSS
VSS
VSS
VDD3V3_PA
GPIO0_3
GPIO0_0
POR_OUT_N
XIN
XOUT
SPIB0_IO2
SPIB0_IO3
SPIB0_CS0_N
SPIB0_CS1_N
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
—
—
—
—
—
—
—
VDD3V3_PA
VDD3V3_PA
VDD3V3_PA
VDD3V3_PA
VDD3V3_PA
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
J1
J2
J3
J4
J5
17 / 64
VDD3V3_PA
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
—
—
—
—
—
—
—
VDD3V3_PA
VDD3V3_PA
—
Rev. 1.6
TZ2100 Series
Technical Data Sheet
Table 3.1 Pin List (Ball number order) 3/4
Ball
Number
L7
L8
L9
L10
L11
L12
L13
L16
L17
L18
L19
M1
M2
M3
M4
M5
M7
M8
M9
M10
M11
M12
M13
M15
M16
M17
M18
M19
N1
N2
N3
N4
N5
N7
N8
N9
N10
N11
N12
N13
N16
N17
2016-07-19
Pin Name
VDD3V3_PL_I2C
VDDC_PA
VSS
VSS
VSS
VDDC_PA
VDDPLL1
PD_BGR33
PD_POR33
VDD3V3_USB
VDD3V3_USB
BOOTSEL0
BOOTSEL1
BOOTSEL2
BOOTSEL3
BOOTSEL4
VDDC_PA
VSS
VDDC_PA
VSS
VDDC_PA
VSS
VDDPLL0
USB0_REXT
USB0_CLK
USB0_VBUS
USB0_DM
USB0_DP
BOOTSEL5
UA0_RXD
UA0_TXD
GPIO0_10
GPIO0_11
VSS
VDDC_PA
VDD1V1_DDR
VDD1V1_DDR
VSS
VDDC_PA
VDDPLL2
VSSUSB
USB0_TEST
Power supply
of pin
—
—
—
—
—
—
—
—
—
—
—
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
—
—
—
—
—
—
—
VDD3V3_USB
VDD3V3_USB
VDD3V3_USB
VDD3V3_USB
VDD3V3_USB
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
—
—
—
—
—
—
—
—
VDD3V3_USB
Ball
Number
N18
N19
P1
P2
P4
P5
P7
P8
P9
P10
P11
P12
P13
P16
P17
P18
P19
R1
R2
R3
R4
R5
R16
R17
R18
R19
T1
T2
T3
T4
T6
T7
T8
T9
T10
T11
T12
T13
T15
T16
T17
T18
18 / 64
Pin Name
VSSUSB
VSSUSB
GPIO0_13
GPIO0_14
I2C0_SDA
GPIO0_12
DDR0_VREF
VSS
VDD_DDRIO
VDD_DDRIO
DDR0_ZQ
VPGM
VDD1V1_DDRPLL
VDD3V3_ADC
VSSADC
SAD0_DIN2
SAD0_DIN3
I2C0_SCL
GPIO0_4
GPIO0_5
GPIO0_6
GPIO0_7
VDD3V3_ADC
VSSADC
SAD0_DIN0
SAD0_DIN1
GPIO0_8
GPIO0_9
VSS
DDR0_DQ12
DDR0_DQ10
DDR0_DQ8
DDR0_DQ0
DDR0_DQ6
DDR0_RAS_N
DDR0_WE_N
DDR0_BA2
DDR0_CA0
VSS
VSS
VSS
VSS
Power supply
of pin
—
—
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD_DDRIO
—
—
—
VDD_DDRIO
—
—
—
—
VDD3V3_ADC
VDD3V3_ADC
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
VDD3V3_PL_I2C
—
—
VDD3V3_ADC
VDD3V3_ADC
VDD3V3_PL_I2C
VDD3V3_PL_I2C
—
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
—
—
—
—
Rev. 1.6
TZ2100 Series
Technical Data Sheet
Table 3.1 Pin List (Ball number order) 4/4
Ball
Pin Name
Number
T19
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
V1
V2
V3
V4
V5
V6
V7
V8
V9
VSS
DDR0_DQ11
VSS
DDR0_DM1
VSS
DDR0_DQ14
VSS
DDR0_DM0
DDR0_DQ2
DDR0_DQ4
DDR0_CAS_N
DDR0_ODT
DDR0_BA0
DDR0_CA3
DDR0_CA2
DDR0_CA9
DDR0_CA13
VSS
DDR0_CK_P
VSS
DDR0_DQ13
DDR0_DQ15
VSS
DDR0_DQS_N1
VSS
DDR0_DQS_P0
VSS
DDR0_DQ3
DDR0_DQ5
2016-07-19
Power supply
of pin
—
VDD_DDRIO
—
VDD_DDRIO
—
VDD_DDRIO
—
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
—
VDD_DDRIO
—
VDD_DDRIO
VDD_DDRIO
—
VDD_DDRIO
—
VDD_DDRIO
—
VDD_DDRIO
VDD_DDRIO
Ball
Number
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
19 / 64
Pin Name
DDR0_CS_N
DDR0_CA15
DDR0_CA8
DDR0_RESET_N
DDR0_CA5
DDR0_CA7
DDR0_BA1
VSS
DDR0_CK_N
VSS
VSS
DDR0_DQ9
VSS
DDR0_DQS_P1
VSS
DDR0_DQS_N0
VSS
DDR0_DQ1
DDR0_DQ7
DDR0_CKE
DDR0_CA10
DDR0_CA6
DDR0_CA11
DDR0_CA14
DDR0_CA4
DDR0_CA1
DDR0_CA12
VSS
VSS
Power supply
of pin
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
—
VDD_DDRIO
—
—
VDD_DDRIO
—
VDD_DDRIO
—
VDD_DDRIO
—
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
VDD_DDRIO
—
—
Rev. 1.6
TZ2100 Series
Technical Data Sheet
3.3. Signal description (in order of pin function)
Some of pins are assigned multiple functions with this product. To define a function on a pin, setting appropriate
pin configuration registers is required after booting up this product. The setting needs to be done with care since
some of the configuration bits may affect multiple different pins in one bit at once.
IDX
Index by
each
function
Signal
Signal name
In / Out
Description
IO's direction Description
or attribute
of signal
Pin share
"yes" means that multiple functions are
signed to this pin
According to the above table, tables shown in 3.3.1 or afterwards show signal descriptions by function group. The
input/output columns may describe "Analog," "Power" and "GND."
Clock Sources and Reset
IDX
Signal name
In / Out
1
XIN
In
2
XOUT
3
XIN_32K
In
4
XOUT_32K
IO
5
6
7
8
9
10
11
SYS_RESET_N
POR_OUT_N
WDT_RSTOUT_N
BAK_ISOEN_N
DBG_SRST_N
SYS_WAKEUP
LOWPWR
In
Out
Out
In
In
In
Out
Out
Description
Resonator input for the system clock (24 MHz)
Oscillator Input for the system clock (24 MHz)
Resonator output for the system clock (24 MHz)
Resonator input for the RTC (32.768 kHz)
Resonator output for the RTC (32.768 kHz)
Oscillator Input for the RTC (32.768 kHz)
System reset input
Power on reset output
Watch dog timer reset output
Backup power domain enable input
CPU (without debug resource) system reset input
Wake up interrupt input
Low power enable output
DDR3/DDR3L Memory Interface
IDX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Signal name
DDR0_CK_P
DDR0_CK_N
DDR0_CKE
DDR0_CA15
DDR0_CA14
DDR0_CA13
DDR0_CA12
DDR0_CA11
DDR0_CA10
DDR0_CA9
DDR0_CA8
DDR0_CA7
DDR0_CA6
DDR0_CA5
DDR0_CA4
DDR0_CA3
DDR0_CA2
DDR0_CA1
2016-07-19
In / out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Description
DDR3/DDR3L differential clock output (plus)
DDR3/DDR3L differential clock output (minus)
DDR3/DDR3L clock enable
DDR3/DDR3L address 15
DDR3/DDR3L address 14
DDR3/DDR3L address 13
DDR3/DDR3L address 12
DDR3/DDR3L address 11
DDR3/DDR3L address 10
DDR3/DDR3L address 9
DDR3/DDR3L address 8
DDR3/DDR3L address 7
DDR3/DDR3L address 6
DDR3/DDR3L address 5
DDR3/DDR3L address 4
DDR3/DDR3L address 3
DDR3/DDR3L address 2
DDR3/DDR3L address 1
20 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
IDX
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Signal name
DDR0_CA0
DDR0_BA2
DDR0_BA1
DDR0_BA0
DDR0_RAS_N
DDR0_CAS_N
DDR0_DQ15
DDR0_DQ14
DDR0_DQ13
DDR0_DQ12
DDR0_DQ11
DDR0_DQ10
DDR0_DQ9
DDR0_DQ8
DDR0_DQ7
DDR0_DQ6
DDR0_DQ5
DDR0_DQ4
DDR0_DQ3
DDR0_DQ2
DDR0_DQ1
DDR0_DQ0
DDR0_DQS_P1
DDR0_DQS_P0
DDR0_DQS_N1
DDR0_DQS_N0
DDR0_DM1
DDR0_DM0
DDR0_CS_N
DDR0_WE_N
DDR0_VREF
DDR0_ODT
DDR0_RESET_N
DDR0_ZQ
In / out
Out
Out
Out
Out
Out
Out
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Out
Out
Analog
Out
Out
Analog
Description
DDR3/DDR3L address 0
DDR3/DDR3L bank address 2
DDR3/DDR3L bank address 1
DDR3/DDR3L bank address 0
DDR3/DDR3L row address selection signal
DDR3/DDR3L column address selection signal
DDR3/DDR3L data bus 15
DDR3/DDR3L data bus 14
DDR3/DDR3L data bus 13
DDR3/DDR3L data bus 12
DDR3/DDR3L data bus 11
DDR3/DDR3L data bus 10
DDR3/DDR3L data bus 9
DDR3/DDR3L data bus 8
DDR3/DDR3L data bus 7
DDR3/DDR3L data bus 6
DDR3/DDR3L data bus 5
DDR3/DDR3L data bus 4
DDR3/DDR3L data bus 3
DDR3/DDR3L data bus 2
DDR3/DDR3L data bus 1
DDR3/DDR3L data bus 0
DDR3/DDR3L differential data strobe plus 1
DDR3/DDR3L differential data strobe plus 0
DDR3/DDR3L differential data strobe minus 1
DDR3/DDR3L differential data strobe minus 0
DDR3/DDR3L write data byte mask 1
DDR3/DDR3L write data byte mask 0
DDR3/DDR3L chip select
DDR3/DDR3L write enable
DDR3/DDR3L DQ reference voltage
DDR3/DDR3L ODT enable
DDR3/DDR3L reset output
DDR3/DDR3L reference resister input
Connect a bridge terminal resistor (recommended value: 220 Ω) between the DDR0_CK_P and the DDR0_CK_N.
2016-07-19
21 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
SPI Flash Memory Controller Interface
IDX
1
2
3
4
5
6
7
Signal name
SPIB0_CLK
SPIB0_IO0
SPIB0_IO1
SPIB0_IO2
SPIB0_IO3
SPIB0_CS0_N
SPIB0_CS1_N
In / out
Out
IO
IO
IO
IO
Out
Out
Description
SPIB0 clock output
SPIB0 serial data output
SPIB0 serial data input
SPIB0 quad data 2
SPIB0 quad data 3
SPIB0 chip select 0
SPIB0 chip select 1
Pin
share
yes
yes
yes
yes
yes
yes
yes
eMMC / SD card / SDIO Interfaces
IDX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Signal name
SD0_CD
SD0_WP
SD0_V18EN
SD0_POWER
SD0_CLK
SD0_CLKB
SD0_CMD
SD0_DAT0
SD0_DAT1
SD0_DAT2
SD0_DAT3
SD1_CD
SD1_WP
SD1_V18EN
SD1_POWER
SD1_CLK
SD1_CLKB
SD1_CMD
SD1_DAT0
SD1_DAT1
SD1_DAT2
SD1_DAT3
EMMC0_CLK
EMMC0_CLKB
EMMC0_CMD
EMMC0_DAT0
EMMC0_DAT1
EMMC0_DAT2
EMMC0_DAT3
EMMC0_DAT4
EMMC0_DAT5
EMMC0_DAT6
EMMC0_DAT7
2016-07-19
In / out
In
In
Out
Out
Out
In
IO
IO
IO
IO
IO
In
In
Out
Out
Out
In
IO
IO
IO
IO
IO
Out
In
IO
IO
IO
IO
IO
IO
IO
IO
IO
Description
SD0 card detection
SD0 card write protection
SD0 card 1.8 V/3.3 V control
SD0 card power supply voltage control
SD0 clock output
SD0 timing control clock B
SD0 command
SD0 data 0
SD0 data 1
SD0 data 2
SD0 data 3
SD1 card detection
SD1 card write protection
SD1 card 1.8 V/3.3 V control
SD1 card power supply voltage control
SD1 clock output
SD1 timing control clock B
SD1 command
SD1 data 0
SD1 data 1
SD1 data 2
SD1 data 3
eMMC clock output
eMMC timing control clock B
eMMC command
eMMC data 0
eMMC data 1
eMMC data 2
eMMC data 3
eMMC data 4
eMMC data 5
eMMC data 6
eMMC data 7
22 / 64
Pin
share
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Rev. 1.6
TZ2100 Series
Technical Data Sheet
External BUS interface
IDX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Signal name
EB0_ADD26
EB0_ADD25
EB0_ADD24
EB0_ADD23
EB0_ADD22
EB0_ADD21
EB0_ADD20
EB0_ADD19
EB0_ADD18
EB0_ADD17
EB0_ADD16
EB0_ADD15
EB0_ADD14
EB0_ADD13
EB0_ADD12
EB0_ADD11
EB0_ADD10
EB0_ADD9
EB0_ADD8
EB0_ADD7
EB0_ADD6
EB0_ADD5
EB0_ADD4
EB0_ADD3
EB0_ADD2
EB0_ADD1
EB0_ADD0
EB0_DAT31
EB0_DAT30
EB0_DAT29
EB0_DAT28
EB0_DAT27
EB0_DAT26
EB0_DAT25
EB0_DAT24
EB0_DAT23
EB0_DAT22
EB0_DAT21
EB0_DAT20
EB0_DAT19
EB0_DAT18
EB0_DAT17
EB0_DAT16
EB0_DAT15
EB0_DAT14
EB0_DAT13
EB0_DAT12
EB0_DAT11
EB0_DAT10
EB0_DAT9
EB0_DAT8
2016-07-19
In / out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Description
EBUS address 26
EBUS address 25
EBUS address 24
EBUS address 23
EBUS address 22
EBUS address 21
EBUS address 20
EBUS address 19
EBUS address 18
EBUS address 17
EBUS address 16
EBUS address 15
EBUS address 14
EBUS address 13
EBUS address 12
EBUS address 11
EBUS address 10
EBUS address 9
EBUS address 8
EBUS address 7
EBUS address 6
EBUS address 5
EBUS address 4
EBUS address 3
EBUS address 2
EBUS address 1
EBUS address 0
EBUS data 31
EBUS data 30
EBUS data 29
EBUS data 28
EBUS data 27
EBUS data 26
EBUS data 25
EBUS data 24
EBUS data 23
EBUS data 22
EBUS data 21
EBUS data 20
EBUS data 19
EBUS data 18
EBUS data 17
EBUS data 16
EBUS data 15
EBUS data 14
EBUS data 13
EBUS data 12
EBUS data 11
EBUS data 10
EBUS data 9
EBUS data 8
23 / 64
Pin
share
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Rev. 1.6
TZ2100 Series
Technical Data Sheet
IDX
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
Signal name
EB0_DAT7
EB0_DAT6
EB0_DAT5
EB0_DAT4
EB0_DAT3
EB0_DAT2
EB0_DAT1
EB0_DAT0
EB0_CE3_N
EB0_CE2_N
EB0_CE1_N
EB0_CE0_N
EB0_BE3_N
EB0_BE2_N
EB0_BE1_N
EB0_BE0_N
EB0_AVD_N
EB0_WE_N
EB0_OE_N
EB0_WAIT_N
EB0_CLKI
EB0_CLKO
In / out
IO
IO
IO
IO
IO
IO
IO
IO
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
In
In
Out
Description
EBUS data 7
EBUS data 6
EBUS data 5
EBUS data 4
EBUS data 3
EBUS data 2
EBUS data 1
EBUS data 0
EBUS chip enable 3
EBUS chip enable 2
EBUS chip enable 1
EBUS chip enable 0
EBUS byte enable [31:24]
EBUS byte enable [23:16]
EBUS byte enable [15:8]
EBUS byte enable [7:0]
EBUS address validity detection output
EBUS write enable
EBUS output enable
EBUS wait input
EBUS clock input
EBUS clock
Pin
share
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
UART interface
IDX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Signal name
UA0_RXD
UA0_TXD
UA1_RXD
UA1_TXD
UA1_CTS_N
UA1_RTS_N
UA1_EXCLK
UA2_RXD
UA2_TXD
UA2_CTS_N
UA2_RTS_N
UA3_RXD
UA3_TXD
UA3_CTS_N
UA3_RTS_N
2016-07-19
In / out
In
Out
In
Out
In
Out
In
In
Out
In
Out
In
Out
In
Out
Description
UART0 serial data input
UART0 serial data output
UART1 serial data input
UART1 serial data output
UART1 CTS input
UART1 RTS output
UART1 external clock input
UART2 serial data input
UART2 serial data output
UART2 CTS input
UART2 RTS output
UART3 serial data input
UART3 serial data output
UART3 CTS input
UART3 RTS output
24 / 64
Pin
share
—
—
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Rev. 1.6
TZ2100 Series
Technical Data Sheet
I2C bus interface
IDX
1
2
3
4
5
6
7
8
Signal name
I2C0_SDA
I2C0_SCL
I2C1_SDA
I2C1_SCL
I2C2_SDA
I2C2_SCL
I2C3_SDA
I2C3_SCL
Note:
2016-07-19
In / out
IO
IO
IO
IO
IO
IO
IO
IO
Description
I2C0 data
I2C0 clock
I2C1 data
I2C1 clock
I2C2 data
I2C2 clock
I2C3 data
I2C3 clock
Pin
share
—
—
yes
yes
yes
yes
yes
yes
Each pin has open drain type interface.
25 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
SPI Interfaces (for Master Controller)
IDX
1
2
3
4
5
6
7
8
Signal name
SPIM0_CLK
SPIM0_DI
SPIM0_DO
SPIM0_CS_N
SPIM1_CLK
SPIM1_DI
SPIM1_DO
SPIM1_CS_N
Note:
In / out
Out
In
Out
Out
Out
In
Out
Out
Description
SPIM0 clock output
SPIM0 serial data input
SPIM0 serial data output
SPIM0 chip select
SPIM1 clock output
SPIM1 serial data input
SPIM1 serial data output
SPIM1 chip select
Pin
share
yes
yes
yes
yes
yes
yes
yes
yes
The SPIM0 and the SPITX0 can NOT be used at the same time in an application, the SPIM1 and the
SPITX1 can NOT be used at the same time, too.
SPI Interfaces (Dedicated for Transmission)
IDX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Signal name
SPITX0_CLK
SPITX0_DO
SPITX0_CS_N
SPITX1_CLK
SPITX1_DO
SPITX1_CS_N
SPITX2_CLK
SPITX2_DO
SPITX2_CS_N
SPITX3_CLK
SPITX3_DO
SPITX3_CS_N
SPITX4_CLK
SPITX4_DO
SPITX4_CS_N
SPITX5_CLK
SPITX5_DO
SPITX5_CS_N
SPITX6_CLK
SPITX6_DO
SPITX6_CS_N
Note:
2016-07-19
In / out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Description
SPITX0 clock output
SPITX0 data output
SPITX0 chip select
SPITX1 clock output
SPITX1 data output
SPITX1 chip select
SPITX2 clock output
SPITX2 data output
SPITX2 chip select
SPITX3 clock output
SPITX3 data output
SPITX3 chip select
SPITX4 clock output
SPITX4 data output
SPITX4 chip select
SPITX5 clock output
SPITX5 data output
SPITX5 chip select
SPITX6 clock output
SPITX6 data output
SPITX6 chip select
Pin
share
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
The SPIM0 and the SPITX0 can NOT be used at the same time in an application. The SPIM1 and the
SPITX1 can NOT be used at the same time, too.
26 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
SPI Interface (for Slave Controller)
IDX
Signal name
1
2
3
4
SPIS0_CLK
SPIS0_DI
SPIS0_DO
SPIS0_CS_N
Note:
In / out
In
In
Out
In
Description
SPIS0 clock input
SPIS0 serial data input
SPIS0 serial data output
SPIS0 chip select
Pin
share
yes
yes
yes
yes
Select one of pin combinations J5/J3/K1/J4 or H1/G3/G4/H2 in an application.
USB2.0 Host or Device Interface
IDX
1
2
3
4
Signal name
USB0_DP
USB0_DM
USB0_REXT
USB0_VBUS
5
USB0_CLK
6
USB0_TEST
Note 1:
In / out
IO
IO
Analog
Analog
In
Analog
Description
USB port I/O data (DP)
USB port I/O data (DM)
to connect an external resister (Note 1)
VBUS voltage detection (for device mode)
Input to the clock generator for USB (12 MHz)
* option for external oscillator connection
Test pin
Connect to GND with 174 Ω (±1%) resistor.
Ethernet MAC Interface
IDX Signal name
1
2
3
4
5
6
7
8
9
ETH0_TXD0
ETH0_TXD1
ETH0_TXEN
ETH0_RXD0
ETH0_RXD1
ETH0_CRSDV
ETH0_MDC
ETH0_MDIO
ETH0_REFCLK
2016-07-19
In / out
Out
Out
Out
In
In
In
Out
IO
In
Description
Ethernet RMII transmission data 0
Ethernet RMII transmission data 1
Ethernet RMII transmission enable
Ethernet RMII receiving data 0
Ethernet RMII receiving data 1
Ethernet RMII carrier sense / receiving data valid
Ethernet management data clock
Ethernet management data I/O
Ethernet RMII reference clock
27 / 64
Pin
share
yes
yes
yes
yes
yes
yes
yes
yes
yes
Rev. 1.6
TZ2100 Series
Technical Data Sheet
Camera Input
IDX
1
2
3
4
5
6
7
8
9
10
11
Signal name
CAM0_CLK
CAM0_VSYNC
CAM0_HSYNC
CAM0_DATA0
CAM0_DATA1
CAM0_DATA2
CAM0_DATA3
CAM0_DATA4
CAM0_DATA5
CAM0_DATA6
CAM0_DATA7
In / out
In
In
In
In
In
In
In
In
In
In
In
Description
Input for clock from camera sensor
Input for vertical synch
Input for data enable or horizontal synch
Camera Input data 0
Camera Input data 1
Camera Input data 2
Camera Input data 3
Camera Input data 4
Camera Input data 5
Camera Input data 6
Camera Input data 7
Pin
share
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Display Output
IDX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Signal name
LCD0_RD0
LCD0_RD1
LCD0_RD2
LCD0_RD3
LCD0_RD4
LCD0_RD5
LCD0_RD6
LCD0_RD7
LCD0_GD0
LCD0_GD1
LCD0_GD2
LCD0_GD3
LCD0_GD4
LCD0_GD5
LCD0_GD6
LCD0_GD7
LCD0_BD0
LCD0_BD1
LCD0_BD2
LCD0_BD3
LCD0_BD4
LCD0_BD5
LCD0_BD6
LCD0_BD7
LCD0_HSYNC
LCD0_VSYNC
LCD0_VALID
LCD0_CLK
2016-07-19
In / out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Description
LCD_R_Data0 output
LCD_R_Data1 output
LCD_R_Data2 output
LCD_R_Data3 output
LCD_R_Data4 output
LCD_R_Data5 output
LCD_R_Data6 output
LCD_R_Data7 output
LCD_G_Data0 output
LCD_G_Data1 output
LCD_G_Data2 output
LCD_G_Data3 output
LCD_G_Data4 output
LCD_G_Data5 output
LCD_G_Data6 output
LCD_G_Data7 output
LCD_B_Data0 output
LCD_B_Data1 output
LCD_B_Data2 output
LCD_B_Data3 output
LCD_B_Data4 output
LCD_B_Data5 output
LCD_B_Data6 output
LCD_B_Data7 output
LCD_HSYNC output
LCD_VSYNC output
LCD_VALID output
LCD clock output
28 / 64
Pin
share
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Rev. 1.6
TZ2100 Series
Technical Data Sheet
Audio Interface
IDX
1
2
3
4
5
6
7
8
9
Signal name
I2S_MCKI
I2S_MCKO
I2S0_BCK
I2S0_LRCK
I2S0_DO
I2S1_BCK
I2S1_LRCK
I2S1_DO
I2S1_DI
In / out
In
Out
IO
IO
Out
IO
IO
Out
In
Description
Audio master clock input
Audio master clock output
I2S0 audio serial clock
I2S0 audio L/R clock
I2S0 audio serial data output
I2S1 audio serial clock
I2S1 audio L/R clock
I2S1 audio serial data output
I2S1 audio serial data input
Pin
share
yes
yes
yes
yes
yes
yes
yes
yes
yes
PWM Output
IDX
1
2
3
4
5
6
Signal name
PWM0_OUT0
PWM0_OUT1
PWM0_OUT2
PWM0_OUT3
PWM0_OUT4
PWM0_OUT5
In / out
Out
Out
Out
Out
Out
Out
Description
PWM output 0
PWM output 1
PWM output 2
PWM output 3
PWM output 4
PWM output 5
Pin
share
yes
yes
yes
yes
yes
yes
Parallel Port Input Interface
IDX
1
2
3
4
5
6
7
8
9
10
11
Signal name
PPI0_DI0
PPI0_DI1
PPI0_DI2
PPI0_DI3
PPI0_DI4
PPI0_DI5
PPI0_DI6
PPI0_DI7
PPI0_STB_N
PPI0_ACK
PPI0_WBUSY
2016-07-19
In / out
In
In
In
In
In
In
In
In
In
Out
Out
Description
Parallel data input 0
Parallel data input 1
Parallel data input 2
Parallel data input 3
Parallel data input 4
Parallel data input 5
Parallel data input 6
Parallel data input 7
Strobe input for parallel data input
Acknowledge output for parallel data input
Output of receive FIFO status
29 / 64
Pin
share
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Rev. 1.6
TZ2100 Series
Technical Data Sheet
GPIO Interfaces
IDX
Signal name
In / out
1
GPIO0_0
IO
2
GPIO0_1
IO
3
GPIO0_2
IO
4
GPIO0_3
IO
5
GPIO0_4
IO
6
GPIO0_5
IO
7
GPIO0_6
IO
8
GPIO0_7
IO
9
GPIO0_8
IO
10
GPIO0_9
IO
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
GPIO0_10
GPIO0_11
GPIO0_12
GPIO0_13
GPIO0_14
GPIO0_15
GPIO0_16
GPIO0_17
GPIO0_18
GPIO0_19
GPIO0_20
GPIO0_21
GPIO0_22
GPIO0_23
GPIO0_24
GPIO0_25
GPIO0_26
GPIO0_27
GPIO0_28
GPIO0_29
GPIO0_30
GPIO0_31
GPIO1_0
GPIO1_1
GPIO1_2
GPIO1_3
GPIO1_4
GPIO1_5
GPIO1_6
GPIO1_7
GPIO1_8
GPIO1_9
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
2016-07-19
Description
Programmable I/O 0
Note: The I/O power supply is VDD3V3_PA.
Programmable I/O 1
Note: The I/O power supply is VDD3V3_PA.
Programmable I/O 2
Note: The I/O power supply is VDD3V3_PA.
Programmable I/O 3
Note: The I/O power supply is VDD3V3_PA.
Programmable I/O 4
Note: Open drain type I/O
Programmable I/O 5
Note: Open drain type I/O
Programmable I/O 6
Note: Open drain type I/O
Programmable I/O 7
Note: Open drain type I/O
Programmable I/O 8
Note: Open drain type I/O
Programmable I/O 9
Note: Open drain type I/O
Programmable I/O 10
Programmable I/O 11
Programmable I/O 12
Programmable I/O 13
Programmable I/O 14
Programmable I/O 15
Programmable I/O 16
Programmable I/O 17
Programmable I/O 18
Programmable I/O 19
Programmable I/O 20
Programmable I/O 21
Programmable I/O 22
Programmable I/O 23
Programmable I/O 24
Programmable I/O 25
Programmable I/O 26
Programmable I/O 27
Programmable I/O 28
Programmable I/O 29
Programmable I/O 30
Programmable I/O 31
Programmable I/O 32
Programmable I/O 33
Programmable I/O 34
Programmable I/O 35
Programmable I/O 36
Programmable I/O 37
Programmable I/O 38
Programmable I/O 39
Programmable I/O 40
Programmable I/O 41
30 / 64
Pin
share
—
—
—
—
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Rev. 1.6
TZ2100 Series
Technical Data Sheet
IDX
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
Signal name
GPIO1_10
GPIO1_11
GPIO1_12
GPIO1_13
GPIO1_14
GPIO1_15
GPIO1_16
GPIO1_17
GPIO1_18
GPIO1_19
GPIO1_20
GPIO1_21
GPIO1_22
GPIO1_23
GPIO1_24
GPIO1_25
GPIO1_26
GPIO1_27
GPIO1_28
GPIO1_29
GPIO1_30
GPIO1_31
GPIO2_0
GPIO2_1
GPIO2_2
GPIO2_3
GPIO2_4
GPIO2_5
GPIO2_6
GPIO2_7
GPIO2_8
GPIO2_9
GPIO2_10
GPIO2_11
GPIO2_12
GPIO2_13
GPIO2_14
GPIO2_15
GPIO2_16
GPIO2_17
GPIO2_18
GPIO2_19
GPIO2_20
GPIO2_21
GPIO2_22
GPIO2_23
GPIO2_24
GPIO2_25
GPIO2_26
GPIO2_27
GPIO2_28
GPIO2_29
GPIO2_30
GPIO2_31
GPIO3_0
2016-07-19
In / out
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Description
Programmable I/O 42
Programmable I/O 43
Programmable I/O 44
Programmable I/O 45
Programmable I/O 46
Programmable I/O 47
Programmable I/O 48
Programmable I/O 49
Programmable I/O 50
Programmable I/O 51
Programmable I/O 52
Programmable I/O 53
Programmable I/O 54
Programmable I/O 55
Programmable I/O 56
Programmable I/O 57
Programmable I/O 58
Programmable I/O 59
Programmable I/O 60
Programmable I/O 61
Programmable I/O 62
Programmable I/O 63
Programmable I/O 64
Programmable I/O 65
Programmable I/O 66
Programmable I/O 67
Programmable I/O 68
Programmable I/O 69
Programmable I/O 70
Programmable I/O 71
Programmable I/O 72
Programmable I/O 73
Programmable I/O 74
Programmable I/O 75
Programmable I/O 76
Programmable I/O 77
Programmable I/O 78
Programmable I/O 79
Programmable I/O 80
Programmable I/O 81
Programmable I/O 82
Programmable I/O 83
Programmable I/O 84
Programmable I/O 85
Programmable I/O 86
Programmable I/O 87
Programmable I/O 88
Programmable I/O 89
Programmable I/O 90
Programmable I/O 91
Programmable I/O 92
Programmable I/O 93
Programmable I/O 94
Programmable I/O 95
Programmable I/O 96
31 / 64
Pin
share
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Rev. 1.6
TZ2100 Series
Technical Data Sheet
IDX
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Signal name
GPIO3_1
GPIO3_2
GPIO3_3
GPIO3_4
GPIO3_5
GPIO3_6
GPIO3_7
GPIO3_8
GPIO3_9
GPIO3_10
GPIO3_11
GPIO3_12
GPIO3_13
GPIO3_14
GPIO3_15
GPIO3_16
GPIO3_17
GPIO3_18
GPIO3_19
GPIO3_20
GPIO3_21
GPIO3_22
GPIO3_23
GPIO3_24
GPIO3_25
GPIO3_26
GPIO3_27
GPIO3_28
GPIO3_29
GPIO3_30
GPIO3_31
2016-07-19
In / out
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Description
Programmable I/O 97
Programmable I/O 98
Programmable I/O 99
Programmable I/O 100
Programmable I/O 101
Programmable I/O 102
Programmable I/O 103
Programmable I/O 104
Programmable I/O 105
Programmable I/O 106
Programmable I/O 107
Programmable I/O 108
Programmable I/O 109
Programmable I/O 110
Programmable I/O 111
Programmable I/O 112
Programmable I/O 113
Programmable I/O 114
Programmable I/O 115
Programmable I/O 116
Programmable I/O 117
Programmable I/O 118
Programmable I/O 119
Programmable I/O 120
Programmable I/O 121
Programmable I/O 122
Programmable I/O 123
Programmable I/O 124
Programmable I/O 125
Programmable I/O 126
Programmable I/O 127
32 / 64
Pin
share
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Rev. 1.6
TZ2100 Series
Technical Data Sheet
AD Converter Input
IDX
1
2
3
4
Signal name
SAD0_DIN0
SAD0_DIN1
SAD0_DIN2
SAD0_DIN3
Note:
In / out
In
In
In
In
Description
Successive AD converter input 0
Successive AD converter input 1
Successive AD converter input 2
Successive AD converter input 3
100 Ω or less drive impedance is recommended for a signal to be input to each SAD DIN pin.
JTAG interface for debugging
IDX
Signal name
In / out
1
DBG_TCK
In
2
DBG_TDO
Out
3
DBG_TDI
In
4
DBG_TMS
In
5
DBG_TRST_N
In
6
DBG_SRST_N
In
Description
Debug clock input
Clock signal for the debug circuit of the ARM core
Debug data output
Serial data output for the debug circuit of the ARM core
Debug data input
Serial data input for the debug circuit of the ARM core
Debug mode selection
Debug mode select signal for the debug circuit of the ARM
core
Debug reset
Reset input signal for the debug circuit of the ARM core
CPU reset
Reset input signal for the ARM CPU
Others
IDX
Signal name
In / out
1
VPGM
—
2
PD_BGR33
—
3
PD_POR33
—
4
5
6
7
8
9
BOOTSEL0
BOOTSEL1
BOOTSEL2
BOOTSEL3
BOOTSEL4
BOOTSEL5
In
In
In
In
In
In
2016-07-19
Description
Test pin
Connect to the GND
Test pin
Connect to the GND
Test pin
Connect to the GND
Boot mode select input 0
Boot mode select input 1
Boot mode select input 2
Boot mode select input 3
Boot mode select input 4
Boot mode select input 5
33 / 64
Pin
share
—
—
—
yes
yes
yes
yes
yes
yes
Rev. 1.6
TZ2100 Series
Technical Data Sheet
VDDs and VSSs
IDX
2
3
Ball number
H9, H11, J8, J12, L8,
L12, M7, M9, M11, N8,
N12
N9, N10
P13
4
P9, P10
VDD_DDRIO
Power
5
6
7
M13
L13
N13
VDDPLL0
VDDPLL1
VDDPLL2
Power
Power
Power
8
P16, R16
VDD3V3_ADC
Power
9
10
11
12
13
14
15
16
L18, L19
G7, G8
H7, J7
G9, G10
K7, L7
G11, G12
J13, K13
G13, H13
A1, A19, H8, H10, H12,
J9, J10, J11, J17, K8,
K9, K10, K11, K12, L9,
L10, L11, M8, M10,
M12, N7, N11, P8, T3,
T15, T16, T17, T18,
T19, U2,U4,U6,
U17,U19, V3, V5, V7,
V17, V19, W1, W3, W5,
W7, W18, W19
P17, R17
N16, N18, N19
VDD3V3_USB
VDD1V8_3V3_EMMC
VDD1V8_3V3_SD0
VDD1V8_3V3_SD1
VDD3V3_PL_I2C
VDD3V3_PL_EBUS
VDD3V3_PA
VDD3V3_PB
Power
Power
Power
Power
Power
Power
Power
Power
1.1 V DDR digital power supply
1.1 V power supply for DDR PLL
Power supply for DDR3 interface
(when using the DDR3).
1.5 V for DDR3 or 1.35 V for DDR3L
1.1 V power supply for the clock PLL
1.1 V power supply for the clock PLL
1.1 V power supply for the clock PLL
3.3 V power supply for the AD converter
reference voltage
USB 3.3 V power supply
Power supply for EMMC I/O
Power supply for SD0 I/O
Power supply for SD1 I/O
Power supply for I2C I/O
Power supply for EBUS I/O
3.3 V power supply for PA digital I/O
3.3 V power supply for backup
VSS
GND
GND
VSSADC
VSSUSB
GND
GND
ADC analog GND
USB analog GND
1
17
18
19
Note:
2016-07-19
Pin name (note)
Attribute
Description
VDDC_PA
Power
1.1 V power supply for CORE digital
VDD1V1_DDR
VDD1V1_DDRPLL
Power
Power
It is handled as a pin name in this section.
34 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
3.4. Setting Pin Functions
Some of pins are assigned to multiple functions in this product. The functions are switched by setting a register
appropriately after booting up this product.
Setting pin function with Registers
The pin function can be selected after booting up by setting the below pin function configuration control registers
([IO_PIN_SEL*]) in the GCONF module.
Control register
[IO_PIN_SEL0]
[IO_PIN_SEL1]
[IO_PIN_SEL2]
[IO_PIN_SEL3]
[IO_PIN_SEL4]
[IO_PIN_SEL5]
Abbreviation
PINS0
PINS1
PINS2
PINS3
PINS4
PINS5
Address
0x50028600
0x50028604
0x50028608
0x5002860C
0x50028610
0x50028614
The following shows that each bit of the registers [IO_PIN_SEL*] selects a kind of function. After booting up, all
bits of the registers are reset to zero, and the default functions are allocated to pins. Setting 0b1 at the bit of the
registers changes function at the pin. The setting needs to be done with care since some of the configuration bits
may affect multiple pins in one bit at once.
Don't set the plural function of anything but the default assigned to an identical ball at the same time. (The
function which has high priority is chosen by function selection in share pin change setting, and the order of its
priority will be default < function 3 < function 2 < function 1.)
* Basically, share pins set only the used function.
Table 3.2 shows the shared pins switching table.
Table 3.2 Shared Pin Switching Table
Ball
number
M1
M2
M3
M4
M5
N1
E5
D5
A6
B6
C6
E6
D6
D7
C7
B7
E7
A7
D8
B8
A8
E8
D9
C9
B9
A9
E9
D10
Default Signal
name
(Pin name)
BOOTSEL0
BOOTSEL1
BOOTSEL2
BOOTSEL3
BOOTSEL4
BOOTSEL5
EB0_ADD0
EB0_ADD1
EB0_ADD2
EB0_ADD3
EB0_ADD4
EB0_ADD5
EB0_ADD6
EB0_ADD7
EB0_ADD8
EB0_ADD9
EB0_ADD10
EB0_ADD11
EB0_ADD12
EB0_ADD13
EB0_ADD14
EB0_ADD15
EB0_ADD16
EB0_ADD17
EB0_ADD18
EB0_ADD19
EB0_ADD20
EB0_ADD21
2016-07-19
Function 1
Control bit
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Function 2
Signal name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Control bit
PINS4[0]
PINS4[1]
PINS4[2]
PINS4[3]
PINS4[4]
PINS4[5]
PINS3[27]
PINS3[28]
PINS3[29]
PINS3[30]
PINS3[31]
—
—
—
—
—
—
—
—
—
—
PINS4[19]
PINS4[20]
PINS4[21]
PINS4[22]
PINS4[23]
PINS4[24]
PINS4[25]
35 / 64
Signal name
GPIO2_0
GPIO2_1
GPIO2_2
GPIO2_3
GPIO2_4
GPIO2_5
GPIO1_27
GPIO1_28
GPIO1_29
GPIO1_30
GPIO1_31
—
—
—
—
—
—
—
—
—
—
GPIO2_19
GPIO2_20
GPIO2_21
GPIO2_22
GPIO2_23
GPIO2_24
GPIO2_25
Function 3
Control bit
PINS2[0]
PINS2[1]
PINS2[2]
PINS2[3]
PINS2[4]
PINS2[5]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
Signal name
PWM0_OUT0
PWM0_OUT1
PWM0_OUT2
PWM0_OUT3
PWM0_OUT4
PWM0_OUT5
LCD0_CLK
LCD0_VSYNC
LCD0_HSYNC
LCD0_VALID
LCD0_RD0
LCD0_RD1
LCD0_RD2
LCD0_RD3
LCD0_RD4
LCD0_RD5
LCD0_RD6
LCD0_RD7
LCD0_GD0
LCD0_GD1
LCD0_GD2
LCD0_GD3
LCD0_GD4
LCD0_GD5
LCD0_GD6
LCD0_GD7
LCD0_BD0
LCD0_BD1
Rev. 1.6
TZ2100 Series
Technical Data Sheet
Ball
number
C10
B10
A10
E11
D11
C11
B11
A11
E12
D12
B12
A12
C13
D13
B13
A13
A14
A15
B14
A16
A17
A18
B15
C14
B16
B17
B18
D14
B19
C15
C16
C17
C18
C19
D15
D17
D16
D18
D19
B5 *
A5 *
E4 *
D4 *
C4 *
B4 *
A4 *
E16
E18
E15
E19
F17
F16
F15
K3
K5
K4
L1
L2
L4
L5
F4 *
F3 *
F2 *
Default Signal
name
(Pin name)
EB0_ADD22
EB0_ADD23
EB0_ADD24
EB0_ADD25
EB0_ADD26
EB0_AVD_N
EB0_DAT0
EB0_DAT1
EB0_DAT2
EB0_DAT3
EB0_DAT4
EB0_DAT5
EB0_DAT6
EB0_DAT7
EB0_DAT8
EB0_DAT9
EB0_DAT10
EB0_DAT11
EB0_DAT12
EB0_DAT13
EB0_DAT14
EB0_DAT15
EB0_DAT16
EB0_DAT17
EB0_DAT18
EB0_DAT19
EB0_DAT20
EB0_DAT21
EB0_DAT22
EB0_DAT23
EB0_DAT24
EB0_DAT25
EB0_DAT26
EB0_DAT27
EB0_DAT28
EB0_DAT29
EB0_DAT30
EB0_DAT31
EB0_WE_N
EB0_OE_N
EB0_CLKO
EB0_CLKI
EB0_CE0_N
EB0_CE1_N
EB0_CE2_N
EB0_CE3_N
EB0_BE0_N
EB0_BE1_N
EB0_BE2_N
EB0_BE3_N
EB0_WAIT_N
GPIO1_0
GPIO1_1
SPIB0_CLK
SPIB0_IO0
SPIB0_IO1
SPIB0_IO2
SPIB0_IO3
SPIB0_CS0_N
SPIB0_CS1_N
SD0_CLK
SD0_CLKB
SD0_CMD
2016-07-19
Function 1
Control bit
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PINS2[9]
PINS2[9]
PINS2[9]
PINS2[9]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PINS2[9]
PINS2[9]
—
—
PINS2[9]
PINS2[9]
PINS2[9]
PINS0[0]
PINS0[1]
—
PINS0[3]
PINS0[4]
PINS0[2]
PINS0[5]
PINS0[6]
—
PINS0[7]
Function 2
Signal name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ETH0_RXD0
ETH0_RXD1
ETH0_CRSDV
ETH0_MDIO
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ETH0_TXD0
ETH0_TXD1
—
—
ETH0_REFCLK
ETH0_MDC
ETH0_TXEN
SPITX0_CLK
SPITX0_DO
—
SPITX1_CLK
SPITX1_DO
SPITX0_CS_N
SPITX1_CS_N
SPITX2_CLK
—
SPITX2_DO
Control bit
PINS4[26]
PINS4[27]
PINS4[28]
PINS4[29]
PINS4[30]
PINS4[31]
PINS5[0]
PINS5[1]
PINS5[2]
PINS5[3]
PINS5[4]
PINS5[5]
PINS5[6]
PINS5[7]
PINS5[8]
PINS5[9]
PINS5[10]
PINS5[11]
PINS5[12]
PINS5[13]
PINS5[14]
PINS5[15]
PINS5[16]
PINS5[17]
PINS5[18]
PINS5[19]
PINS5[20]
PINS5[21]
PINS5[22]
PINS5[23]
PINS5[24]
PINS5[25]
PINS5[26]
PINS5[27]
PINS5[28]
PINS5[29]
PINS5[30]
PINS5[31]
PINS4[6]
PINS4[7]
PINS4[8]
PINS4[9]
PINS4[10]
PINS4[11]
PINS4[12]
PINS4[13]
PINS4[14]
PINS4[15]
PINS4[16]
PINS4[17]
PINS4[18]
PINS3[0]
PINS3[1]
PINS3[2]
PINS3[3]
PINS3[4]
PINS3[5]
PINS3[6]
PINS3[7]
PINS3[8]
PINS3[9]
PINS3[10]
PINS3[11]
36 / 64
Signal name
GPIO2_26
GPIO2_27
GPIO2_28
GPIO2_29
GPIO2_30
GPIO2_31
GPIO3_0
GPIO3_1
GPIO3_2
GPIO3_3
GPIO3_4
GPIO3_5
GPIO3_6
GPIO3_7
GPIO3_8
GPIO3_9
GPIO3_10
GPIO3_11
GPIO3_12
GPIO3_13
GPIO3_14
GPIO3_15
GPIO3_16
GPIO3_17
GPIO3_18
GPIO3_19
GPIO3_20
GPIO3_21
GPIO3_22
GPIO3_23
GPIO3_24
GPIO3_25
GPIO3_26
GPIO3_27
GPIO3_28
GPIO3_29
GPIO3_30
GPIO3_31
GPIO2_6
GPIO2_7
GPIO2_8
GPIO2_9
GPIO2_10
GPIO2_11
GPIO2_12
GPIO2_13
GPIO2_14
GPIO2_15
GPIO2_16
GPIO2_17
GPIO2_18
GPIO1_0
GPIO1_1
GPIO1_2
GPIO1_3
GPIO1_4
GPIO1_5
GPIO1_6
GPIO1_7
GPIO1_8
GPIO1_9
GPIO1_10
GPIO1_11
Function 3
Control bit
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[7]
PINS2[8]
PINS2[8]
PINS2[8]
PINS2[8]
PINS2[8]
PINS2[8]
PINS2[8]
PINS2[8]
PINS2[8]
PINS2[8]
PINS2[8]
—
—
PINS2[12]
PINS2[13]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PINS2[10]
PINS2[10]
PINS2[10]
PINS2[10]
PINS2[11]
PINS2[11]
PINS2[11]
—
—
—
—
—
PINS2[15]
PINS2[14]
—
—
—
—
—
—
—
—
—
—
Signal name
LCD0_BD2
LCD0_BD3
LCD0_BD4
LCD0_BD5
LCD0_BD6
LCD0_BD7
CAM0_CLK
CAM0_VSYNC
CAM0_HSYNC
CAM0_DATA0
CAM0_DATA1
CAM0_DATA2
CAM0_DATA3
CAM0_DATA4
CAM0_DATA5
CAM0_DATA6
CAM0_DATA7
—
—
SD1_CD
SD1_WP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SD1_CMD
SD1_CLK
SD1_CLKB
SD1_DAT0
SD1_DAT1
SD1_DAT2
SD1_DAT3
—
—
—
—
—
SD1_V18EN
SD1_POWER
—
—
—
—
—
—
—
—
—
—
Rev. 1.6
TZ2100 Series
Technical Data Sheet
Ball
number
F1 *
E3 *
E2 *
E1 *
B1 *
C1 *
D1 *
A2 *
B2 *
C2 *
D2 *
A3 *
B3 *
C3 *
D3 *
R2 **
R3 **
R4 **
R5 **
T1 **
T2 **
N4
N5
P5
P1
P2
F5
G1
G2
G5
G3
G4
H1
H2
H5
H4
J1
J2
J3
J5
J4
K1
K2
Default Signal
name
(Pin name)
SD0_DAT0
SD0_DAT1
SD0_DAT2
SD0_DAT3
EMMC0_CLK
EMMC0_CLKB
EMMC0_CMD
EMMC0_DAT0
EMMC0_DAT1
EMMC0_DAT2
EMMC0_DAT3
EMMC0_DAT4
EMMC0_DAT5
EMMC0_DAT6
EMMC0_DAT7
GPIO0_4
GPIO0_5
GPIO0_6
GPIO0_7
GPIO0_8
GPIO0_9
GPIO0_10
GPIO0_11
GPIO0_12
GPIO0_13
GPIO0_14
GPIO0_15
GPIO0_16
GPIO0_17
GPIO0_18
GPIO0_19
GPIO0_20
GPIO0_21
GPIO0_22
GPIO0_23
GPIO0_24
GPIO0_25
GPIO0_26
GPIO0_27
GPIO0_28
GPIO0_29
GPIO0_30
GPIO0_31
Note:
2016-07-19
Function 1
Control bit
PINS0[8]
PINS0[9]
PINS0[10]
PINS0[11]
PINS0[12]
—
PINS0[13]
PINS0[14]
PINS0[15]
PINS0[16]
PINS0[17]
PINS0[18]
PINS0[19]
PINS0[20]
—
—
—
PINS0[21]
PINS0[21]
PINS0[21]
PINS0[21]
PINS0[21]
PINS0[21]
PINS0[21]
PINS0[21]
PINS0[21]
—
—
—
—
—
—
—
—
—
—
—
—
PINS0[22]
PINS1[25]
PINS1[25]
PINS1[26]
PINS0[23]
Function 2
Signal name
SPITX2_CS_N
SPITX3_CLK
SPITX3_DO
SPITX3_CS_N
SPITX4_CLK
—
SPITX4_DO
SPITX4_CS_N
SPITX5_CLK
SPITX5_DO
SPITX5_CS_N
SPITX6_CLK
SPITX6_DO
SPITX6_CS_N
—
—
—
PPI0_DI0
PPI0_DI1
PPI0_DI2
PPI0_DI3
PPI0_DI4
PPI0_DI5
PPI0_DI6
PPI0_DI7
PPI0_STB_N
—
—
—
—
—
—
—
—
—
—
—
—
PPI0_ACK
SPIS0_CLK
SPIS0_CS_N
SPIS0_DO
PPI0_WBUSY
Control bit
PINS3[12]
PINS3[13]
PINS3[14]
PINS3[15]
PINS3[16]
PINS3[17]
PINS3[18]
PINS3[19]
PINS3[20]
PINS3[21]
PINS3[22]
PINS3[23]
PINS3[24]
PINS3[25]
PINS3[26]
PINS0[25]
PINS0[25]
PINS0[26]
PINS0[26]
PINS0[27]
PINS0[27]
PINS0[28]
PINS0[29]
PINS0[30]
PINS0[30]
PINS0[31]
PINS1[0]
PINS1[1]
PINS1[2]
PINS1[2]
PINS1[4]
PINS1[5]
PINS1[6]
PINS1[6]
PINS1[14]
PINS1[8]
PINS1[8]
PINS1[9]
PINS1[27]
PINS1[11]
PINS1[11]
PINS1[12]
PINS1[13]
Signal name
GPIO1_12
GPIO1_13
GPIO1_14
GPIO1_15
GPIO1_16
GPIO1_17
GPIO1_18
GPIO1_19
GPIO1_20
GPIO1_21
GPIO1_22
GPIO1_23
GPIO1_24
GPIO1_25
GPIO1_26
I2C1_SDA
I2C1_SCL
I2C2_SDA
I2C2_SCL
I2C3_SDA
I2C3_SCL
UA1_RXD
UA1_TXD
UA1_CTS_N
UA1_RTS_N
UA1_EXCLK
UA2_RXD
UA2_TXD
UA2_CTS_N
UA2_RTS_N
UA3_RXD
UA3_TXD
UA3_CTS_N
UA3_RTS_N
I2S_MCKI
I2S0_BCK
I2S0_LRCK
I2S0_DO
SPIS0_DI
I2S1_BCK
I2S1_LRCK
I2S1_DO
I2S1_DI
Function 3
Control bit
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PINS1[18]
PINS1[17]
PINS1[16]
PINS1[16]
PINS1[24]
PINS1[23]
PINS1[22]
PINS1[22]
PINS1[15]
PINS1[19]
PINS1[19]
PINS1[20]
PINS1[31]
PINS1[28]
PINS1[29]
PINS1[30]
PINS1[21]
Signal name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SPIM0_DI
SPIM0_DO
SPIM0_CS_N
SPIM0_CLK
SPIS0_DI
SPIS0_DO
SPIS0_CLK
SPIS0_CS_N
I2S_MCKO
SPIM1_CLK
SPIM1_CS_N
SPIM1_DO
SD0_V18EN
SD0_CD
SD0_WP
SD0_POWER
SPIM1_DI
The pin in which "*" is written in "ball number" is SD-IO structure (3.3 V or 1.8 V interface
bidirectional multi-drive buffer).
The pin in which "**" is written in "ball number, and " the I2C0_SDA pin, and the I2C0_SCL pin are
open drain type structure.
37 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
4. Electrical characteristics
4.1. Absolute Maximum ratings
Item
Supply voltage
Input voltage
Output voltage
Input current
Storage temperature
Note 1:
Symbol
VDDMAX
VINMAX
VOUTMAX
IIN
Tstg
Maximum rating
-0.3 to (VDD+0.3) (Note 1)
-0.3 to (VDD+0.3) (Note 1)
-0.3 to (VDD+0.3) (Note 1)
±10
-40 to 125
Unit
V
V
V
mA
°C
VDD is a supply voltage which is described in operating conditions of next section.
4.2. Recommended Operating Conditions
Operating conditions are divided in three types according to product types.
Operating Conditions of the TZ2100XBG
Item
Symbol (target power
supply pin name)
VDDC_PA
VDDPLL0
VDDPLL1
VDDPLL2
VDD1V1_DDR
VDD1V1_DDRPLL
VDD_DDRIO
VDD3V3_PA
Supply Voltage VDD3V3_PL_EBUS
VDD3V3_PL_I2C
Range
VDD1V8_3V3_SD0
VDD1V8_3V3_SD1
VDD1V8_3V3_EMMC
VDD3V3_USB
VDD3V3_ADC
VDD3V3_PB
Condition
Min
Typ.
Max
Unit
—
—
—
—
—
—
When connected to DDR3
When connected to DDR3L
—
—
—
—
(Note 1)
(Note 2)
(Note 1)
—
(Note 1)
—
—
(Note 4)
—
1.00
1.00
1.00
1.00
1.00
1.00
1.425
1.283
3.00
3.00
3.00
2.70
1.70
2.70
1.70
2.70
1.70
3.15
3.00
3.00
-20
1.10
1.10
1.10
1.10
1.10
1.10
1.50
1.35
3.30
3.30
3.30
3.30
1.80
3.30
1.80
3.30
1.80
3.30
3.30
3.30
—
1.20
1.20
1.20
1.20
1.20
1.20
1.575
1.45
3.60
3.60
3.60
3.60
1.95
3.60
1.95
3.60
1.95
3.45
3.60
3.60
80
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Operating
Temperature
°C
Ta (ambient temperature)
(Note 3)
-40
—
85
Range
Note:
A voltage difference between a minimum voltage and a maximum voltage in group of 1.1 V power
supplies are required to be within 100 mV.
Note 1: When using as a 1.8 V interface mode.
Note 2: When using the VDD1V8_3V3_SD1 as EBUS, apply the same supply voltage as the
VDD3V3_PL_EBUS to the VDD1V8_3V3_SD1. In this case, the minimum operating voltage is 3.0 V.
Note 3: Optional with the extended operating temperature products.
Note 4: The minimum operating voltage is 2.0 V when using SRAM data retention for the buck-up and RTC
operation.
2016-07-19
38 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
Operating Conditions of TZ2102XBG
Symbol (target power
supply pin name)
VDDC_PA
VDDPLL0
VDDPLL1
VDDPLL2
VDD1V1_DDR
VDD1V1_DDRPLL
Item
VDD_DDRIO
VDD3V3_PA
Supply Voltage VDD3V3_PL_EBUS
VDD3V3_PL_I2C
Range
VDD1V8_3V3_SD0
VDD1V8_3V3_SD1
VDD1V8_3V3_EMMC
Operating
Temperature
Range
Note:
Note 1:
Note 2:
Note 3:
2016-07-19
VDD3V3_USB
VDD3V3_ADC
VDD3V3_PB
Ta (ambient temperature)
Condition
Min
Typ.
Max
Unit
—
—
—
—
—
—
When connected to DDR3
When connected to DDR3L
—
—
—
—
(Note 1)
(Note 2)
(Note 1)
—
(Note 1)
—
—
(Note 3)
1.06
1.06
1.06
1.06
1.06
1.06
1.425
1.283
3.00
3.00
3.00
2.70
1.70
2.70
1.70
2.70
1.70
3.15
3.00
3.00
1.135
1.135
1.135
1.135
1.135
1.135
1.50
1.35
3.30
3.30
3.30
3.30
1.80
3.30
1.80
3.30
1.80
3.30
3.30
3.30
1.21
1.21
1.21
1.21
1.21
1.21
1.575
1.45
3.60
3.60
3.60
3.60
1.95
3.60
1.95
3.60
1.95
3.45
3.60
3.60
V
V
V
V
V
V
—
-20
—
80
°C
V
V
V
V
V
V
V
V
V
V
A voltage difference between a minimum voltage and a maximum voltage in group of 1.1 V power
supplies are required to be within 100 mV
When using as a 1.8 V interface mode.
When using the VDD1V8_3V3_SD1 as EBUS, apply the supply voltage same as the
VDD3V3_PL_EBUS to the VDD1V8_3V3_SD1. In this case, the minimum operating voltage is 3.0 V.
The minimum operating voltage is 2.0 V when using SRAM data retention for the buck-up and RTC
operation.
39 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
Operating Conditions of TZ2101XBG/TZ2102XBG (Extended Temperature Products)
Symbol (target power
supply pin name)
VDDC_PA
VDDPLL0
VDDPLL1
VDDPLL2
VDD1V1_DDR
VDD1V1_DDRPLL
Item
VDD_DDRIO
VDD3V3_PA
Supply Voltage VDD3V3_PL_EBUS
VDD3V3_PL_I2C
Range
VDD1V8_3V3_SD0
VDD1V8_3V3_SD1
VDD1V8_3V3_EMMC
Operating
Temperature
Range
Note 1:
Note 2:
Note 3:
2016-07-19
VDD3V3_USB
VDD3V3_ADC
VDD3V3_PB
Ta (ambient temperature)
Condition
Min
Typ.
Max
Unit
—
—
—
—
—
—
When connected to DDR3
When connected to DDR3L
—
—
—
—
(Note 1)
(Note 2)
(Note 1)
—
(Note 1)
—
—
(Note 3)
1.10
1.10
1.10
1.10
1.10
1.10
1.425
1.283
3.00
3.00
3.00
2.70
1.70
2.70
1.70
2.70
1.70
3.15
3.00
2.70
1.15
1.15
1.15
1.15
1.15
1.15
1.50
1.35
3.30
3.30
3.30
3.30
1.80
3.30
1.80
3.30
1.80
3.30
3.30
3.30
1.20
1.20
1.20
1.20
1.20
1.20
1.575
1.45
3.60
3.60
3.60
3.60
1.95
3.60
1.95
3.60
1.95
3.45
3.60
3.60
V
V
V
V
V
V
—
-40
—
85
°C
V
V
V
V
V
V
V
V
V
V
When using as a 1.8 V interface mode.
When using the VDD1V8_3V3_SD1 as EBUS, apply the supply voltage same as the
VDD3V3_PL_EBUS to the VDD1V8_3V3_SD1. In this case, the minimum operating voltage is 3.0 V.
The minimum operating voltage is 2.0 V when using SRAM data retention for the buck-up and RTC
operation.
40 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
4.3. Current Dissipations
Item
Symbol
Measurement of power supply
terminal
VDDC_PA, VDD1V1_DDR
VDDPLL0, VDDPLL1, VDDPLL2,
VDD1V1_DDRPLL
Current dissipation 1
IDDC
Current dissipation 2
IDD_DDR
VDD1V1_DDR, VDD1V1_DDRPLL
Current dissipation 3
IDD_DDRIO
VDD_DDRIO
Current dissipation 4
IDD3V3_PB
VDD3V3_PB
Current dissipation 5
IDD1V8_3V3_SD0
VDD1V8_3V3_SD0
Current dissipation 6
IDD3V3_3V3_SD1
VDD1V8_3V3_SD1
Current dissipation 7
IDD1V8_3V3_EMMC
VDD1V8_3V3_EMMC
Current dissipation 8
IDD3V3_USB
VDD3V3_USB
Note:
Note 1:
Note 2:
Note 3:
Note4 :
Note5 :
2016-07-19
Max
Unit
1.19
(Note 1)
A
74
(Note 2)
95
(Note 2)
10
(Note 3)
24
(Note 4)
24
(Note 4)
50
(Note 4)
35
(Note 5)
mA
mA
µA
mA
mA
mA
mA
The maximum current values are calculated from the maximum value during the execution of the
following software, in addition of each item such as device variation, power supply voltage, package
temperature and internal operation conditions unless otherwise specified.
Application software for demonstration with LCD panel display (made by Toshiba)
Evaluation software for SDRAM (made by Toshiba), when supply voltage of VDD_DDRIO is 1.45 V
Evaluation software for Back-up mode in power state (made by Toshiba). Data backup operating at the
Back up SRAM and RTC operating are carried on this software. A ambient temperature is at 60 °C.
Evaluation software for eMMC or SD Card (made by Toshiba), when supply voltage of VDD1V8_3V3
is 1.95 V.
Evaluation software for USB (made by Toshiba).
41 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
4.4. DC Characteristics
Digital I/O pins
This table is specified Digital I/O pin, NOT included SD-IO type. The field "I/O cell attribute" shows "Open drain
type" for the characteristics of open drain type.
(VDD3V3_PA, VDD3V3_PB, VDD3V3_PL_I2C, VDD3V3_PL_EBUS = 3.0 V to 3.6 V)
Item
Symbol
Low-level input
voltage
VIL
High-level input
voltage
VIH
Low-level input
current
IIL
High-level input
current
IIH
Low-level output
VOL
voltage
High-level output
VOH
voltage
Note:
2016-07-19
I/O cell attribution
Input (without Schmitttrigger)
Input (with Schmitt-trigger)
Input (Open drain)
Input (without Schmitttrigger)
Input (with Schmitt-trigger)
Input (Open drain)
Input (HiZ, PD)
Input (PU)
Input (Open drain)
Input (HiZ, PU)
Input (PD)
Input (Open drain)
Output
Output (Open drain)
Output
Conditions
Min
Max
Unit
—
VSS
0.8
V
—
VSS
VDD × 0.3
V
—
2.0
VDD
V
—
—
VIN = VSS
VIN = VSS
VIN = VSS
VIN = VDD
VIN = VDD
VIN = VDD
IOL = 4 mA
IOL = 8 mA
IOL = 8 mA
IOH = -4 mA
IOH = -8 mA
2.1
VDD × 0.7
-10
-200
-10
-10
10
-10
—
—
—
VDD-0.4
VDD-0.4
VDD
5.5
10
-10
10
10
200
10
0.4
0.4
0.4
—
—
V
V
µA
µA
µA
µA
µA
µA
V
V
V
V
V
HiZ, PD, and PU in the above table respectively indicate high-impedance, with a pull-down resistor,
and with a pill-up resistor. Input direction and output direction can be set to be fixed or programmable
for some I/O. Table 3.2 is described pins of the open drain type structure and the SD-IO structure.
42 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
eMMC/SD Card/SDIO pins
This section describes the pin characteristics the SD-IO type shown in Table 3.2.
(VDD1V8_3V3_EMMC, VDD1V8_3V3_SD0, VDD1V8_3V3_SD1 = 2.7 V to 3.6 V)
Item
Low-level input
voltage
High-level input
voltage
Low-level input
current
High-level input
current
Low-level output
voltage
High-level output
voltage
Symbol
I/O attribution
Conditions
Min
Max
Unit
VIL
Input
—
VSS
VDD × 0.25
V
VIH
Input
—
VDD × 0.625
VDD
V
IIL
Input (when high-impedance)
Input (with pull-up resistor)
VIN = VSS
VIN = VSS
-10
-360
10
-30
µA
µA
IIH
Input
VIN = VDD
-10
10
µA
VOL
Output
IOL = 2 mA
—
VDD × 0.125
V
VOH
Output
IOH = -2 mA
VDD × 0.75
—
V
(VDD1V8_3V3_EMMC, VDD1V8_3V3_SD0, VDD1V8_3V3_SD1 = 1.7 V to 1.95 V)
Item
Low-level input
voltage
High-level input
voltage
Low-level input
current
High-level input
current
Low-level output
voltage
High-level output
voltage
2016-07-19
Symbol
I/O attribution
Conditions
Min
Max
Unit
VIL
Input
—
VSS
0.58
V
VIH
Input
—
1.27
VDD
V
IIL
Input (when high-impedance)
Input (with pull-up resistor)
VIN = VSS
VIN = VSS
-2
-195
2
-18
µA
µA
IIH
Input
VIN = VDD
-2
2
µA
VOL
Output
IOL = 2 mA
—
0.45
V
VOH
Output
IOH = -2 mA
1.40
—
V
43 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
4.5. AC Characteristics
Clock Inputs
Oscillation frequency with a crystal resonator
Item
Oscillator Frequency
Symbol
fOSC24M
Conditions
—
Min
—
Typ.
24
Max
—
Unit
MHz
Conditions
—
Min
—
Typ.
24
Max
—
Unit
MHz
Conditions
—
Min
—
Typ.
32.768
Max
—
Unit
kHz
Min
—
Typ.
32.768
Max
—
Unit
kHz
Tolerance: ±100 ppm
Oscillation frequency with an external oscillator
Item
External Clock Source Frequency
Symbol
fEXT24M
Tolerance: ±100 ppm
Oscillation frequency with a crystal resonator
Item
Oscillator Frequency
Symbol
fOSC32K
Tolerance: ±20 ppm
However, it depends on the accuracy required for the RTC.
Oscillation frequency with an external oscillator
Item
External Clock Source Frequency
Symbol
fEXT32K
Conditions
—
Tolerance: ±20 ppm
However, it depends on the accuracy required for the RTC.
2016-07-19
44 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
DDR3/DDR3L Memory Interface
tCK(=1/fSDCK)
tSDCKL
tSDCKH
DDRCLK
DDRBCLK
tSDASETUP
tSDAHOLD
tSDCSETUP
tSDCHOLD
DDRAD[15:0]
DDRCS_N
DDRRAS_N
DDRCAS_N
DDRWE_N
DDRBA2,1,0
DDRODT
DDRCKE
tSDADQSAC
DDRDQS[1:0]
DDRDQSN[1:0]
tSDWDSETUP
tSDWDHOLD
DDRDQ[15:0]
DDRDQM[1:0]
DDRVREF
Item
Symbol
DDRCLK frequency
DDRCLK clock period
DDRCLK H level width
DDRCLK L level width
fSDCK
tCK
tSDCKH
tSDCKL
tSDASETUP
Address/Command output setup time
tSDCSETUP
tSDAHOLD
Address/Command output hold time
tSDCHOLD
DDRDQS output delay time
tSDADQSAC
Data output setup time
tSDWDSETUP
Data output hold time
tSDWDHOLD
2016-07-19
45 / 64
—
—
—
—
800 Mbps
Min
Max
—
400
2.5
—
0.47
0.53
0.47
0.53
—
200
—
ps
—
275
—
ps
—
—
—
-0.25
75
150
0.25
—
—
tCK
ps
ps
Conditions
Unit
MHz
ns
tCK
tCK
Rev. 1.6
TZ2100 Series
Technical Data Sheet
SPI Flash Memory Controller Interface
tCS
SPIB0_CSn_N
1/fCK
(n=0,1)
SPIB0_CLK
tSU
tHD
SPIB0_IO0
SPIB0_IO1
SPIB0_IO2
SPIB0_IO3
Input Timing (SDCE: rising edge)
(Note 1)
SPIB0_CLK
tSU
tHD
SPIB0_IO0
SPIB0_IO1
SPIB0_IO2
SPIB0_IO3
Input Timing (SDCE: falling edge) (Note 1)
tCS
SPIB0_CSn_N
(n=0,1)
SPIB0_CLK
tV
tHO
SPIB0_IO0
SPIB0_IO1
SPIB0_IO2
SPIB0_IO3
Output Timing
Item
SPI_CLK Clock Frequency
Data in Setup Time
Data in Hold Time
Output Valid
Output Hold Time
Chip Select High Time
Note 1:
Note 2:
2016-07-19
Symbol
fCK
tSU
tHD
tV
tHO
tCS
Conditions
—
—
—
—
—
—
Min
18.75
3
10
—
2.5
Typ.
—
—
—
—
—
(Note 2)
Max
50
—
—
4.5
—
Unit
MHz
ns
ns
ns
ns
ns
The input timing can be selected the following two modes, SDCE; Rising edge and SDCE Falling edge.
The tCS can be set up 5100 ns by SCSD.
46 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
eMMC / SD Card / SDIO Interface
1/fSDCLK
[Read]
SDn_CLK,
EMMC0_CLK
ｔSDS
ｔSDH
SDn_CMD,
SDn_DAT[3:0],
EMMC0_CMD,
EMMC0_DAT[7:0]
(n=0,1)
[Write]
SDn_CLK
EMMC0_CLK
ｔSDD
SDn_CMD
SDn_DAT[3:0]
EMMC0_CMD
EMMC0_DAT[7:0]
ｔSDD
(n=0,1)
SD Card Default Speed
Item
Clock frequency
CMD/DATA output delay time
CMD/DATA setup time
CMD/DATA hold time
Symbol
fSDCLK
tSDD
tSDS
tSDH
Conditions
—
CL < 40pF (Note 1)
—
—
Min
—
0
5.5
7.8
Typ.
—
—
—
—
Max
25
11
—
—
Unit
MHz
ns
ns
ns
Symbol
fSDCLK
tSDD
tSDS
tSDH
Conditions
—
CL < 40pF (Note 1)
—
—
Min
—
0
5.5
7.8
Typ.
—
—
—
—
Max
25
11
—
—
Unit
MHz
ns
ns
ns
Legacy MMC
Item
Clock frequency
CMD/DATA output delay time
CMD/DATA setup time
CMD/DATA hold time
Note 1:
2016-07-19
External load capacity (CL)
47 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
1/fSDCLK
[Read]
SDn_CLK
EMMC0_CLK
ｔSDS
SDn_CMD,
SDn_DAT[3:0],
EMMC0_CMD,
EMMC0_DAT[7:0]
(n=0,1)
ｔSDH
[Write]
SDn_CLK
EMMC0_CLK
ｔSDD
ｔSDD
SDn_CMD,
SDn_DAT[3:0]
EMMC0_CMD,
EMMC0_DAT[7:0]
(n=0,1)
SD Card High Speed
Item
Clock frequency
CMD/DATA output delay time
CMD/DATA setup time
CMD/DATA hold time
Symbol
fSDCLK
tSDD
tSDS
tSDH
Conditions
—
CL < 40pF (Note 1)
—
—
Min
—
3.5
5.5
2.0
Typ.
—
—
—
—
Max
50
13.5
—
—
Unit
MHz
ns
ns
ns
Symbol
fSDCLK
tSDD
tSDS
tSDH
Conditions
—
CL < 40pF (Note 1)
—
—
Min
—
3.5
5.5
2.0
Typ.
—
—
—
—
Max
25
13.5
—
—
Unit
MHz
ns
ns
ns
Symbol
fSDCLK
tSDD
tSDS
tSDH
Conditions
—
CL < 40pF (Note 1)
—
—
Min
—
3.5
5.5
2.0
Typ.
—
—
—
—
Max
50
13.5
—
—
Unit
MHz
ns
ns
ns
SD Card SDR12
Item
Clock frequency
CMD/DATA output delay time
CMD/DATA setup time
CMD/DATA hold time
SD Card SDR25
Item
Clock frequency
CMD/DATA output delay time
CMD/DATA setup time
CMD/DATA hold time
Note 1:
2016-07-19
External load capacity (CL)
48 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
SD Card SDR50
Item
Clock frequency
Symbol
fSDCLK
CMD/DATA output delay time
tSDD
CMD/DATA setup time
CMD/DATA hold time
tSDS
tSDH
Conditions
—
CL < 30 pF (Note
1)
—
—
Min
—
Typ.
—
Max
100
Unit
MHz
1.3
—
6.5
ns
2.0
1.0
—
—
—
—
ns
ns
Min
—
Typ.
—
Max
150
Unit
MHz
1.30
—
4.77
ns
1.42
1.42
—
—
—
—
ns
ns
SD Card SDR104
Item
Clock frequency
Symbol
fSDCLK
CMD/DATA output delay time
tSDD
CMD/DATA setup time
CMD/DATA hold time
tSDS
tSDH
Conditions
—
CL < 15 pF (Note
1)
—
—
Symbol
fSDCLK
tSDD
tSDS
tSDH
Conditions
—
CL < 40pF (Note 1)
—
—
Min
—
3.5
5.5
2.0
Typ.
—
—
—
—
Max
50
13.5
—
—
Unit
MHz
ns
ns
ns
Item
Clock frequency
Symbol
fSDCLK
Min
—
Typ.
—
Max
150
Unit
MHz
CMD/DATA output delay time
tSDD
1.30
—
4.77
ns
CMD/DATA setup time
CMD/DATA hold time
tSDS
tSDH
Conditions
—
CL < 15 pF (Note
1)
—
—
1.42
1.42
—
—
—
—
ns
ns
eMMC High Speed SDR
Item
Clock frequency
CMD/DATA output delay time
CMD/DATA setup time
CMD/DATA hold time
eMMC HS200
Note 1:
2016-07-19
External load capacity (CL)
49 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
External Bus Interface
4.5.5.1. Synchronous mode
tEBCLKO
EB0_CLKO
tEBOD
tEBOD
EB0_OUT
Output Signal
Item
Clock Cycle Time
Output Data Delay Time
Symbol
fEBCLKO
tEBOD
Conditions
(Note 1)
(Note 1)
Min
—
0.5
Typ.
40
—
Max
—
10
Unit
ns
ns
Typ.
40
—
—
Max
—
—
—
Unit
ns
ns
ns
tEBCLKI
EB0_CLKI
ｔEBIS
ｔEBIH
EB0_IN
Input Signal
Item
Clock Cycle Time
Input Data Setup Time
Input Data Hold Time
Note 1:
Note 2:
Note 3:
Symbol
tEBCLKI
tEBIS
tEBIH
Conditions
(Note 2)
(Note 3)
(Note 3)
Min
—
10
0.5
External load capacity (CL)
40 (max)
[pF]
CL = �
6 (min)
Connect to the dummy line of pattern layout between EB0_CLKI and EB0_CLKO on board, and locate
the end point of this line to be close to an external peripheral device in layout. Design signal delay 2 ns
or less on board.
Transition Time (20% - 80%)
1.0 (max)
Transition Time = �
[ns]
0 (min)
Refer to the timing chart in the Chapter 27 of the reference manual of the External BUS Interface. These show the
operation is based on the clock timing of EB0_CLKO.
2016-07-19
50 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
4.5.5.2. Asynchronous Mode
tINTERCLK
Internal Clock
(EBUS)
tEBIS
EB0_IN
tEBOD
EB0_OUT
Item
Symbol
Clock Cycle Time
tINTERCLK
Output Data Delay Time
Input Data Setup Time
Input Data Hold Time
tEBOD
tEBIS
tEBIH
Note 1:
Note 2:
Note 3:
Conditions
(Note 1)
(Note 2)
(Note 1)
(Note 3)
(Note 3)
Min
Typ.
Max
Unit
10
—
40
ns
—
10
1
—
—
—
15
—
—
ns
ns
ns
External load capacity (CL)
40 (max)
[pF]
CL = �
6 (min)
The clock cycle time can be set to 40 ns (default value), 20 ns or 10 ns.
Transition Time (20% - 80%)
1.0 (max)
Transition Time = �
[ns]
0 (min)
Refer to the timing chart of the section 5.4.3, 5.4.4 and 5.4.5 in the Chapter 27 of the reference manual External
BUS interface. These show the operation is based on the internal clock timing.
Determine the width of control pulses, EB0_CEn_N and etc., according to an external device specification to be
connected as follow.
tINTERCLK × 'Setting value' (Note 4) - tEBIS - tBoard (Note 5) ≥ Pulse width required by an external device [ns]
Note 4:
Note 5:
2016-07-19
The setting value on the external bus controller.
The delay time [ns] on the board.
51 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
I2C Bus Interface
1/fI2CLK
I2Cn_CLK
ｔI2HIGH
ｔI2DS
ｔI2TF
ｔI2LOW
ｔI2DH
ｔI2TR
I2Cn_DATA
(n=0 ~ 3)
ｔI2TR
ｔI2TF
Standard Speed (100 kHz)
Item
Clock frequency
LOW period of the SCL clock
HIGH period of the SCL clock
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
Input Data setup time
Input Data hold time
capacitive load for each bus line
Symbol Conditions
fI2CLK
—
tI2LOW
—
tI2HIGH
—
tI2TR
—
tI2TF
—
tI2DS
—
(Note 1)
tI2DH
(Note 2)
Cb
(Note 4)
Min
0
4.7
4.0
—
—
250
Typ.
—
—
—
—
—
—
Max
100
—
—
1000
300
—
Unit
kHz
μs
μs
ns
ns
ns
0
—
3.45
μs
—
—
400
pF
Symbol Conditions
Min
fI2CLK
—
0
tI2LOW
—
1.3
tI2HIGH
—
0.6
tI2TR
(Note 4)
20 + 0.1Cb
tI2TF
(Note 4)
20 + 0.1Cb
tI2DS
(Note 3)
100
(Note 1)
tI2DH
0
(Note 2)
Cb
(Note 4)
—
Typ.
—
—
—
—
—
—
Max
400
—
—
300
300
—
Unit
kHz
μs
μs
ns
ns
ns
—
0.9
μs
—
400
pF
Symbol Conditions
fI2CLK
—
tI2LOW
—
tI2HIGH
—
tI2TR
—
tI2TF
—
tI2DS
—
(Note 1)
tI2DH
(Note 2)
Cb
(Note 4)
Min
0
0.5
0.26
—
—
50
Typ.
—
—
—
—
—
—
Max
1000
—
—
120
120
—
Unit
kHz
μs
μs
ns
ns
ns
0
—
—
μs
—
—
550
pF
Fast Speed (400 kHz)
Item
Clock frequency
LOW period of the SCL clock
HIGH period of the SCL clock
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
Input Data setup time
Input Data hold time
capacitive load for each bus line
Fast mode Plus Speed (1 MHz)
Item
Clock frequency
LOW period of the SCL clock
HIGH period of the SCL clock
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
Input Data setup time
Input Data hold time
capacitive load for each bus line
2016-07-19
52 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
Note 1:
Note 2:
Note 3:
Note 4:
2016-07-19
The I2C interface should have the minimum hold time of 300 ns internally (from the VIH min point of
SCL signal) in order to prevent from instability at the falling edge of SCL.
The max value of tI2DH is valid as long as the low period of SCL (tLow) is not extended.
Fast Speed mode of I2C interface can be used in Standard Speed mode, if the condition of tI2DS ≥ 250
ns is satisfied. This means the interface does not extend the low period of the SCL. In this case the next
data should be output to SDA before the following time;
tI2TR(Max) + tI2DS = 1000 + 250 = 1250 ns
(maximum rise time of Standard Speed mode + the setup time of the next data)
Cb is a total capacitance of one bus line (unit: pF).
53 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
SPI Interface (for Master Controller and Transmission)
SPIM0 and SPIM1 for master controller, SPITX0 to SPITX6 for dedicated transmission.
1/fSPMCLK
SPIMn_CLK
SPITXm_CLK
ｔSPMS
ｔSPMH
SPIMn_IN
SPITXm_IN
ｔSPMD
ｔSPMD
SPIMn_OUT
SPITXm_OUT
(n=0,1; m=0, 1, …, 6)
Item
Clock frequency
Output Data delay time
Input Data setup time
Input Data hold time
Symbol
fSPMCLK
tSPMD
tSPMS
tSPMH
Note 1:
External load capacity (CL)
Note 2:
Transition Time (20% - 80%)
Conditions
(Note 1)
(Note 1)
(Note 2)
(Note 2)
Min
—
0.5
8
0
Typ.
—
—
—
—
Max
25
10
—
—
Unit
MHz
ns
ns
ns
30 (max)
[pF]
CL = �
0 (min)
1.0 (max)
Transition Time = �
[ns]
0 (min)
The maximum value of fSPMCLK may be reduced by the load on board layout, and an external device.
The above timing chart is in case of SCPH = 0. In case of SCPH = 1, the signal of SPIMn_Out synchronizes to the
rising edge of SPIMn_CLK, the specification of tSPMD is same as the value in case of SCPH = 0.
There is no specifications about SPITXm (m = 0, 1, … , 6) input signals.
2016-07-19
54 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
SPI Interface (for Slave Controller)
1/fSPSCLK
SPISn_CLK
(SPISn_SHDW_CLK)
ｔSPSS
ｔSPSH
SPISn_IN
(SPISn_SHDW_IN)
ｔSPSD
ｔSPSD
SPISn_OUT
(SPISn_SHDW_OUT
(n=0)
Item
Clock frequency
Output Data delay time
Input Data setup time
Input Data hold time
Symbol
fSPSCLK
tSPSD
tSPSS
tSPSH
Note 1:
External load capacity (CL)
Note 2:
Transition Time (20% - 80%)
Conditions
—
(Note 1)
(Note 2)
(Note 2)
Min
—
0.5
40
25
Typ.
—
—
—
—
Max
5
50
—
—
Unit
MHz
ns
ns
ns
30 (max)
CL = �
[pF]
0 (min)
1.0 (max)
Transition Time = �
[ns]
0 (min)
The above timing chart is in case of SCPH = 0. In case of SCPH = 1, the signal of SPISn_Out
(SPISn_SHDW_Out) synchronizes to the rising edge of SPISn_CLK (SPISn_SHDW_CLK), the specification of
tSPSD is same as the value in case of SCPH = 0.
2016-07-19
55 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
Ethernet MAC interface
tCYC
[RMII Transmission]
ETH0_REFCLK
tCO(min)
tCO(max)
ETH0_TXD[1:0]
ETH0_TXEN
tCYC
[RMII Receiving]
ETH0_REFCLK
tHOLD
tSETUP
ETH0_RXD[1:0]
ETH0_CRSDV
Item
ETH_REFCLK clock cycle time
ETH_TXD1 to 0/ETH_TXEN output delay time
ETH_RXD1 to 0/ETH_CRSDV setup time
ETH_RXD1 to 0/ETH_CRSDV hold time
Symbol
tCYC
tCO
tSETUP
tHOLD
Conditions
(Note 2)
(Note 1)
(Note 2)
(Note 2)
Note 1:
External load capacity (CL)
Note 2:
Skew against reference clock of PHY device must be 0.5 ns or less.
Transition Time (20% - 80%)
2016-07-19
Min
—
2
4
2
Typ.
20
—
—
—
Max
—
12.5
—
—
Unit
ns
ns
ns
ns
25 (max)
CL = �
[pF]
0 (min)
1.0 (max)
Transition Time = �
[ns]
0 (min)
56 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
Camera Input
tCAMCLK
CAM0_CLK
tCAMS
tCAMH
tCAMS
tCAMH
CAM0_VSYNC
CAM0_HSYNC
CAM0_DATA[0:7]
Item
CAM0_CLK clock cycle time
CAM0_VSYNC/CAM0_HSYNC/
CAM0_DATA[7:0] setup time
CAM0_VSYNC/CAM0_HSYNC/
CAM0_DATA[7:0] hold time
2016-07-19
Symbol
tCAMCLK
Conditions
—
Min
10
Typ.
—
Max
—
Unit
ns
tCAMS
—
4
—
—
ns
tCAMH
—
1
—
—
ns
57 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
LCD Output
tCYC
[GDCDCR_L].PDC=1
(Rising edge)
LCD0_CLK
tCOp
tCOp
LCD0_RD[7:0]
LCD0_GD[7:0]
LCD0_BD[7:0]
LCD0_HSYNC
LCD0_VSYNC
LCD0_VALID
[GDCDCR_L].PDC=0
(Falling edge)
tCYC
LCD0_CLK
tCOn
tCOn
LCD0_RD[7:0]
LCD0_GD[7:0]
LCD0_BD[7:0]
LCD0_HSYNC
LCD0_VSYNC
LCD0_VALID
Item
clock cycle time
output delay time
2016-07-19
Symbol
tCYC
tCOp
tCOn
Conditions
—
[GDCDCR_L].PDC = 1 (Rising edge)
[GDCDCR_L].PDC = 0 (Falling edge)
58 / 64
Min
23
0
0
Typ.
—
—
—
Max
—
5
5
Unit
ns
ns
ns
Rev. 1.6
TZ2100 Series
Technical Data Sheet
Audio Interface
Bit clock output (1): Falling edge data output, Rising edge input data sampling
ｔABCK
(n=0,1)
Output clock
I2Sn_BCK
ｔADIS
Input
ｔADIH
I2Sn_DI
Output
ｔADOD
ｔADOD
ｔADOD
I2Sn_LRCK
I2Sn_DO
Bit clock output (2)：Rising edge date output、Falling edge input data sampling
ｔABCK
(n=0,1)
Output clock
I2Sn_BCK
ｔADIS
Input
ｔADIH
I2Sn_DI
Output
ｔADOD
ｔADOD
I2Sn_LRCK
I2Sn_DO
Item
Symbol
Conditions
I2S Output Clock Period
tABCK
—
I2S Input Data Setup Time
I2S Input Data Hold Time
I2S Output Delay Time
tADIS
tADIH
tADOD
—
—
—
Note 1:
2016-07-19
Min
81.38
(Note 1)
10
10
0
Typ.
Max
Unit
—
—
ns
—
—
—
—
—
10
ns
ns
ns
Max 12.288 MHz
59 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
Bit clock input (1)：Falling edge data output, Rising edge input data sampling
ｔABCK
(n=0,1)
Input clock
I2Sn_BCK
ｔADIS
Input
ｔADIH
I2S_LRCK
I2Sn_DI
Output
ｔADOD
ｔADOD
I2Sn_DO
Bit clock input (2)：Rising edge data output, Falling edge input data sampling
ｔABCK
(n=0,1)
Input clock
I2Sn_BCK
ｔADIS
Input
ｔADIH
I2Sn_LRCK
I2Sn_DI
Output
ｔADOD
ｔADOD
I2Sn_DO
Item
Symbol
Conditions
I2S Input Clock Period
tABCK
—
I2S Input Data Setup Time
I2S Input Data Hold Time
I2S Output Delay Time
tADIS
tADIH
tADOD
—
—
—
Note 1:
2016-07-19
Min
81.38
(Note 1)
10
10
0
Typ.
Max
Unit
—
—
ns
—
—
—
—
—
10
ns
ns
ns
Max 12.288 MHz
60 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
Parallel Data Input
tPW_PPTWTSTB
PPI0_STB_N
tSU_PPTWDA
PPI0_DIn
(n=0, 1, …, 7)
tDLY_PPTWACKN
PPI0_ACK
PPI0_WBUSY
tDLY_PTWACKA
Item
Strobe Pulse Width
Write Data Setup Time
Output Delay of Asserting
Acknowledge and Write-Busy Signals
Output Delay of De-asserting
Acknowledge Signal
Note 1:
Transition Time (20% - 80%)
Note 2:
External load capacity (CL)
Symbol
tPW_PPTWSTB
tSU_PPTWDA
Conditions
(Note 1)
(Note 1)
Min
50
30
Typ.
—
—
Max
—
—
Unit
ns
ns
tDLY_PTWACKA
(Note 2)
—
—
70
ns
tDLY_PPTWACKN
(Note 2)
—
—
70
ns
1.0 (max)
Transition Time = �
[ns]
0 (min)
30 (max)
[pF]
CL = �
0 (min)
AD Conversion Input
Item
Sampling Frequency
Symbol
fs
Analog Input Voltage Range VIN
ADC Differential Error
DNL
ADC Integrated Error
INL
2016-07-19
Conditions
Min
Typ.
Max
Unit
Input on 1 channel
—
—
1.07
MHz
—
There is no AC noise
in the power supply
and the GND.
0
—
VDD3V3_ADC
V
-2
—
+4
LSB
-6
—
+6
LSB
61 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
5. Package
5.1. Package outline
Package name: P-LFBGA310-1616-0.80-001
Unit: mm
Weight: 0.75 g (Typ.)
Figure 5.1
2016-07-19
Package Outline
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Rev. 1.6
TZ2100 Series
Technical Data Sheet
6. Revision history
Table 6.1 Revision History
Revision
0.1
1.0
1.1
1.2
1.3
1.4
1.5
1.6
2016-07-19
Date
Description
2015-03-11 Initial release in English version
Official version
3.3 Added the explanation of attribute, instead of the table
3.3.2 Added the notice
3.3.19 Added the notice
3.3.22 Deleted P7 of column
2015-07-15
3.4.1 Added the note of pin-type in Table 3.2
4.2 Added Operating Conditions
4.3 Added Current dissipations
4.4 Added DC characteristics
4.5 Added AC characteristics
2015-10-02 3.3.22 Correct IDX16 column
2015-11-30 Modify CF to CL symbol
Modified Figure 2.1.
2016-01-05 Changed RTC clock frequency to 32.768 kHz in 3.3.1.
Added note description in Table 3.2.
2016-01-14 Modified 3.3.1 XOUT_32K to In/Out.
Changed description from SPI interface to SPI Flash Memory
Controller Interface.
Changed note description in 1.1.CPU Note 1.
Changed description in 1.7.(1)
Added 1.7.(3) WVGA resolution (800 × 480)
Changed description of 3.3.1.DBG_SRST_N.
Changed title name 3.3.17 and 4.5.13.
Modified from CL to CL and Note description in 4.5 (4.5.5.1, 4.5.5.2,
2016-05-30 4.5.7, 4.5.8, 4.5.9, 4.5.13).
Changed description in 1.11.(2)
Added IDX6 DBG_SRST_N in 3.3.20.JTAG interface for debugging.
Modified description in 3.4.1.
Added SPI_CLK Clock Frequency minimum specification 18.75 MHz
in 4.5.3.
Added Note description in 3.3.11.
Added Fast mode Plus Speed (1 MHz) specification.
Changed VDD3V3_PB minimum value and added Note description
in 4.2.1 and 4.2.2, 4.2.3.
Added products (ADD codes) and Operating Temperature, Internal
Voltage Range, USB 2.0 Function in List of Products.
Added etc. in 1.1.CPU Operation frequency.
Delete Note in 3.3.20. JTAG interface for debugging.
2016-07-19
Modified description in 3.4.1.
Changed 4.2.2 title name (TZ2101XBG/TZ2102XBG→TZ2102XBG).
Modified Conditions of “High-level output voltage” in 4.4.1.
Modified Unit of “Strobe Pulse Width” in 4.5.13.
63 / 64
Rev. 1.6
TZ2100 Series
Technical Data Sheet
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information in this document, and related hardware, software and systems (collectively "Product") without notice.
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versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and
application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook"
and (b) the instructions for the application with which the Product will be used with or for. Customers are solely responsible for all
aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this
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• Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any
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any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise.
• ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF
SALE FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY
WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES
OR LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION
AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS
RELATED TO SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT.
• Do not use or otherwise make available Product or related software or technology for any military purposes, including without
limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile
technology products (mass destruction weapons). Product and related software and technology may be controlled under the
applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the
U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited
except in compliance with all applicable export laws and regulations.
• Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of
Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled
substances, including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR
LOSSES OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS.
2016-07-19
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Rev. 1.6