Thermal Management of
the ACULED® VHL
Introduction
Excelitas’ new ACULED® VHLTM,
with its superior four-chip design and
smallest footprint, gives customers the
most flexible multi-chip LED on the
market. The product family contains
various products from UV via VIS to IR
with a variety of chip configurations,
including sensors and thermistors.
Excelitas’ ACULED® DYOTM even
enables customers to put together their
own configuration. Please refer to the
Custom Design Guide, “ACULED DYO Design-Your-Own,” for more details on
this product.
Preventing the ACULED from
overheating by taking away the heat from
the package is a key point when
designing the ACULED into your product.
This application note describes the
thermal management of the ACULED
and further considerations in heat-sink
design.
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Features and Benefits of the
ACULED® VHL and DYO
High power light, UV and IR source
Ultra compact footprint
Excellent color mixing due to high
packaging density
Separate anode and cathode for each
color and pad
Various standard configurations available
Combination of LED with sensors
Design-Your-Own (DYO)
Applications
General illumination
Entertainment and shop design
Furniture lighting
Architectural and landscape lighting
Mood lighting
Vision systems
Backlighting
Medical lighting
Display and signs
Customized chip configuration
Author
• Jörg Hannig
Excelitas Technologies
Luitpoldstrasse 6
85276 Pfaffenhofen
Germany
Phone: +49 8441 8917 0
Fax: +49 8441 71910
Email: joerg.hannig@excelitas.com
Technical Support
• For additional technical support,
please contact us at:
generalinquiries@excelitas.com
Table of Contents
General Remarks and Construction of the ACULED VHL
3
Efficiency and Efficacy
4
Influence of Thermal Management
4
Heat Generation in the ACULED
8
Heat Transportation and Thermal Path
9
Calculating with Thermal Resistances
11
Thermal Resistances of the ACULED VHL
13
Thermal Resistances of the ACULED DYO
15
Heat-Sink Calculation
19
Heat-Sink Types
22
Heat-Sink Mounting
24
Symbols and Units
28
Abbreviations
30
Notes
32
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Thermal Management of the ACULED® VHL
2
General Remarks and Construction of the ACULED VHL
The ACULED VHL board is based on an insulated metal core substrate (IMS) made from
copper and a highly-sophisticated isolation material with a low thermal resistance between the
copper and chip pads. This package provides excellent heat dissipation and thermal
management from the chip to the substrate’s backside. The thermal resistance Rth,JB of the
entire package is quite low, depending on the chip configuration. To dissipate the heat,
adequate cooling must be considered. To avoid damaging the LED chips by overheating when
equipped with at least one high-power LED chip, the ACULED must not run without appropriate
cooling - even at lower currents!
Figure 1 shows the typical layout of the ACULED VHL. The chips are placed in the middle of the
board, protected by a PPA-based ring and silicone resin encapsulation. The latter is transparent
and suitable for a wide range of radiation - from ultraviolet (UV) to infrared (IR). It is also more
resistant to heat than epoxy resin, and its heat expansion characteristics are closer to those of
chips. With the ACULED’s high-power LEDs, silicone achieves superior resistance to light
radiation, mitigating degradation, and maintaining LED color purity over the LED’s lifetime. The
mechanical stress applied to the chips is lowest with silicone, when compared to other standard
encapsulation materials. Due to its softness, pressure to the silicone area within the ring must
be avoided. Please refer to the application note, “Handling of LED and Sensor Products
Encapsulated by Silicone Resin,” to learn more about handling silicone-based products such as
the ACULED.
The clockwise numbered pads C1 - C4 inside the encapsulation ring show the pads where the LED
chips are placed. The distance between the chips is typically 0.2 mm with a pitch of 1.2 mm.
Therefore, the lighting area is approximately 2.2 x 2.2 mm², depending on the particular chip
configuration for the specific ACULED VHL or ACULED DYO product. The numbers of the soldering
pads run counter-clockwise from pin 1 to pin 8. The pad numbers 4 and 5 are printed on the board.
Pin 1 is easily located by the small gold dot, which can be used as a reference for mounting.
Whether ESD protection diodes can be used depends on the ESD sensitivity of the LED chips,
referenced in the specific datasheets of the products.
The tracks on the ACULED are made from copper with a thin gold layer to achieve better
bonding results.
Figure 1
Layout and Dimensions of the
ACULED VHL
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Thermal Management of the ACULED® VHL
3
Efficiency and Efficacy
Modern high-power and high-brightness LED chips used with the ACULED product family can
be driven at 1 to 5 W, depending on the chip material (i.e. color) and cooling. The efficiency of
these chips is up to 20% and more in practice, depending on the current, chip material, cooling
etc. In laboratory scale and at low current, the efficiency is even much higher. Efficiency η
means how much optical power (radio metrical, measured in watts) comes out of the LED chip
when a certain amount of electrical power is applied, usually measured in mW/W or simply
percentage. Besides the efficiency, the efficacy ηopt is also often used. This is the output power
in lumens, i.e. the photometrical value giving the amount of visible light that leaves the LED per
Watt of electrical input power. Efficacy is measured in lm/W and only suitable when comparing
LEDs of the same color or wavelength and within the visible range. For example, a 950 nm IR
LED does not have any lumens, since it emits only non-visible radiation and no visible light.
Thus, for heat management, efficiency rather than efficacy must be dealt with. The following
equations show the general calculations:
Calculation of electrical power
The electrical power Ptot is forward current multiplied by forward voltage:
Ptot
= IF — VF
(1)
The forward voltage VF at a certain forward current IF can be taken from the specific diagram in the
ACULED datasheet. The electrical power of the particular ACULED at defined operating conditions
is also provided by its datasheet.
Calculation of the efficiency
Efficiency is optical power Popt over electrical power:
η = Popt / Ptot
(2)
The optical power is given in the specific ACULED datasheet for non-visible chips and chips
with colors close to the limit of the human eye’s spectral sensitivity. The efficiency of the
particular ACULED at defined operating conditions is also provided by its datasheet for the nonvisible
LED-chips.
Calculation of the efficacy
Efficacy is luminous flux Φ V over electrical power:
ηopt = ΦV / Pel
(3)
The luminous flux at a certain forward current IF can be taken from the specific diagram in the
ACULED datasheet. The efficacy of the particular ACULED at defined operating conditions is also
provided by its datasheet for the visible LED-chips.
Influence of Thermal Management
As we have seen in the previous section, modern high-power LED chips used with the ACULED
product family have efficiencies of 10% - 20% of radiation output at common operation
conditions. Thus, 80% to 90% of the electrical energy is transformed into another kind of
energy, specifically heat. Unlike with incandescent lights, almost no heat is radiated into the
LED’s environment. Hence, the LED light is often referred to as “cold” due to the absence of IR
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Thermal Management of the ACULED® VHL
4
radiation. With standard light bulbs, a high amount of IR radiation is emitted, warming up the
environment or illuminated subject. A big advantage of LEDs is not radiating heat around
heatsensitive subjects requiring illumination. However, heat is still present in LED chips, particular in
the pn-junction where the light is generated. This heat must be mitigated by thermal conduction to
avoid destruction of the LED chip and other unwanted effects.
Besides helping to avoid chip damage by overheating, good thermal management helps us to get a
grip on all parameters impacted by temperature, which include:
•
•
•
•
life time [tLife]
forward voltage [VF]
flux [Φ e and Φ V]
wavelength [λ] resp. color [x2°/ y2°] and color temperature (TCT).
A big advantage of the ACULED VHL and DYO versus other similar products on the market is
minimized thermal crosstalk between the pads. We will learn more about this in a later chapter
of this application note. As a result of this low thermal crosstalk, the warming of one LED has
minimal affect on neighboring chips, resulting in excellent constancy in the parameters
described above.
Influence on lifetime
Overheating an LED chip, i.e. exceeding its junction temperature TJ over the allowable
maximum, will damage the chips within a short time. But long term temperature affects also
influence a decreased lifetime. During operation, the lower the temperature, the longer the
lifetime for the chip and the whole ACULED product. Some degeneration processes require a
minimum temperature to get started. Thus, a low TJ will dramatically increase the product’s
lifetime. Since these processes are very complex and not fully understood today, it’s virtually
impossible to get reliable curves of tLife versus TJ today for a longer periode of time.
Influence on forward voltage
The forward voltage VF usually decreases in the range of several mV per Kelvin with increases in
temperature. Since this change in approximation is linear over the typical small temperature
changes, it is provided in the temperature coefficient of forward voltage TCVF found in the
ACULED VHL datasheet or the chip datasheets of the ACULED DYO chips. Figure 2 shows typical
curves for red, green, and blue chips.
The change ∆VF of the forward voltage is calculated by the following equation:
∆VF = TCVF — ∆TJ
VF1
= TCVF — (TJ1 - TJ0) + VF0
(4)
(4a)
VF1 is the forward voltage that we want to calculate at a temperature TJ1, whereas VF0 is a
known forward voltage at a known temperature TJ0, e.g. values given by the datasheets. In a
steady state, the junction temperature TJ and the substrate temperature TB are interchangeable in
the equation:
VF1
= TCVF — (TB1 - TB0) + VF0
(4b)
With a decrease of the forward voltage, power consumption drops as well at a given current. But
due to the small change, it is of no practical significance.
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Thermal Management of the ACULED® VHL
5
Figure 2
Relative Forward Voltage
Relative forward voltage
versus ACULED VHL
1,06
board temperature TB for
red, green and blue chips
1,04
1,02
V/V
1
0,98
0,96
0,94
0,92
10
20
30
40
50
60
70
80
T B [°C]
Influence on flux and intensity
The flux, Φ e and Φ V , and their deducted values, such as luminance, radiance, luminous
intensity or radiant intensity, decreases with increasing temperature. Generally speaking, the
intensity drop of blue and green chips is usually small, whereas the drop with yellow, amber and
red chips is larger. Figure 3 shows typical curves representing the relative luminous drift for the
chips of the RGYB ACULED VHL. These charts can be found in the specific datasheets of the
ACULED VHL products. For the ACULED DYO, an approximation is given by the luminous or
radiant flux temperature coefficient (TCΦV resp. TCΦe) in the specific datasheets of the chips.
The change ∆Φ of the luminous or radiant flux can be calculated analogous to the calculation of the
forward voltage drift over temperature by the following equation:
∆Φ
= TCΦ — ∆TJ
Φ1
= TCΦ — (TJ1 - TJ0) + Φ0
(5)
(5a)
Φ 0 is the known flux at a known temperature TJ0 given by the datasheets. In a steady state, the
junction temperature TJ can be interchanged with the substrate temperature TB in the equation:
Φ1
= TCΦ — (TB1 - TB0) + Φ0
(5b)
If a certain flux is necessary in your application, it’s important to level out the intensity drop. A
good thermal management will also help you to keep the drift as low as possible. The balancing
of the drift over temperature is important, particularly when having chips of different colors on
your ACULED like RGGB or RGYB, to keep the same intensity ratio and, therefore, the same
color appearance. With the RGYB for example, the color mix drifts to a blue-greenish light with
increasing temperature, since yellow and red fade out much more than blue and green, as
shown in Figure 3. Due to the excellent suppression of any thermal crosstalk, each chip can be
levelled out individually without regard for how its temperature and heating change influence its
neighbors.
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Thermal Management of the ACULED® VHL
6
Besides a changing mixed color ratio due to the different intensity changes, each chip also
changes color as a result of wavelength drift caused by temperature.
Figure 3
Relative Luminous Flux = f(T B)
Change of relative
luminous flux vs. board
temperature TB for the
RGYB chips of the
ACULED VHL
140,00
130,00
120,00
in %
90,00
/
100,00
25°C
110,00
80,00
70,00
60,00
50,00
40,00
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
T B [°C]
Influence on wavelength and color
The change of the wavelength (λpeak resp. λdom) and, therefore, the color versus the
temperature, is linear in first approximation at small temperature changes and can be
determined by the temperature coefficients TCλ peak and/or TCλ dom. These are found in the
ACULED VHL datasheets or the specific chip datasheets of the ACULED DYO. Figure 4 shows
a typical curve of the IR ACULED VHL. This curve is shown in each individual ACULED VHL
datasheet.
The change ∆λ of the peak or dominant wavelength can be calculated analogous to the
calculation of the forward voltage drift over temperature by the following equation:
∆λ
= TCλ — ∆TJ
λ1
= TCλ — (TJ1 - TJ0) + λ0
(6)
(6a)
λ0 is the known wavelength at a known temperature TJ0 given by the datasheets. In a steady
state, the junction temperature TJ is interchangeable with the substrate temperature TB in the
equation:
λ1
= TCλ — (TB1 - TB0) + λ0
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(6b)
Thermal Management of the ACULED® VHL
7
Figure 4
Peak wavelength λ peak = f(T B)
Change of peak
wavelength vs. substrate
temperature TB for the IR
ACULED VHL
875,0
870,0
peak
[nm]
865,0
860,0
855,0
850,0
845,0
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
T B [°C]
Heat Generation in the ACULED
The amount of heat or thermal power Pth that is generated in an operating ACULED is estimated by
the following equation:
Pth
= Ptot - Popt
(7a)
= (1 - η) Ptot
(7b)
For an easier calculation with regard to safety in heat management, we recommend calculating with
the electrical power consumption Ptot as the total heat dissipation. This gives 10% - 20% of “safety
margin” for any unexpected thermal conditions in your application. Hence, all further calculations
shown in this application note are done with Ptot. The electrical power of the
particular ACULED product can be found in its datasheet. Typical values of ACULED products
equipped with four high-power LEDs are 5 W at 350 nm and 10 W at 700 nm, respectively. This
requires up to 10 W of heat to be drawn away from the ACULED board.
The limiting value for prevention of overheating is the junction temperature TJ at the pn junction of
the chip. Typically, it must not ever exceed TJ max = 125 °C. The specific values of your
ACULED VHL or chips used for your ACULED DYO can be found in the datasheets. The
maximum substrate temperature1 TB max is calculated as follows:
TB max = TJ max - ∆TJB
= TJ max - Rth JB — Ptot
(8a)
(8b)
1
The symbol TB often is explained as board temperature or base temperature. It indicates the temperature at the
backside of the substrate and, hence, at the interface to the subsequenting board or heat sink. In this application
note, “board.” “base,“ and “substrate“ temperature are used synonymously for the TB on the back side of the
ACULED.
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Thermal Management of the ACULED® VHL
8
∆TJB represents the temperature difference between junction and substrate temperature, and Rth JB
represents the thermal resistance between junction temperature and substrate, which is typically 5
K/W for the ACULED VHL. Taking a Ptot = 5 W ACULED, for example, will lead to an absolute
maximum substrate temperature according to Equation 8b of:
TB max =
125 °C - 5 K/W — 5 W =
100 °C
(Remember, that the Kelvin [K] scale equals the Degree-Celsius [°C] scale when only looking at
difference values like ∆TJB in this case.) In this example, the substrate temperature must not exceed
100 °C. The thermal resistance for a particular ACULED product, as well as the
maximum allowable junction temperature TJ , can be found in its datasheet. The junction
temperature is mainly dependent on the following parameters:
•
•
•
power consumption Ptot of the ACULED, as described in this chapter
ambient temperature TA
thermal path from chip’s pn-junction to ambient surrounding (resistance Rth JA)
Table 1
Material
Thermal Conductivity
λth [W / (mK)]
copper
400
gold
320
wire bonds, chip pads
aluminum
230
heat sinks
AlN:
Al2O3:
GaN:
silicon:
sapphire:
ceramic
chip substrates
used for
ACULED board (IMS), heat pipes,
PCB tracks and pads
170
30
160
150
42
Thermal conductivity λth
(typically) for different
materials
PCB substrate
chip substrate
tin
67
solder
TIM (thermal grease)
2 - 4.5
water (no convection)
0.6
cooling (convection)
FR4
0.23
PCB substrate
silicone
0.1
encapsulation
air (no convection)
0.025
cooling (convection)
interface between ACULED and heat sink
Heat Transportation and Thermal Path
Generally, there are three different ways of heat transportation:
•
•
•
Convection
Radiation
Conduction
Unlike with incandescent lights where a significant amount of the generated heat is transported
by radiation, high-power LEDs have less than 5% of their heat transported by convection and
radiation. Hence, more than 95% of the generated heat must be drawn away from the LED chip
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Thermal Management of the ACULED® VHL
9
by conduction. The highly sophisticated copper substrate (IMS) of the ACULED VHL was
designed to provide excellent heat transport from the chip to the backside of the substrate.
However, it’s also important to dissipate the heat from the ACULED’s substrate by adequate
heat-sinks and cooling.
temperature
thermal resistance
Figure 5
assembly
Principle of thermal paths
in the ACULED VHL/DYO
LED-Chip
TJ
TC
red: pn-junction (J)
chip substrate
Rth C
Rth JB
Rth P
IMS-PCB
TIM
TB
Rth JA
Rth BA
TA
Heatsink
Ambient Surrounding (Air)
Figure 5 shows the characteristic of the ACULED construction regarding the conductive thermal
path. Depending on the cooling and heat-sink, the heating situation will achieve a steady state
within a few tens of milliseconds for the ACULED VHL package without an additional heat-sink
(see Figure 6) and up to several minutes when cooled properly, as shown later in Figure 16 on
page 22 of this application note. Since the silicone filling material has very low thermal
conductivity, it does not extract much heat from the chips. Also, the heat transportation by the
bond wires is marginal and, therefore, not included in the thermal path model of the ACULED.
The thermal resistances of the ACULED, as shown in Figure 5, are explained in Table 2. Table
1 shows the thermal conductivity λth for different materials, showing which are good for heat
transfer or heat spreading and which are not.
Figure 6
Turn-on (left) and turn-off
(right) decay of the
ACULED VHL when
operated without cooling
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Thermal Management of the ACULED® VHL
10
In the ACULED VHL datasheet, the thermal resistance Rth JB between the chip’s junction layer
and the back of the substrate is given for all chips running with the same nominal current. In the
previous section, the use of this value to calculate the temperature drop was shown in Equation
8. When configuring your own ACULED DYO, this critical resistance is computed by combining
the “package” resistance Rth P for the IMS-PCB with the individual chip’s thermal resistances
Rth C , provided in the appropriate chip datasheets. The next sections describe how to achieve
this calculation. The thermal resistant Rth P , of course, includes the whole ACULED VHL
package - from the chip pad layer, including the die junction, down to the substrate’s back side.
Besides calculating Rth JB for your own ACULED DYO configuration, calculating Rth BA from the
ACULED to the ambient surrounding is important for selecting an appropriate heat-sink. This is
calculated according to Equation 8b as follows:
Rth BA = ∆TBA / Ptot =
(TB - TA) / Ptot
(8c)
With the ambient temperature TA and the given maximum temperature TB of the ACULED VHL
substrate (see datasheet), we can calculate the maximum thermal resistance allowable for the heatsink. Of course, heat-sinks with better thermal resistances, as calculated by Equation 8c, are also
working properly.
The last step from the heat-sink to the ambient surrounding (e.g. air) is usually a heat transfer
by convection. The air or liquid in water-cooled systems flows through the heat-sink and heat is
removed. Therefore, along with the ambient temperature TA , the flow parameters of the air or
liquid, such as velocity and density, are also very important to consider. With a fan, for example,
the air flow velocity and, in turn, the heat transfer from the heat sink to the ambient air can be
increased dramatically. Figure 7 shows the difference made by a cooling fan - up to 30 °C in
this case.
120
Figure 7
100
TJ vs. time t of operation of
the ACULED VHL on the
same heat-sink with free
convection (red) and with
additional fan (green)
TJ [°C]
80
60
40
free convection
20
with fan
0
0
200
400
600
800
1000
1200
t [s]
Calculating with Thermal Resistances
When calculating the thermal resistance of your own ACULED DYO configuration, the
necessary heat-sink, or the temperature drops, it is important to know how all three individual
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Thermal Management of the ACULED® VHL
11
values work together. In this section, we will learn how to use the various formulas and
equations.
In these calculations, the thermal resistances Rth are analogous to the electrical resistances. The
formula required to calculate the temperature drop ∆T through a thermal resistance has already
been used in previous sections:
∆T = Ptot — Rth
(8)
Serial resistances can simply be added:
Rth, all = Rth, 1 + Rth, 2 + Rth, 3 + T
(9)
For example, this was done with Rth JB as an addition of the internal chip and the package
resistance in Table 2. Parallel resistances are calculated by the following equation:
1
Rth, all =
1
R
th,1
+
1
R
th,1
(10)
1
+ +L
R
th,1
Figure 8 shows the corresponding schematic diagrams. When more than one ACULED is
mounted to a single heat-sink, it results in parallel working heat resistances. The individual
thermal resistances Rth JB of each ACULED must be calculated according to Equation 10 to
provide the combined thermal resistance of all the ACULEDs. Though the resulting Rth JB all is
lower than the individual resistances, it does not indicate a lower temperature drop from TJ to TB all
since the power consumption Ptot all is also increasing.
Thermal Resistance
identifies
internal resistance of
LED chip
Rth C
package (board)
Rth P
Rth JB = Rth C + Rth P
whole ACULED
heat sink including
thermal grease and
heat transfer to air
overall module
resistance
Rth BA
Rth JA = Rth JB + Rth BA
between
Temperatures
chip’s pn-junction TJ
and chip substrate
backside TC
ACULED VHL
not published
TC and ACULED
backside TB
TJ and TB
TB and ambient
temperature TA
ACULED DYO
Table 2
shown in DYO
Explanation of the thermal
resistances of the
chip datasheets
ACULED VHL/DYO as
shown in Figure 5
5 K/W
shown in datasheets
depends on chip
configuration
depending on application specific
heat sink
TJ and TA
Let us look on an example. Let’s assume putting a single RGYB ACULED VHL (product code
ACL01-MC-RGYB-E08-C01-L) on a heat sink. From the datasheet, we get the following values:
•
•
•
Rth JB
Ptot
TJ max
= 5 K/W
= 11.2 W (@ 700 mA)
= 125 °C
According to Equation 8, we get a temperature drop of ∆TJB = 11.2 W — 5 K/W = 56 K, or a
maximum allowable substrate temperature TB max = 69 °C. The heat-sink must assure this
maximum temperature to avoid heat damage of the LED chip on this RGYB ACULED when
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Thermal Management of the ACULED® VHL
12
driven at 700 mA. Let’s now assume we have 10 of these ACULEDs on one heat-sink. What is the
maximum temperature TB all the heat-sink must cool to? According to Equation 10, the
overall thermal resistance is:
Rth, all =
1
10
5 KW
= 0.5 K/W
The resistance of this configuration now is much lower, but the total power consumption is 10
times higher, or Ptot all = 10 — Ptot = 112 W. According to Equation 8, the temperature drop is still
∆TJB tot = 112 W — 0.5 K/W = 56 K or TB all = 69 °C. Hence, the heat sink still must cool the
substrates down to 69 °C - meaning it must draw away 10 times more heat (112 W instead of
11.2 W). The lesson learned is that it’s always very important to look at the whole situation when
calculating thermal resistance, particularly in terms of the total heat generated or power
consumed. The value Rth by itself can be misleading. This is also very important to know when
comparing different packages.
However, all these equations apply strictly to vertical heat transportation. The more ACULEDs that
are mounted on a heat-sink, the higher the influence of the horizontal heat spreading in the different
layers of the heat-sink. It’s also very important to keep in mind the total amount of heat (given by
Equation 7b) that must be drawn away.
We will learn in the next sections that the ACULED can be considered as a mixture between parallel
and serial thermal resistances, which is especially important when designing your
ACULED DYO for your particular application. But even if you use standard ACULED VHLs, it is
recommended to read the next section and learn more about the ACULED package and its
internal thermal management.
a)
Figure 8
b)
Rth, 1
Rth, 2
Rth, 3
Rth, 1
c)
Schematic diagrams of
thermal resistance
principals:
a) serial
b) parallel
c) mixture
Rth, 2
Rth, 1
Rth, 3
Rth, 3
Rth, 2
Thermal Resistances of the ACULED VHL
Figure 9 shows the thermal schematic diagram of the ACULED VHL and ACULED DYO
together with a heat-sink. The ACULED VHL has four electrically and thermally separated pads (see
Figure 1) whose resistances Rth Cn are “connected” in parallel. Due to its superior internal thermal
concept, there is almost no thermal crosstalk (typically << 1K) between the chip pads and, thus,
between the individual chips. The heating of one chip does not heat up the
neighboring chips, which is very important in practice for a fine adjustment of the intensity of a chip
without influencing the others. We have already seen the influence of temperature rise on the LED
chip properties in one of the previous chapters.
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Thermal Management of the ACULED® VHL
13
Unlike the ACULED VHL, there are packages available on the market with only one pad for all
the LEDs. In these packages, the heat of each LED chip is widely dissipated by this single pad
and can, therefore, heat up the neighboring chips. With the ACULED VHL, however, the heat of
each chip is spread away from the middle of the ACULED to its outbound and conducted to the
IMS copper body through the dielectric layer via a relative large area. Since this layer is the
highest thermal resistance in the whole package, together with the heat dissipating concept, it
prevents neighboring chips from heating up since the heat must pass this layer twice before
reaching the neighboring pads. In terms of thermal management, this makes the ACULED
VHL/DYO concept superior to other packages when used with different chips or with chips
driven at different currents or modes.
TJ
Figure 9
Schematic diagram of
thermal resistances of the
ACULED VHL/DYO
mounted on a heat-sink
Rth JB
TC
Rth JA
TB
Rth BA
TA
Figure 10
Vertical cross section of
the heat dissipation in the
ACULED VHL at IF
= 700 mA operation
(simulated)
When mounted on heat-sinks, the thermal resistance of the adhesive or thermal grease
between the ACULED and the heat-sink must also be considered for thermal management. In
Figure 9, for example, the resistant Rth BA was divided into the resistant Rth TIM of the thermal
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Thermal Management of the ACULED® VHL
14
grease or interface material (TIM) and Rth hs of the heat-sink itself (e.g. made from aluminium).
Please refer to the chapters entitled “Heat-sink types” and “Heat-sink mounting” later in this
application note for more information.
Thermal Resistances of the ACULED DYO
Figure 9 also applies to the ACULED DYO which uses the same IMS PCB as the ACULED
VHL. But now we have to also consider the specific thermal resistances Rth C of the used chips,
which is already done with the ACULED VHL in the specific datasheets. Figure 11 shows a
more detailed view on the internal thermal situation, which is necessary in understanding the
following calculations. The “package resistance” Rth P was divided into four parallel resistances
Rth Pn with n running from 1 to 4 for each chip pad. Since there is almost no crosstalk between
the pads, as described in the previous section, this approach is allowed. The absence of a
nameable thermal crosstalk also leads to different temperatures TCn on the junction between
pad and chip. Together with the individual thermal resistance Rth Cn of each chip, we can
calculate the individual thermal resistance Rth JBn for each chip according to Equation 9:
Rth JBn = Rth Cn + Rth Pn
(9a)
In practice, the thermal resistances Rth Pn are almost the same in the ACULED DYO/VHL,
namely approx. 20 K/W (Table 3). Inserted into Equation 10, we get the already-known (see
Table 2) combined resistance Rth P = 5 K/W. Since the substrate temperature is also the same
for all paths, the chip with the lowest maximum allowable junction temperature TJn and/or the
chip with the highest resistance Rth Cn limits the maximum allowable substrate temperature
TB max. The values for TJ and Rth C are found in the datasheets of the particular DYO chips.
TJn
Rth JBn
Figure 11
Detailed schematic
diagram of thermal
resistances of the
ACULED VHL/DYO
TCn
TB
However, the calculation of thermal resistance is not the main issue. The most important
concern in thermal calculation is to what temperature TB we must cool down the ACULED to
achieve safe operation of the chips. Following are some examples of how we can calculate TB
for the ACULED DYO with the given information in the datasheets and this application note.
Example 1: ACULED DYO equipped with four equal chips
According to Equations 8 and 9a, the temperature difference ∆TJBn of each single chip path n is:
∆TJBn
= PCn — Rth JBn
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= PCn — (Rth Cn + Rth Pn)
(11a)
Thermal Management of the ACULED® VHL
15
TB = TJn - PCn — (Rth Cn + Rth Pn)
⇔
(11b)
Please note that the substrate temperature TB is the same for all chips at a steady state,
therefore, it’s not indicated by the pad index n. Let’s assume the following values for a blue chip
driven at 350 mA (you can find the values for your configuration in the corresponding chip
datasheets):
•
•
•
•
Rth Pn
Rth C
PC
TJ
≈
=
=
=
20 K/W (according to table 3)
0.7 K/W
1.2 W (@ 350 mA)
125 °C
Inserted in Equation 11b, these values lead to a maximum allowable substrate temperature of
TB max = 99 °C. For the ACULED VHL, this maximum temperature is already found in the specific
datasheets.
Pad
thermal resistance
[K/W]
1
Rth P1 = 20.7
2
Rth P2 = 19.8
3
Rth P3 = 20.7
4
Rth P4 = 19.8
all
Rth P = 5
Table 3
Thermal resistances of the
ACULED VHL/DYO
package for each pad
Example 2: ACULED DYO equipped with four different chips
But what happens if different chips with different thermal resistances are used? Let’s assume
the values for the four chips driven at 700 mA as shown in Table 4. The fifth column shows the
temperature drop between the chip’s pn-junction and the ACULED substrate back side,
according to Equation 11a. Remember that the biggest temperature difference and, thus, the
path with the highest resistance, is determining the maximum allowable board temperature
TB max. In our case, this is the chip on pad 4. Assuming a typical maximum junction temperature
of 125 °C, TB max is 60 °C. To keep the ACULED at this maximum temperature can be
challenging with some applications. The following tips can be helpful if you face a problem with
requiring substantial cooling down:
1) Choose another chip from the chip list with lower values of Rth C and PC at a given current and
wavelength.
2) Drive the chip at lower current. This leads to lower power consumption, according to
Equation 1. You can balance the loss of intensity by choosing a higher intensity rank or using
more chips of this kind.
3) If possible, put the chips with the highest temperature drop on the even pads of the ACULED
board, since these pads have a slightly lower thermal resistance (see Table 3).
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Thermal Management of the ACULED® VHL
16
Pad n
Rth Pn
Rth Cn
PCn
∆TJBn
thermal
cross talk
1
20.7 K/W
1.4 K/W
1.5 W
34 K
0.6 K
2
19.8 K/W
0.7 K/W
2.5 W
52 K
0.5 K
3
20.7 K/W
1.0 K/W
2.5 W
55 K
0.6 K
4
19.8 K/W
1.8 K/W
3.0 W
65 K
0.5 K
Table 4
Example of different
temperature drops due to
different chip parameters
(assigned to example 2 in
the text)
Calculating with thermal cross talk
Each chip on the ACULED also brings some heat to the neighboring chip pads and chips. As pointed
out before, this thermal crosstalk is very low at the ACULED VHL/DYO due to the
separation of the pads and its superior design. But in some applications, it may be from interest to
know how much additional heat results from this thermal crosstalk. Table 5 shows the thermal
crosstalk coefficients Cnm between the chip pads n and m. To calculate the heat rise in each
LED (i.e. the temperature difference ∆TJBn between the junction temperature of the chip placed on
pad n and the substrate temperature), the following matrix is used:
∆T
C
th JB1
∆T
∆T
C
R
JB1
13
C
CR
JB2
=
JB3
21
C
31
R
C1
C
P
24
C
th JB3
—
34
C2
(12)
P
C3
C
∆TJB4
32
14
23
th JB2
C
P
C
12
C
41
42
C
43
R
th JB4
P
C4
Remember Equation 9a to calculate Rth JBn. The matrix can also be written as follows:
∆TJB1 = PC1 — Rth JB1 + PC2 — C12 + PC3 — C13 + PC4 — C14
∆TJB2 = PC1 — C21 + PC2 — Rth JB2 + PC3 — C23 + PC4 — C24
∆TJB3 = PC1 — C31 + PC2 — C32 + PC3 — Rth JB3 + PC4 — C34
∆TJB4 = PC1 — C41 + PC2 — C42 + PC3 — C43 + PC4 — Rth JB4
It depicts the formulas learned from Equation 11a along with additional terms of the heating by
the neighboring chips. Looking at Example 1 from above, the additional thermal heating is only
0.3 K. The last column in Table 4 shows the additional heating for Example 2 with a maximum
heating of 0.6 K (shown is the additional heating of the neighboring three chips at chip pad n).
These numbers show that the heating by thermal crosstalk can be ignored in practice with the
ACULED VHL/DYO and, hence, the influence on wavelength shift, forward voltage rise, and flux
decrease to neighboring chips is almost zero. This makes the ACULED VHL/DYO an excellent
tool when adjusting colors. Figure 12 shows a typical increase ∆TJ of the junction temperature
caused by thermal crosstalk for the ACULED VHL and a comparable configuration with only one
common chip pad (i.e. high thermal crosstalk). All three neighboring chips are driven at 350 mA.
In practice, these values change slightly depending on the specific chip configuration and the
thermal resistances Rth C of the chips. Figure 13 shows the thermal simulation and the crosstalk to
the neighboring chips if only one chip is driven for a common pad and a separated pad
(ACULED VHL) design.
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Thermal Management of the ACULED® VHL
17
Pad m
1
Pad n
2
3
4
Table 5
Matrix of thermal
1
Rth P1 = 20.7
C12 = 0.10
C13 = 0.03
C14 = 0.09
2
C21 = 0.10
Rth P2 = 19.8
C23 = 0.09
C24 = 0.03
3
C31 = 0.03
C32 = 0.09
Rth P3 = 20.7
C34 = 0.10
4
C41 = 0.09
C42 = 0.03
C43 = 0.10
Rth P4 = 19.8
resistances Rth Pn and
crosstalk coefficients Cnm
of the ACULED VHL/DYO
for calculating thermal
crosstalk. All values in
K/W.
Figure 12
30
Influence of thermal
crosstalk to junction
temperature for different
chip pad configurations at
350 mA
25
∆TJ [°C]
20
common chip pad
15
ACULED VHL
10
5
0
0
1
2
3
4
5
6
7
8
9
10
t [s]
Figure 13
Simulation of thermal
crosstalk for different chip
pad configurations (detail)
Left: common chip pad
Right: ACULED VHL with
separated chip pads
Temperature control by NTCs
The safest way of controlling the heat is to measure it. As shown in the previous sections, we
can do this by controlling TB since we can calculate the corresponding junction temperature of
the used chips. The board temperature is measured by thermistors close to the ACULED’s
board. The ACULED DYO allows you to put an NTC chip on one pad of the ACULED to easily
control the temperature close to the chips. The temperature TNTC inside the NTC is nearly the
same as TB. However, in practice there will always be a small difference with TNTC < TB since
heat is also drawn away from the NTC via the soldering pads. The matrix in Equation 12 can
also be used to calculate the heat on the pad of the NTC for a given chip configuration by
setting the PCn value of the NTC to zero:
∆TB NTC = TB - TNTC = PC2 — C12 + PC3 — C13 + PC4 — C14
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(12a)
Thermal Management of the ACULED® VHL
18
In this example chip pad 1 was used to place the NTC. If another pad is used, the numbers of Pn
and Cnm change according to Matrix 12 and Table 5. This temperature drop is typically very low (<<
1 K) and can be ignored in practice. Thus, the NTC is really measuring the board
temperature TB in a steady state.
The principle of an NTC is the change of its internal ohmic resistance R over the temperature T.
As the name indicates, R(T) is a typically negative function, as shown in Figure 14. The specific
values of the NTCs available for the ACULED DYO can be found in the chip datasheets.
Figure 14
Typical curve of resistance
R vs. temperature T of an
NTC
Heat-Sink Calculation
In the previous sections, we learned how to deal with thermal resistances and calculate the
board temperature TB max so that the ACULED back side can be cooled down during operation. Now
we must find an appropriate heat-sink to fulfil this requirement. The heat-sink draws the heat from
the ACULED board and transports it into the ambient environment - typically air, although watercooled heat-sinks can be necessary under extreme conditions. In the next
section, different types of heat-sinks will be explained.
A look at Figure 9 provides the last step of transferring heat from the ACULED substrate with the
temperature TB to the ambient temperature TA that must be accomplished by the heat-sink. It’s very
important to also consider the interface between the heat sink and the ACULED, which is usually a
thermal grease, glue or foil. This interface material (TIM) has its own thermal
resistance Rth TIM that must be added to the thermal resistance of the heat-sink Rth hs. According to
the equations from the previous sections, the temperature difference between the ACULED
substrate and ambient surrounding is calculated using Equation 8c:
∆TBA
⇔
TA
= Ptot — Rth BA
= Ptot — (Rth TIM + Rth hs)
= TB - Ptot — (Rth TIM + Rth hs)
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(8d)
(8e)
Thermal Management of the ACULED® VHL
19
⇔
Rth hs =
T
B
−TA
P
tot
- Rth TIM
(8f)
With TB max inserted in this equation at a given heat-sink and its thermal resistance, a maximum
ambient temperature TA max can be calculated that must not be exceeded. In other words, if the
air around your ACULED module can become hotter than this calculated maximum TA max due
to, for instance, its proximity to a radiator, the chosen heat-sink is not appropriate for operation
of the ACULED. Therefore, it’s also important to consider the environment where the ACULED
is used. Be aware of any additional heating that can occur from other active electronic devices
close to the ACULED, such as motors, micro processors, power electronics, and similar parts.
Subtracting a safety of ∆TSafety ≈ 10 - 20 °C from TB max is recommended in practice:
Rth hs ≈
− ∆T
T
B −TA
Safety
P
- Rth TIM
(8g)
tot
With the Example 1 from the previous section (TB max = 99 °C), an ambient temperature TA of
25 °C, and a safety of ∆TSafety = 20 °C, we get:
99 °C − 25 °C − 20 °C
Rth hs + Rth TIM ≈
1.2 W
= 45 K/W
This thermal resistance can easily be achieved by even smaller heat-sinks, but keep in mind
that a good thermal conduction between the heat-sink and the ACULED (expressed by Rth TIM) is also
necessary. Example 2 (see Table 4) from the last section leads to the following maximum thermal
resistance of the heat-sink:
60 °C − 25 °C − 20 °C
Rth hs + Rth TIM ≈
9.5 W
= 1.5 K/W
This is a much more challenging result that requires a larger, highly-sophisticated heat-sink.
Rth hs is usually provided within the heat-sink datasheet. Remember that this value must be
given as a resistance versus air. In practice, the heat must be transferred to the air (or cooling
liquid) by convection and radiation - a very complex process - so calculating with thermal
resistances, though quite easy, only gives estimated values. Another approach to find an
appropriate heat-sink is by estimating the surface required to remove heat by convection, shown
by the following equation
Ahs ≈
P
tot
α⋅ (∆TBA −∆TSafety )
(13)
with Ahs as the area of the heat-sink exposed to air (or liquid) and α as the heat transfer
coefficient that is typically in the range of 5 - 100 W/(m²—K) against air. With a 5 W ACULED
VHL, for example, a heat-sink area of approx Ahs ≈ 50 cm² is needed at room temperature
(TA = 25 °C). Since heat-sinks have fins to increase the area versus air, the base area of the
heat-sink will be much smaller than this calculated value. The heat transfer coefficient α can be
dramatically increased by a fan. Generally speaking, we can say that the higher the surface of
the heat-sink, the better the heat transfer to the ambient surrounding - and forced air flow (e.g.
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Thermal Management of the ACULED® VHL
20
by a fan) is better than free convection. Most heat sink suppliers provide the necessary
information and specifications that enable you to calculate the appropriate heat-sink according to
the equations mentioned above.
With the formulas we’ve learned so far, we can now also estimate at what maximum power and
current the ACULED can be operated without additional heat-sinks. Equation 8b, inserted into
Equation 13 with the ACULED substrate back side area AACL (1.3 cm²), gives us the following
equation:
∆ TJ −∆T
Ptot ≈
A
1
α⋅A
Safety
+R
(14)
th JB
ACL
⇒ Ptot ≈ α — AACL — (∆TJA - ∆TSafety)
1
with
α⋅A
>> Rth JB
ACL
Assuming a typical Rth JB of 5 K/W for the ACULED VHL, we get a safety power of approx.
200 mW. Of course the ACULED also transports some heat to the air on the front side, which
can be considered when used without heat-sink. Therefore, in practice, it can be operated at
50 mA and 600 mW without additional heat-sinks.
However, all these formulas are only very rough estimations since α is hard to determine in
reality. The most accurate approach is simulating the heat transfer processes with modern
thermal simulation software (see www.nusod.org) that can handle complex structures showing
the critical thermal paths. Figure 15 shows the ACULED VHL in this thermal simulation process done
by finite element simulation software. The results of this process, confirmed by
measurements of the real product, enabled us to improve the internal thermal management of the
ACULED, evidenced, for example, at the low thermal crosstalk.
Figure 15
Thermal simulation of the
ACULED (detail of the chip
area)
Upper left: finite element
mesh model
Upper right: temperature
simulation at all chip
operation
When calculating heat-sinks, we must consider the maximum current IF at which the ACULED
will be driven. This is included in Ptot in the previous formulas (see Equation 1). Figure 16 shows
that chips can be damaged by exceeding the maximum current of the heat-sink in operation. In
this figure, the curves of the pn-junction temperature TJ of a RGYB-ACULED are shown when
driven at IF = 350 mA, respectively, 700 mA on a small heat-sink of 25 x 25 x 18.5 mm³. Though
this heat-sink works properly at lower currents and power consumptions up to approx. Ptot =
6 W, it will fail with the ACULED VHL’s highest current because the junction temperature
exceeds the critical maximum after two minutes of operation.
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Thermal Management of the ACULED® VHL
21
Figure 16
200
180
TJ at different currents IF
with the same heat-sink
vs. time t of operation
Though the heat-sink
works properly at 350 mA
it is not suitable at higher
current.
700 mA
350 mA
160
140
TJ [°C]
120
100
80
60
40
20
0
0
50
100
150
200
250
300
t [s]
Heat-Sink Types
The task of the heat-sink is to transport heat generated by the chips of the ACULED to the
environment or cooling medium. This is typically done by convection of air, but can also be
accomplished by a water-cooled system. Water cooling can be a good solution, particularly
when driving several ACULEDs at high current and, therefore, at high total power consumption (see
Equation 1). In some applications like machine vision, water is already used for other
cooling processes and can, therefore, be easily adapted. Also, the use of Peltier-coolers
(thermoelectric cooling) is an option for specific applications. Figure 19 shows examples of
different heat-sink types.
The main parameters that determine the type and size of heat-sink are the temperature
difference (e.g. ∆TBA), the surface area Ahs , and the flow rate v of the cooling medium (water or
fluid).
Heat-sinks against air
Standard heat-sinks made from a metal with good thermal conductivity, such as aluminium or
copper, are available to the market in a variety of dimensions and profiles. To enlarge the
surface area against air, these heat-sinks are equipped with fins or fingers. To support the
convection by heat radiation, most heat-sinks are black anodized. The principle of these heatsinks is quite easy - the heat-sink is heated by the ACULED and, therefore, is warming the
surrounding air. This warm air is rising, and cooler air follows. The cool air is again warmed by
the heat-sink, and so on. This is known as natural convection. As well as its area Ahs , the
properties of the surface (e.g. material, color) are also important for heat transfer to the air since
they have an influence on the surface emission factor and heat transfer coefficient α.
Heat-sinks and fans
If the natural convection of the air is not enough for cooling, a fan can force the air and strongly
decrease the thermal resistance. Heat-sinks with fans, such as those used with modern microprocessors are also available. See Figure 7 for an example of additional cooling by a fan with
the ACULED VHL.
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Thermal Management of the ACULED® VHL
22
Figure 17 shows how a fan can strongly decrease the thermal resistance Rth hs of a heat-sink by as
much as five times, depending on the air flow velocity vA. The curves indicate this for
different aluminium-made pin fin heat-sinks from the company PINBLOC, all on a 32 x 32 mm² base
with 81 pins at different heights (10, 15 and 20 mm). The power dissipation of the heatsinks
dramatically increases when the air flow is forced by a fan.
Figure 17
Power dissipation P (rising
curves) and heat-sink
resistance Rth hs (falling
curves) vs. air flow velocity
vA for different pin fin heatsinks (small picture).
picture and graphic
courtesy of PINBLOC
(Cologne, Germany)
Heat pipes
Heat pipes provide a very effective way of cooling by using evaporation and condensation of
fluids in a self-contained system. Figure 18 shows the principle of a heat pipe. The heat source
(e.g. the ACULED) heats up the fluid (e.g. water or alcohol) inside the heat pipe on its “warm”
side or end. The fluid, which is in a relative small volume inside the heat pipe, evaporates due to
the heat and is cooled down on the “cold” side through condensation. The cold side is
connected to another external heat-sink or designed for a good cooling by the surrounding
ambient. Since the temperature depends on the low pressure inside the heat pipe, the
temperature drop from the warm to the cold side can be defined by the vacuum.
Heat pipes do not require external water or electrical connections, do not have any moving
parts, and do not need maintenance. They are widely used for cooling high-end
microprocessors, for example, and have a thermal resistance or Rth hs < 1 K/W.
Heat-sinks with liquid cooling
Unlike heat pipes, which use the mechanism of evaporation and condensation of a liquid in a
contained system, a convection system uses the good thermal capacity of water or liquids. The
principle of these coolers is similar to air cooled systems, but now a liquid, rather than air,
transports the heat. Therefore, theses systems require water connection, pumps, and usually a
condenser to continuously cool down the liquid. They are used in applications where water
cooling already exists (for instance at machines) and high amounts of heat are generated such as heat generated by a large number of ACULEDs with a high packaging density.
Some companies provide micro-channel coolers that allow high heat flux capability of approx.
1000 W/cm² (remember, the ACULED VHL has up to approx. 10 W/cm² heat density). These
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Thermal Management of the ACULED® VHL
23
liquid-cooled heat-sinks can take away a high amount of heat in a small footprint and are also used
for laser diode bars.
Figure 18
The principle mechanism of
heat pipes
Figure 19
Examples of different heatsink types for air cooling:
Top:
standard
heat-sinks
Bottom left: ceramic heatsink
Bottom right: heat-sink
with fan
Heat-Sink Mounting
When mounting the ACULED to a heat-sink, the most important issue is a very good thermal
contact between the ACULED’s substrate back side and the heat-sink itself. Figure 9 previously
pointed out the additional thermal resistance Rth TIM for the junction material between the
ACULED and the heat-sink, known as thermal interface material (TIM). This resistance should
be kept as small as possible. Depending on the kind of mechanical connection (clamping,
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Thermal Management of the ACULED® VHL
24
screwing, gluing etc.), the TIM must also provide a good mechanical connection/adhesion. For
general mounting recommendations, please refer to the application note, “Mounting of the
ACULED® Product Family.”
Thermal grease and similar materials
Without any TIM, there can be a risk of having bad thermal conduction between the ACULED and
heat-sink due to air gaps resulting from micro-roughness of the materials. The use of thermal
grease helps avoid these gaps. However, since the thermal conductivity of thermal grease though much better than air - is in the range of 2 - 5 W / (m—K), we must apply it as thinly as
possible. Its task is to displace only the air gaps and any additional (thick) layer
between the ACULED and the heat-sink will increase the thermal resistance. A few 10
micrometers of thermal grease is usually sufficient.
If good adhesion is necessary, a kind of thermal glue should be used. Generally speaking, you could
say that the better the adhesion of the glue, the lower the thermal conductivity. Therefore, the best
heat transfer is achieved by highly-conductive thermal grease and screwing or
clamping the ACULED to the heat-sink. Since the ACULED board is electrically isolated from
the solder pads and from the chip pads, there is no need to use insolating material, which also has
lower thermal conductivity.
Thermal conductivity tapes
Thermal tapes are typically double-sided adhesive films that are easy to handle, but bear the
risk of delamination. Due to their thickness of some 100 s micrometers and a relatively low
thermal conductivity of 1 - 2 W / (m—K), they have a much higher thermal resistance than thermal
grease. Therefore, they should be used only at lower power or less critical applications.
Table 6 shows the properties of typical TIMs between the ACULED and heat-sink. The heat
transition resistance Rα (reciprocal value of the heat transfer coefficient α) can be used to
calculate the thermal resistance Rth TIM of the material when the area ATIM is known (usually the area
of the ACULED AACL):
Rth TIM
TIM
thermal
grease
elastomer
tapes
adhesive
tapes
phase change
materials
thermal glue
= Rα / ATIM
heat
transistion
resistance
Rα [cm²—K/W]
(15)
Table 6
operating
temperature
Properties of different
remarks
thermal interface materials
1-4
up to 250 °C
high thermal conductivity; high pressure
helpful, no mechanical adhesion
lower thermal conductivity, high pressure
required, suited for mass production
lower thermal conductivity, easy mechanical
mounting
0.3 - 0.7
up to 200 °C
Wax-like material with low glass transition
temperature, available as tape or paste
0.3 - 2
- 60 - + 250 °C
thermal grease with glue; easy mechanical
mounting, curing necessary
0.3 - 2
- 60 - + 200 °C
1-3
- 40 - + 200 °C
During mounting, it is important to put some uniform pressure on the ACULED to achieve a
good mechanical and thermal contact and to help the interface material displace the air.
However, be careful not to put pressure on the silicone (refer to application note, “Handling of
LED and Sensor Products Encapsulated by Silicone Resin”). Also consider the “cool” side of the
heat-sink. For example, in an air-cooled system, ensure that the air can flow fast and easily
through the rims and fins of the heat-sink. When using natural convection, the rims of the heat-
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Thermal Management of the ACULED® VHL
25
sink should be vertical for optimized air flow, since warm air flows to the top (see Figure 20).
Also ensure that other heat sources, such as radiators, sunlight, microprocessors, and other
power consumers that can produce heat, are kept away from the LED or heat-sink - or that they
are considered in your thermal calculations. As described before, it is highly recommended to
control the heat by a thermistor on the ACULED, the board, or the heat-sink to avoid
overheating due to damaged fans, broken water tubes (with water cooled systems), or
additional heat sources.
Unlike other SMD-LEDs on the market, it’s not necessary to draw away the heat via the solder
pads. Therefore, the ACULED can be upside-down mounted on a simple FR4-PCB for electrical
connection and have a heat-sink attached to its back side. With this concept, the use of highpriced IMS or ceramic PCBs is not necessary and multi-layer PCBs can even be used. This is
not possible with the previously-mentioned high thermal conductive materials (refer to Table 1
for λth of different PCB materials). However, if possible, the solder pads of the ACULED can be
used to assist the heat transportation (e.g. by designing big and thick copper pads and tracks or
even thermal vias on your PCB where the ACULED is mounted). Refer to Figure 21 for
examples on the recommended method for mounting the ACULED as a through-looking device with
the best thermal and electrical connectivity.
Figure 20
Orientation of the heatsink rims when used with
natural
convection:
best
(right) and less effective
orientations (left, middle)
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Thermal Management of the ACULED® VHL
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Figure 21
Clockwise from upper left:
(1) The ACULED mounted
as through looker on a
FR4 board, small heat-sink
(for 350 mA operation) and
PMMA standard optics.
(2) All parts mounted
together.
(3) 3 assemblies of (2)
connected together
(4) 3 blue ACULED VHL
under operation
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Thermal Management of the ACULED® VHL
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Symbols and Units
The following terms and their typical units are used in the application notes and datasheets of the
ACULED. Please note that not all of these are used in this particular note.
A
[m²]
area, surface
AACL
[cm²]
surface area of ACULED substrate back side
Ahs
[cm²]
surface area of heat-sink
Arad
[mm²]
radiating surface
ATIM
[cm²]
surface area of TIM with usually ATIM = AACL
α
[W/(m²—K)]
heat transfer coefficient
Cnm
[K/W]
thermal crosstalk coefficient between ACULED pads n and m
Ee
[W/m²]
irradiance
EV
[lx]
illuminance [lux]
Φe
[mW]
radiant flux
ΦV
[lm]
luminous flux [lumen]
Ie
[W/sr]
radiant intensity
IF
[mA]
forward current
IFM
[mA]
surge current
IR
[µA]
reverse current
IV
[cd]
luminous intensity [candela]
Le
[W/(m²—sr)]
radiance
LV
[cd/m²]
luminance
λdom
[nm]
dominant wavelength
λpeak
[nm]
peak wavelength
λth
[W/(m—K)]
thermal conductivity
∆λ
[nm]
spectral half bandwidth
η
[%]
efficiency
ηopt
[lm/W]
optical (luminous) efficacy
PCn
[W]
power consumption of chip placed on pad n of the ACULED
Popt
[mW]
output power (optical)
Pth
[W]
thermal power (i.e. the amount of electrical power consumption that
is transformed into heat)
Ptot
[W]
power consumption (electrical) [Watt]
R
[Ω]
(electric) resistance
Rα
[(K—cm²)/W]
heat transition resistance; reciprocal value of the heat transfer
coefficient α
Rth
[K/W]
thermal resistance (general) [Kelvin per Watt]
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Rth BA
[K/W]
thermal resistance from base (B) backside to ambient surrounding
(A)
Rth C
[K/W]
thermal resistance of chip from junction (J) to chip substrate back
side
Rth Cn
[K/W]
thermal resistance of chip from junction (J) to chip substrate back
side at chip placed on pad n of the ACULED
Rth hs
[K/W]
thermal resistance of heat-sink
Rth JA
[K/W]
thermal resistance from junction (J) to ambient air or surrounding (A)
Rth JB
[K/W]
thermal resistance from junction (J) to base (B) back side
Rth JBn
[K/W]
thermal resistance from junction (J) to base (B) back side assigned to
pad n of the ACULED
Rth P
[K/W]
thermal resistance of package from chip pad to base (B) back side,
indicates the mount without chip
Rth Pn
[K/W]
thermal resistance of package from chip pad to base (B) back side
assigned to pad n of the ACULED
Rth TIM
[K/W]
thermal resistance of TIM, usually between ACULED substrate (back
side) and heat-sink
RH
[%]
relative humidity
t
[s]
time
tLife
[h]
life time of LED chip or module
T
[°C] or [K]
temperature (general)
TA
[°C]
ambient temperature
[°C]
maximum allowed ambient temperature
TB
[°C]
base temperature on back side of package (substrate)
TB max
[°C]
maximum allowed base temperature on back side of package
(substrate)
TC
[°C]
temperature on back side of chip substrate
TCn
[°C]
temperature on back side of chip substrate placed on pad n of the
ACULED
TCT
[K]
(correlated) color temperature
TJ
[°C]
temperature at pn-junction of the LED chip; usually referred to the
maximum allowable junction temperature
TJn
[°C]
temperature at pn-junction of the LED chip placed on pad n of the
ACULED. Usually the maximum allowable temperature is meant.
TNTC
[°C]
temperature inside NTC chip
Top
[°C]
operating temperature
Tsold
[°C]
soldering temperature (at backside of the ACULED VHL)
Tst
[°C]
storage temperature
∆TB NTC
[K]
difference between base and temperature and NTC chip temperature
TA
max
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∆TBA
[K]
difference between base and ambient temperature
∆TJA
[K]
difference between junction and ambient temperature
∆TJB
[K]
difference between junction and base temperature [Kelvin]
∆TJBn
[K]
difference between junction temperature of chip placed on pad n of
the ACULED and base temperature
∆TSafety
[K]
additional “safety” temperature to be subtracted from the TB max to be
on the safe side when calculating heat-sink dimensions
TCΦe
[mW/K]
temperature coefficient of radiant flux
TCΦV
[mlm/K]
temperature coefficient of luminous flux
TCλ dom
[nm/K]
temperature coefficient of dominant wavelength
TCλ peak
[nm/K]
temperature coefficient of peak wavelength
TCVF
[mV/K]
temperature coefficient of forward voltage
vA
[m/s]
(cooling) air flow velocity
VF or UF
[V]
forward voltage
VR or UR
[V]
reverse voltage
xn°
[-]
x coordinate in CIE color space for n-degree observer (usually n = 2
is used with light sources like LEDs: x2°)
yn°
[-]
y coordinate in CIE color space for n-degree observer (usually n = 2
is used with light sources like LEDs: y2°)
2ψ
[°]
viewing angle (usually at half of maximum intensity)
Abbreviations
The following abbreviations are used in the application notes. Please note that not all of these
abbreviations are used in this particular note.
ACULED®
The trademarked name for Excelitas’ range of All Color Ultrabright LEDs.
BOM
Bill of material
ccw
Counter clockwise
CCT
Correlated color temperature
CIE
Commission Internationale de l'Eclairage = International Commission on
Illumination
COB
Chip-on-board
CRI
Color rendering index, value to measure the quality of light used for illumination
purposes. 100% means best natural appearance of illuminated colors by the light
source.
DYOTM
Design-Your-Own, indicates an ACULED with customized chip configuration
DUT
Device under test
ESD
Electro-static discharge
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FR4
Flame resistant 4, low cost PCB material made from epoxy resin and fiberglass
mat
FWHM
Full width at half maximum
IMS
Insulated metal substrate, PCB substrate made from aluminum or copper to
provide excellent heat management
IR
Infra-red, radiation above 700 nm within the scope of this application note
LED
Light-emitting diode
NTC
Negative temperature coefficient, used as acronym for an NTC resistant.
Thermistor to control (LED-) temperature
PCB
Printed circuit board
PD
Photo-diode
PMMA
Polymethyl methacrylate, transparent thermoplastic; in optical grade used for
lenses
pn junction
Layer in the LED chip, where positive (p) and negative (n) charged carriers
recombine to light respectively radiation.
PPA
Polyphtalamide (plastic)
PT100
Thermistor made from platin with 100 Ω at 0 °C. Has a positive temperature
coefficient (PTC).
SMD
Surface mount device
TIM
Thermal interface material
UV
Ultra-violet, with LEDs radiation below 405 nm within the scope of this application
note
VHLTM
Very high lumen. This is the name for the newest generation of standard
monochromatic and multi-colored four-chip ACULEDs.
VIS
Visible light, radiation between 405 and 700 nm within the scope of this application
note
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Notes
1.
2.
3.
4.
5.
6.
7.
8.
9.
Excelitas maintains a tolerance of ± 5% on flux and power measurements.
Excelitas maintains a tolerance of ± 2 nm for dominant wavelength measurements.
Excelitas maintains a tolerance of ± 1 nm for peak wavelength measurements.
Excelitas maintains a tolerance of ± 2 K/W for thermal resistance measurements depending on chip
properties.
Due to the special conditions of the manufacturing processes of LEDs, the typical data or calculated
correlations of technical parameters can only reflect statistical figures. These do not necessarily
correspond to the actual parameters of each single product, which could differ from the typical data and
calculated correlations or the typical characteristic line. If requested, e.g. because of technical
improvements, these typ. data will be changed without any further notice.
Proper current derating must be observed to maintain junction temperature below the maximum.
LEDs are not designed to be driven in reverse bias.
All drawings are not to scale.
All dimensions are specified in [mm] if not otherwise noticed.
North American Sales Office
Excelitas Technologies
35 Congress Street
Salem, MA 01970, USA
Telephone: +1 978-745-3200
Toll free: (North America) +1 800-950-3441
Fax: +1 978-745-0894
generalinquiries@excelitas.com
www.excelitas.com
European Headquarters
Excelitas Technologies
Wenzel-Jaksch-Str. 31
65199 Wiesbaden, Germany
Telephone: (+49) 611-492-269
Fax: (+49) 611-492-170
Asia Headquarters
Excelitas Technologies
47 Ayer Rajah Crescent #06-12
Singapore 139947
Telephone: (+65) 6775-2022
Fax: (+65) 6775-1008
For a complete listing of our global offices, visit www.excelitas.com
©2011 Excelitas Technologies Corp. All rights reserved. The Excelitas logo and design are registered trademarks of Excelitas Technologies Corp. ACULED®, VHL™, and DYO™ are trademarks of Excelitas
Technologies Corp. or its subsidiaries, in the United States and other countries. All other trademarks not owned by Excelitas Technologies Corp. or its subsidiaries that are depicted herein are the property of their
respective owners. Excelitas reserves the right to change this document at any time without notice and disclaims liability for editorial, pictorial or typographical errors.
600195_01 APP0707
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