Measurement and Modeling of Thermal Resistance of
High Speed SiGe Heterojunction Bipolar Transistors
J. -S. Rieh, D. Greenberg, B. Jagannathan, G. Freeman, S. Subbanna
IBM Communications R & D Center, Hopewell Junction, NY 12533
Phone: (845)894-7163, Fax: (845)892-3039, Email: jsrieh@us.ibm.com
I. INTRODUCTION
The characteristics of semiconductor devices, as well
as the long-term time dependence of the characteristics, or
reliability, are a function of the temperature. Therefore,
accurate information on the temperature of the devices in
operation, or the junction temperature, is of importance in
predicting the device performance and the degradation of the
device performance. Since the junction temperature is
dictated by the thermal resistance of the device when the
power dissipation is given, an accurate value of the thermal
resistance is critical for the correct junction temperature
estimation, and this requires a precise thermal measurement.
In addition, an accurate modeling of the thermal resistance is
also desired as a tool for the reliable prediction of the thermal
resistance values of arbitrary device structures. A reliable
model would help the optimization of devices and can be
incorporated into scalable device models. Traditionally,
thermal resistance and junction temperature have been issues
for high power devices. Recently, however, there is an
increasing interest in the thermal behavior of high speed
bipolar transistors as the current density of these devices
continues to increase in order to improve their speed of
operation. In this paper, the thermal resistance of high speed
SiGe HBTs is extracted from junction temperature
measurement on various device dimensions, and an analytic
physical model has been developed based on the
measurement data and utilized for the prediction of thermal
resistance for various applications.
elsewhere [1][2]. Thermal resistance can be extracted from
the relation between the power dissipation and the junction
temperature, for which a temperature-sensitive electrical
parameter (TSEP) is utilized in order to link the two
parameters experimentally [3]. The most widely used TSEP is
the base-emitter voltage VBE [4][5] and the current gain β
[6][7]. In this study, a method utilizing VBE was employed for
the extraction, which is briefly described as follows. First, the
device is biased with fixed emitter current IE and collectorbase voltage VCB, and then VBE is measured for different
substrate temperatures TS swept from 283K to 353K. Next,
the device is biased with the same IE at fixed substrate
temperature of TS = 298K, and VBE is measured for different
dissipated power (Pdiss = ICVCE + IBVBE) with VCB changed
from -0.2V to 1.0V. By eliminating VBE from the two
measurements, the relation between temperature and power is
obtained, which turned out to be very linear for the measured
devices as shown in Fig. 1. As a final step, a compensation is
made in order to account for the self-heating effect in the first
measurement, since it related VBE to the substrate temperature
TS, not to the junction temperature Tj. This can be done by
taking y-axis intercept point of the obtained temperaturepower relation, denoted by To in Fig. 1, and shifting the entire
curve upward by the amount of the difference between the
ambient temperature Tamb and To [6]. This completes the
extraction procedure.
350
340
Temperature [K]
Abstract- Thermal resistance has been measured for high speed
SiGe HBT’s with various emitter widths and lengths. The
smaller devices exhibited higher thermal resistance values, but
eventually resulted in lower junction temperature rise for a
given power density. A physical model has been developed which
showed a good agreement with the measurement. The model
indicates that the thermal resistance depends strongly on the
deep trench geometry. The thermal resistance is also anticipated
to increase with the existence of adjacent devices due to a heat
dissipation interference, according to the model.
after co mpensatio n
330
320
310
298K-TO
300
befo re compensatio n
290
280
TO=274K
270
260
II. MEASUREMENT
SiGe HBTs processed with IBM’s 0.18µm BiCMOS
technology, which features fT/fmax of 120GHz/100GHz and
BVCEO/BVCBO of 1.8V/6.5V, were employed for the
measurement. The details about the technology can be found
0
0.02
0.03
0.04
Dissipated Power [W]
Figure 1. Junction temperature shown before and after the
compensation. The device size is 0.2×19.2µm2.
0-7803-7129-1/01/$10.00 (C) 2001 IEEE
110
1
0.01
III. RESULTS
Junction Temperature [K]
345
0.2x6.4um2
335
0.2x2.56um2
330
0.2x1.28um2
325
0.2x0.64um2
315
310
305
300
0.002
0.004
Thermal Resistance [K/W]
12000
10000
8000
6000
4000
2000
0
0
0.002
0.004
0.006
0.008
0.01
0.012
Power Density [W/um2]
Figure 3. Extracted thermal resistance for 0.2µm-wide
devices with various emitter lengths. Same legend as Fig. 2
has been used.
14000
12000
10000
8000
6000
We=0.8um
We=0.28um
4000
We=0.2um
2000
We=0.16um
0
0
2
4
6
8
Reciprocal Emitter Area 1/Ae [1/um2]
observations suggest that the heat dissipation of the devices
can be improved with enlarged deep trench area and broken
emitter fingers. Plotted in Fig. 3 is the thermal resistance Rth
extracted by the relation Tj = Tamb + Rth ⋅ Pdiss, which
maintains constant values over the entire power range
considered. Although the thermal resistance increases rapidly
as the device gets smaller, the junction temperature is still
lower for smaller devices for a given power density as already
discussed before. Figure 4 shows the extracted thermal
resistance for various emitter widths, ranging from 0.16µm up
to 0.8µm, as well as different emitter lengths, as a function of
reciprocal emitter area 1/AE. The message conveyed in this
plot is that for the same device area, or, equivalently, same
power handling capability, smaller emitter width results in
lower thermal resistance. This is the effect of lateral scaling
on thermal resistance.
320
0
14000
Figure 4. Measured (symbols) and calculated (lines) thermal
resistance for various device dimensions.
0.2x19.2um2
340
16000
Thermal Resistance [K/W]
The extraction has been repeated for various device
dimensions with different emitter width WE and length LE.
Figure 2 shows the junction temperatures of 0.2µm-wide
devices with various emitter lengths ranging from 0.64µm to
19.2µm as a function of the density of the power dissipated.
All measurements were made at the identical emitter current
density of JE = 5mA/µm 2 and VCB swept from -0.2V up to 1V.
Considering that the peak fT occurs around this current
density, the dissipated power density shown in the plot well
represents the actual power range in the normal operation of
each device. Given this, the fact that the measured junction
temperature for this power range remains lower than ~345K,
even for the largest device measured (LE = 19.2µm) which is
much longer than those routinely used in practical
applications, strongly indicates the thermal effect of modern
high speed bipolar devices has not reached the level of
concern when operated at nominal bias conditions. It is
interesting to note that the junction temperature is smaller for
the devices with shorter emitter length at a given power
density level. This trend indicates that the heat dissipation is
more effective in shorter devices than in the longer devices.
This can be ascribed to following two factors. Firstly, the
emitter area to deep trench area ratio is smaller for shorter
devices. In other words, the shorter devices have larger deep
trench area per dissipated power, leading to a better heat
dissipation. This reveals the significant role of the deep trench
geometry in the thermal resistance of the devices, as will be
confirmed by the thermal model described in the next section.
Secondly, the effect of the heat dissipation toward the
longitudinal direction (from the shorter edge) is more
pronounced for shorter devices. Although the heat dissipation
toward latitudinal direction (from the longer edge) dominates,
the total heat dissipation still benefits from the longitudinal
components, the fraction of which increases with the
decreasing aspect ratio of the device layout. These
0.006
0.008
0.01
0.012
Power Density [W/um2]
Figure 2. Measured junction temperature for different
emitter sizes shown as a function of power density. The
current density was fixed at JE =5mA/µm2 for the
measurement.
111
2
Heat reservoir at ambient temp
Rterm
Rm2
Rm1
Rs1
V. MODEL PREDICTION
Rs2
dt
dw
S1
Rs3
S2
Rs4
45°
Heat reservoir at ambient temp
Figure 5. Device schematic illustrating metal via, poly
emitter, deep trench, downward heat flow boundary, and
thermal resistor components employed in the model. In
actual calculations, 3-D structure has been incorporated.
IV. MODEL
A model has been developed for the thermal resistance
of bipolar transistors with deep trench isolation. It assumes
heat dissipation through two opposite directions: downward
through Si substrate and upward through metal wiring. For the
downward dissipation, two assumptions have been made.
First, the trench behaves as a heat insulator as the thermal
conductivity of oxide is much lower than that of Si (0.014 vs
1.48 W/cmK at T = 300K). Second, the heat flux is uniformly
confined within a 45°-angled cone originating from a point
heat source. Based on these assumptions, the downward
thermal resistance can be represented by four pieces of
thermal resistors (Rs1, Rs2, Rs3, and Rs4) for transistors with
deep trench. The upward dissipation can be modeled with
three piece resistors, the first two (Rm1 and Rm2) representing
the thermal resistance from poly emitter and metal via,
respectively, and the third piece, designated as Rterm (terminal
resistance), representing the effective thermal resistance from
the via to air, or heat reservoir. Unlike all the other resistor
components, which can be analytically calculated from the
given geometrical structure and thermal conductivity, the
value of Rterm depends on the finishing metal configuration
and it should be treated as an extrinsic element which varies
from case to case. The total thermal resistance is then given
by the parallel combination of the two components, one from
downward and the other from upward heat dissipation, the
final form being given by Rth = (Rs1 + Rs2 + Rs3 + Rs4)||(Rm1 +
Rm2 + Rterm). Two dimensional cross section of the device with
the corresponding thermal resistance components is shown in
Fig. 5, which also illustrates the assumed boundary of heat
flux. The total thermal resistance was calculated based on the
three dimensional geographical structure of the devices and
the appropriate thermal conductivity of the materials, and it is
compared with the measured values in Fig. 4 as represented
by lines. Note that one single value of Rterm, determined from
112
3
With the help of the developed physical model, the
effect of the structural variation of devices and the existence
of adjacent devices can be predicted.
Both lateral and vertical variation of the device
structure influence the thermal resistance. The effect of the
lateral variation of emitter dimension has been exhibited by
both measurement and model in Fig. 3 and Fig 4, which
basically indicates that Rth decreases with increasing emitter
length and emitter width. The deep trench area dependence of
the thermal resistance was also strongly suggested by the
measurement, and the model supports and clearly explains the
idea. Figure 6 depicts the variation of Rth due to the scaling of
the two deep trench parameter S1 and S2, which are the
shorter and longer distance between deep trench and emitter
edges, respectively, as defined in Fig. 5. The extension of S1
and S2 reduces Rth, as it results in the increase of the deep
trench area, allowing a wider heat dissipation path. The
enlarged deep trench area, however, causes an increase in the
collector to substrate capacitance Ccs, leading to a potential
electrical performance degradation. This implies that there is
a trade-off between the thermal and electrical optimization of
the devices. In this context, the extension of S1 looks more
favorable than S2, as it involves smaller increase of the deep
trench area for the same amount of Rth reduction.
Also shown in Fig. 6 is the effect of the scaling of
vertical dimensions - deep trench depth dt and wafer thickness
dw as defined in Fig. 5. The reduction of deep trench depth
leads to a smaller Rth, as it has an equivalent effect of
widening the heat dissipation path. The total elimination of
deep trench turned out to reduce Rth by ~40%, which is
consistent with the measurement results from [8]. The effect
2
1.8
1.6
1.4
Normalized Rth
Metal
Finishing
the fitting between the model and the measurement, was
employed for the entire range of WE and it shows a fairly
good agreement for all WE values measured.
1.2
1
0.8
0.6
S1
S2
dt
dw
0.4
0.2
0
0.0
0.5
1.0
1.5
2.0
Normalized dimension
Figure 6. Model-predicted thermal resistance for several
structural dimension variations. The definition of the
varied parameters can be found in Fig. 5.
devices and shorter distance. This suggests that a good
thermal design would require not only optimized device
layout but also optimized circuit layout in thermal point of
view.
VI. CONCLUSIONS
Thermal resistance has been extracted for high speed
SiGe HBT’s with various emitter widths and lengths, and a
physical model has been developed which shows a good
agreement with the measurement. The narrower and shorter
devices exhibited lower junction temperature rise for a given
power density, although they have higher thermal resistance,
making small devices more attractive in thermal point of
view. The junction temperature rise for the longest device
measured, however, was still within acceptable range when
operated at nominal bias conditions. The model indicates that
the deep trench geometry, both lateral and vertical, has a
strong impact on the thermal resistance, and there exists a
trade-off between the electrical and thermal behavior of the
devices. The thermal resistance is expected to increase with
the existence of adjacent devices due to heat dissipation
interference, suggesting that a thermal consideration is needed
for circuit layout as well as device layout.
Figure 7. A modified model depicting the effect of
adjacent devices in the array. The heat dissipation path
is truncated in order to account for the thermal
interference between devices.
3
Le=15um
Le=10um
Normalized Rth
2.5
Le=5um
2-D array
Le=2.5um
2
1.5
REFERENCES
1
1-D array
0.5
0
10
20
30
40
50
60
Edge to edge separation [um]
Figure 8. Calculated thermal resistance of devices with
various emitter length LE, located in the middle of 1-D
and 2-D array with different device edge-to-edge
separations. Thermal resistance values are normalized to
those of isolated devices.
of wafer thinning depends on how closely the devices are
packed to each other. The details of the device packing effect
will be provided shortly. Assumed in the curve presented in
Fig. 6 is the average device-to-device distance of 50µm, while
shorter distances would exhibit a more prominent effect of
wafer thinning.
The thermal measurement and model discussed up to
now are all based on isolated devices. In actual circuit
operations, however, the heat dissipation of a device may
interfere with that of adjacent devices in operation, leading to
an increase in the effective thermal resistance. In order to
account for the packing effect, a modified model was
employed in which the heat dissipation path from a device is
truncated due to the interference with adjacent device as
depicted in Fig. 7. The effective thermal resistance was
calculated for a device placed in the middle of 1-D and 2-D
array with various device-to-device distances and emitter
lengths as shown in Fig. 8. The calculated results indicate that
the packing effect is moderate when the device is surrounded
by 2 sides only (1-D array), but it becomes considerable when
surrounded by 4 sides (2-D array), especially for longer
113
4
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