Virtex-4 Memory Interface Noise Comparison—a Case Study
Greg Lara, Virtex Solutions Marketing
Introduction
To satisfy the requirements for greater data throughput, designers are turning to the latest highspeed memory devices, including DDR2 SDRAM and QDR II SRAM. One key requirement for
building successful high-bandwidth memory interfaces is to minimize switching noise. Wide
busses combined with high-drive, high-slew-rate I/Os create the potential for simultaneous
switching noise that can lead to unreliable interfaces and even system failure. Fortunately, FPGA
designers have at their disposal many tools to help them control noise when building highbandwidth memory interfaces. The latest innovation is FPGA packaging that helps to control
noise at the chip level.
Lab measurements and simulations conducted by renowned signal integrity expert Dr. Howard
Johnson show that the advanced packaging technology of Virtex™-4 FPGAs provides the benefit
of up to seven times less crosstalk compared to competing 90nm FPGAs. To see how this
advantage applies to high-bandwidth memory interfaces, Xilinx recently performed laboratory
measurements comparing Virtex-4 FPGAs and Stratix-II FPGAs. The results confirm that Virtex-4
FPGAs produce significantly less SSO noise.
Test Setup
Using the Xilinx ML481 evaluation board, we implemented 72-bit interfaces to DDR2 SDRAM and
QDR II SRAM devices. Xilinx designed the ML481 board specifically for the purpose of
conducting “apples-to-apples” comparisons between Virtex-4 and Stratix II FPGAs. The board is
divided into two sides; one side holds a Virtex-4 XC4VLX60 in an FF1148 package and the other
a Stratix II EP2S60 FPGA in F1020 package. The two halves are completely isolated electrically,
with separate power and ground planes and separate power supplies.
The ML481 board contains several purpose-built test points. Controlled impedance 50 ohm traces
route from aggressor and victim pins to SMA connector on the board. We connected 50 ohm
coaxial cables between the SMA connectors and the oscilloscope used to capture the data shown
in the figures below.
Interface test frequencies:
o DDR2 SDRAM: 267MHz SSTL18 Class 2
o QDR II SRAM: 300 MHz HSTL18 Class 2
Test Results
The figures below show the oscilloscope plots of SSO noise measured at victim pins on the
Virtex-4 and Stratix II FPGAs mounted on the ML481 board when implementing DDR2 SDRAM
and QDR II SRAM interfaces
Virtex-4 Memory Interfaces Noise Comparison
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DDR2 SDRAM
72-bit Interface, SSTL18 Class 2 @ 534 Mbps
Stratix II
Virtex-4
200 mV/div
200 mV/div
197 mV p-p
950 mV p-p
X
950 mV peak-to-peak noise
197 mV peak-to-peak noise
Figure 1. Virtex-4 FPGAs demonstrate significantly less SSO noise than Stratix II FPGAs
for a 72-bit DDR2 SDRAM interface.
QDR II SRAM / FCRAM II / RLDRAMII
72-bit Interface, HSTL18 Class 2 @ 300MHz
Stratix II
200 mV/div
Virtex-4
200 mV/div
1030 mV p-p
1030 mV peak-to-peak noise
110 mV p-p
110 mV peak-to-peak noise
Figure 2. Virtex-4 FPGAs demonstrate significantly less SSO noise than Stratix II FPGAs
for a 72-bit QDR II SRAM interface.
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Conclusion
The latest laboratory measurements confirm that Xilinx Virtex-4 FPGAs deliver a significant signal
integrity advantage when building high-bandwidth memory interfaces with the latest highperformance memory devices.
The SparseChevron pinout places a power and ground pin pair next to every I/O. Just as a welldesigned high-speed connector interleaves ground pins in between every signal pin, the
SparseChevron pinout provides a low-impedance return path for switching I/O signal energy to
shield neighboring signal pins from undesirable inductive crosstalk. By designing with Virtex-4
FPGAs, engineers can improve system-level signal integrity by controlling noise at the chip level.
To Learn More
For more information on the signal integrity benefits provided by Virtex-4 SparseCheveron
packaging, visit www.xilinx.com/virtex4/si. There you can download reports and listen to ondemand webcast seminars by Dr. Howard Johnson regarding his investigation and analysis of the
signal integrity properties of Virtex-4 FPGAs.
For more information on Virtex-4 advanced memory interface solutions, visit
www.xilinx.com/memory .
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